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1 | /* |
1 | /* |
2 | * Copyright (C) 2005 Jakub Jermar |
2 | * Copyright (C) 2005 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup sparc64interrupt |
29 | /** @addtogroup sparc64interrupt |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | */ |
33 | */ |
34 | 34 | ||
35 | #include <arch/interrupt.h> |
35 | #include <arch/interrupt.h> |
- | 36 | #include <arch/trap/interrupt.h> |
|
36 | #include <interrupt.h> |
37 | #include <interrupt.h> |
- | 38 | #include <arch/drivers/fhc.h> |
|
37 | #include <arch/types.h> |
39 | #include <arch/types.h> |
38 | #include <debug.h> |
40 | #include <debug.h> |
39 | #include <ipc/sysipc.h> |
41 | #include <ipc/sysipc.h> |
- | 42 | #include <arch/asm.h> |
|
- | 43 | #include <arch/barrier.h> |
|
- | 44 | ||
- | 45 | #include <genarch/kbd/z8530.h> |
|
40 | 46 | ||
41 | /** Register Interrupt Level Handler. |
47 | /** Register Interrupt Level Handler. |
42 | * |
48 | * |
43 | * @param n Interrupt Level (1 - 15). |
49 | * @param n Interrupt Level (1 - 15). |
44 | * @param name Short descriptive string. |
50 | * @param name Short descriptive string. |
45 | * @param f Handler. |
51 | * @param f Handler. |
46 | */ |
52 | */ |
47 | void interrupt_register(int n, const char *name, iroutine f) |
53 | void interrupt_register(int n, const char *name, iroutine f) |
48 | { |
54 | { |
49 | ASSERT(n >= IVT_FIRST && n <= IVT_ITEMS); |
55 | ASSERT(n >= IVT_FIRST && n <= IVT_ITEMS); |
50 | 56 | ||
51 | exc_register(n - 1, name, f); |
57 | exc_register(n - 1, name, f); |
52 | } |
58 | } |
53 | 59 | ||
54 | /* Reregister irq to be IPC-ready */ |
60 | /* Reregister irq to be IPC-ready */ |
55 | void irq_ipc_bind_arch(unative_t irq) |
61 | void irq_ipc_bind_arch(unative_t irq) |
56 | { |
62 | { |
57 | panic("not implemented\n"); |
63 | panic("not implemented\n"); |
58 | /* TODO */ |
64 | /* TODO */ |
59 | } |
65 | } |
60 | 66 | ||
- | 67 | void interrupt(void) |
|
- | 68 | { |
|
- | 69 | uint64_t intrcv; |
|
- | 70 | uint64_t data0; |
|
- | 71 | ||
- | 72 | intrcv = asi_u64_read(ASI_INTR_RECEIVE, 0); |
|
- | 73 | data0 = asi_u64_read(ASI_UDB_INTR_R, ASI_UDB_INTR_R_DATA_0); |
|
- | 74 | ||
- | 75 | switch (data0) { |
|
- | 76 | #ifdef CONFIG_Z8530 |
|
- | 77 | case Z8530_INTRCV_DATA0: |
|
61 | /** @} |
78 | /* |
- | 79 | * So far, we know we got this interrupt through the FHC. |
|
- | 80 | * Since we don't have enough information about the FHC and |
|
- | 81 | * because the interrupt looks like level sensitive, |
|
- | 82 | * we cannot handle it by scheduling one of the level |
|
- | 83 | * interrupt traps. Call the interrupt handler directly. |
|
62 | */ |
84 | */ |
- | 85 | fhc_uart_reset(); |
|
- | 86 | z8530_interrupt(); |
|
- | 87 | break; |
|
- | 88 | #endif |
|
- | 89 | } |
|
- | 90 | ||
- | 91 | membar(); |
|
- | 92 | asi_u64_write(ASI_INTR_RECEIVE, 0, 0); |
|
- | 93 | } |
|
63 | 94 | ||
- | 95 | /** @} |
|
- | 96 | */ |
|
64 | 97 |