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1 | /* |
1 | /* |
2 | * Copyright (C) 2005 Jakub Jermar |
2 | * Copyright (C) 2005 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup sparc64 |
29 | /** @addtogroup sparc64 |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | */ |
33 | */ |
34 | 34 | ||
35 | #include <arch.h> |
35 | #include <arch.h> |
36 | #include <debug.h> |
36 | #include <debug.h> |
37 | #include <arch/trap/trap.h> |
37 | #include <arch/trap/trap.h> |
38 | #include <arch/console.h> |
38 | #include <arch/console.h> |
39 | #include <arch/drivers/tick.h> |
39 | #include <arch/drivers/tick.h> |
40 | #include <proc/thread.h> |
40 | #include <proc/thread.h> |
41 | #include <console/console.h> |
41 | #include <console/console.h> |
42 | #include <arch/boot/boot.h> |
42 | #include <arch/boot/boot.h> |
43 | #include <arch/arch.h> |
43 | #include <arch/arch.h> |
44 | #include <arch/mm/tlb.h> |
44 | #include <arch/mm/tlb.h> |
45 | #include <mm/asid.h> |
45 | #include <mm/asid.h> |
46 | 46 | ||
47 | bootinfo_t bootinfo; |
47 | bootinfo_t bootinfo; |
48 | 48 | ||
49 | void arch_pre_mm_init(void) |
49 | void arch_pre_mm_init(void) |
50 | { |
50 | { |
51 | trap_init(); |
51 | trap_init(); |
52 | tick_init(); |
52 | tick_init(); |
53 | } |
53 | } |
54 | 54 | ||
55 | void arch_post_mm_init(void) |
55 | void arch_post_mm_init(void) |
56 | { |
56 | { |
57 | standalone_sparc64_console_init(); |
57 | standalone_sparc64_console_init(); |
58 | } |
58 | } |
59 | 59 | ||
60 | void arch_pre_smp_init(void) |
60 | void arch_pre_smp_init(void) |
61 | { |
61 | { |
62 | } |
62 | } |
63 | 63 | ||
64 | void arch_post_smp_init(void) |
64 | void arch_post_smp_init(void) |
65 | { |
65 | { |
66 | thread_t *t; |
66 | thread_t *t; |
67 | 67 | ||
68 | /* |
68 | /* |
69 | * Create thread that polls keyboard. |
69 | * Create thread that polls keyboard. |
70 | */ |
70 | */ |
71 | t = thread_create(kkbdpoll, NULL, TASK, 0, "kkbdpoll"); |
71 | t = thread_create(kkbdpoll, NULL, TASK, 0, "kkbdpoll"); |
72 | if (!t) |
72 | if (!t) |
73 | panic("cannot create kkbdpoll\n"); |
73 | panic("cannot create kkbdpoll\n"); |
74 | thread_ready(t); |
74 | thread_ready(t); |
75 | } |
75 | } |
76 | 76 | ||
77 | void calibrate_delay_loop(void) |
77 | void calibrate_delay_loop(void) |
78 | { |
78 | { |
79 | } |
79 | } |
80 | 80 | ||
81 | /** Acquire console back for kernel |
81 | /** Acquire console back for kernel |
82 | * |
82 | * |
83 | */ |
83 | */ |
84 | void arch_grab_console(void) |
84 | void arch_grab_console(void) |
85 | { |
85 | { |
86 | } |
86 | } |
87 | /** Return console to userspace |
87 | /** Return console to userspace |
88 | * |
88 | * |
89 | */ |
89 | */ |
90 | void arch_release_console(void) |
90 | void arch_release_console(void) |
91 | { |
91 | { |
92 | } |
92 | } |
93 | 93 | ||
94 | /** Take over TLB and trap table. |
94 | /** Take over TLB and trap table. |
95 | * |
95 | * |
96 | * Initialize ITLB and DTLB and switch to kernel |
96 | * Initialize ITLB and DTLB and switch to kernel |
97 | * trap table. |
97 | * trap table. |
98 | * |
98 | * |
99 | * The goal of this function is to disable MMU |
99 | * First, demap context 0 and install the |
100 | * so that both TLBs can be purged and new |
- | |
101 | * kernel 4M locked entry can be installed. |
100 | * global 4M locked kernel mapping. |
102 | * After TLB is initialized, MMU is enabled |
- | |
103 | * again. |
- | |
104 | * |
101 | * |
- | 102 | * Second, prepare a temporary IMMU mapping in |
|
105 | * Switching MMU off imposes the requirement for |
103 | * context 1, switch to it, demap context 0, |
- | 104 | * install the global 4M locked kernel mapping |
|
106 | * the kernel to run in identity mapped environment. |
105 | * in context 0 and switch back to context 0. |
107 | * |
106 | * |
108 | * @param base Base address that will be hardwired in both TLBs. |
107 | * @param base Base address that will be hardwired in both TLBs. |
109 | */ |
108 | */ |
110 | void take_over_tlb_and_tt(uintptr_t base) |
109 | void take_over_tlb_and_tt(uintptr_t base) |
111 | { |
110 | { |
112 | tlb_tag_access_reg_t tag; |
111 | tlb_tag_access_reg_t tag; |
113 | tlb_data_t data; |
112 | tlb_data_t data; |
114 | frame_address_t fr; |
113 | frame_address_t fr; |
115 | page_address_t pg; |
114 | page_address_t pg; |
116 | 115 | ||
117 | fr.address = base; |
- | |
118 | pg.address = base; |
- | |
119 | - | ||
120 | immu_disable(); |
- | |
121 | dmmu_disable(); |
- | |
122 | - | ||
123 | /* |
116 | /* |
124 | * Demap everything, especially OpenFirmware. |
117 | * Switch to the kernel trap table. |
125 | */ |
118 | */ |
126 | itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0); |
119 | trap_switch_trap_table(); |
- | 120 | ||
- | 121 | fr.address = base; |
|
127 | dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0); |
122 | pg.address = base; |
128 | 123 | ||
129 | /* |
124 | /* |
130 | * We do identity mapping of 4M-page at 4M. |
125 | * We do identity mapping of 4M-page at 4M. |
131 | */ |
126 | */ |
132 | tag.value = ASID_KERNEL; |
127 | tag.value = 0; |
- | 128 | tag.context = 0; |
|
133 | tag.vpn = pg.vpn; |
129 | tag.vpn = pg.vpn; |
134 | 130 | ||
135 | itlb_tag_access_write(tag.value); |
- | |
136 | dtlb_tag_access_write(tag.value); |
- | |
137 | - | ||
138 | data.value = 0; |
131 | data.value = 0; |
139 | data.v = true; |
132 | data.v = true; |
140 | data.size = PAGESIZE_4M; |
133 | data.size = PAGESIZE_4M; |
141 | data.pfn = fr.pfn; |
134 | data.pfn = fr.pfn; |
142 | data.l = true; |
135 | data.l = true; |
143 | data.cp = 1; |
136 | data.cp = 1; |
144 | data.cv = 1; |
137 | data.cv = 0; |
145 | data.p = true; |
138 | data.p = true; |
146 | data.w = true; |
139 | data.w = true; |
147 | data.g = true; |
140 | data.g = true; |
148 | 141 | ||
- | 142 | /* |
|
- | 143 | * Straightforwardly demap DMUU context 0, |
|
- | 144 | * and replace it with the locked kernel mapping. |
|
- | 145 | */ |
|
- | 146 | dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0); |
|
149 | itlb_data_in_write(data.value); |
147 | dtlb_tag_access_write(tag.value); |
150 | dtlb_data_in_write(data.value); |
148 | dtlb_data_in_write(data.value); |
151 | 149 | ||
152 | /* |
150 | /* |
153 | * Register window traps can occur before MMU is enabled again. |
- | |
154 | * This ensures that any such traps will be handled from |
151 | * Install kernel code mapping in context 1 |
155 | * kernel identity mapped trap handler. |
152 | * and switch to it. |
156 | */ |
153 | */ |
- | 154 | tag.context = 1; |
|
- | 155 | data.g = false; |
|
- | 156 | itlb_tag_access_write(tag.value); |
|
- | 157 | itlb_data_in_write(data.value); |
|
157 | trap_switch_trap_table(); |
158 | mmu_primary_context_write(1); |
158 | 159 | ||
- | 160 | /* |
|
159 | tlb_invalidate_all(); |
161 | * Demap old context 0. |
- | 162 | */ |
|
- | 163 | itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0); |
|
160 | 164 | ||
- | 165 | /* |
|
- | 166 | * Install the locked kernel mapping in context 0 |
|
- | 167 | * and switch to it. |
|
- | 168 | */ |
|
161 | dmmu_enable(); |
169 | tag.context = 0; |
162 | immu_enable(); |
170 | data.g = true; |
- | 171 | itlb_tag_access_write(tag.value); |
|
- | 172 | itlb_data_in_write(data.value); |
|
- | 173 | mmu_primary_context_write(0); |
|
163 | } |
174 | } |
164 | 175 | ||
165 | /** @} |
176 | /** @} |
166 | */ |
177 | */ |
167 | 178 |