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1 | /* |
1 | /* |
2 | * Copyright (C) 2006 Jakub Jermar |
2 | * Copyright (C) 2006 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup sparc64 |
29 | /** @addtogroup sparc64 |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | */ |
33 | */ |
34 | 34 | ||
35 | #include <smp/ipi.h> |
35 | #include <smp/ipi.h> |
36 | #include <cpu.h> |
36 | #include <cpu.h> |
37 | #include <arch/cpu.h> |
37 | #include <arch/cpu.h> |
38 | #include <arch/asm.h> |
38 | #include <arch/asm.h> |
39 | #include <config.h> |
39 | #include <config.h> |
40 | #include <mm/tlb.h> |
40 | #include <mm/tlb.h> |
41 | #include <arch/interrupt.h> |
41 | #include <arch/interrupt.h> |
42 | #include <arch/trap/interrupt.h> |
42 | #include <arch/trap/interrupt.h> |
43 | #include <arch/barrier.h> |
43 | #include <arch/barrier.h> |
44 | #include <preemption.h> |
44 | #include <preemption.h> |
45 | #include <time/delay.h> |
45 | #include <time/delay.h> |
46 | #include <panic.h> |
46 | #include <panic.h> |
47 | 47 | ||
48 | /** Invoke function on another processor. |
48 | /** Invoke function on another processor. |
49 | * |
49 | * |
50 | * Currently, only functions without arguments are supported. |
50 | * Currently, only functions without arguments are supported. |
51 | * Supporting more arguments in the future should be no big deal. |
51 | * Supporting more arguments in the future should be no big deal. |
52 | * |
52 | * |
53 | * Interrupts must be disabled prior to this call. |
53 | * Interrupts must be disabled prior to this call. |
54 | * |
54 | * |
55 | * @param mid MID of the target processor. |
55 | * @param mid MID of the target processor. |
56 | * @param func Function to be invoked. |
56 | * @param func Function to be invoked. |
57 | */ |
57 | */ |
58 | static void cross_call(int mid, void (* func)(void)) |
58 | static void cross_call(int mid, void (* func)(void)) |
59 | { |
59 | { |
60 | uint64_t status; |
60 | uint64_t status; |
61 | bool done; |
61 | bool done; |
62 | 62 | ||
63 | /* |
63 | /* |
64 | * This functin might enable interrupts for a while. |
64 | * This function might enable interrupts for a while. |
65 | * In order to prevent migration to another processor, |
65 | * In order to prevent migration to another processor, |
66 | * we explicitly disable preemption. |
66 | * we explicitly disable preemption. |
67 | */ |
67 | */ |
68 | 68 | ||
69 | preemption_disable(); |
69 | preemption_disable(); |
70 | 70 | ||
71 | status = asi_u64_read(ASI_INTR_DISPATCH_STATUS, 0); |
71 | status = asi_u64_read(ASI_INTR_DISPATCH_STATUS, 0); |
72 | if (status & INTR_DISPATCH_STATUS_BUSY) |
72 | if (status & INTR_DISPATCH_STATUS_BUSY) |
73 | panic("Interrupt Dispatch Status busy bit set\n"); |
73 | panic("Interrupt Dispatch Status busy bit set\n"); |
74 | 74 | ||
75 | do { |
75 | do { |
76 | asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_0, (uintptr_t) func); |
76 | asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_0, (uintptr_t) func); |
77 | asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_1, 0); |
77 | asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_1, 0); |
78 | asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_2, 0); |
78 | asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_2, 0); |
79 | asi_u64_write(ASI_UDB_INTR_W, (mid << INTR_VEC_DISPATCH_MID_SHIFT) | ASI_UDB_INTR_W_DISPATCH, 0); |
79 | asi_u64_write(ASI_UDB_INTR_W, (mid << INTR_VEC_DISPATCH_MID_SHIFT) | ASI_UDB_INTR_W_DISPATCH, 0); |
80 | 80 | ||
81 | membar(); |
81 | membar(); |
82 | 82 | ||
83 | do { |
83 | do { |
84 | status = asi_u64_read(ASI_INTR_DISPATCH_STATUS, 0); |
84 | status = asi_u64_read(ASI_INTR_DISPATCH_STATUS, 0); |
85 | } while (status & INTR_DISPATCH_STATUS_BUSY); |
85 | } while (status & INTR_DISPATCH_STATUS_BUSY); |
86 | 86 | ||
87 | done = !(status & INTR_DISPATCH_STATUS_NACK); |
87 | done = !(status & INTR_DISPATCH_STATUS_NACK); |
88 | if (!done) { |
88 | if (!done) { |
89 | /* |
89 | /* |
90 | * Prevent deadlock. |
90 | * Prevent deadlock. |
91 | */ |
91 | */ |
92 | (void) interrupts_enable(); |
92 | (void) interrupts_enable(); |
93 | delay(20 + (tick_read() & 0xff)); |
93 | delay(20 + (tick_read() & 0xff)); |
94 | (void) interrupts_disable(); |
94 | (void) interrupts_disable(); |
95 | } |
95 | } |
96 | } while (done); |
96 | } while (done); |
97 | 97 | ||
98 | preemption_enable(); |
98 | preemption_enable(); |
99 | } |
99 | } |
100 | 100 | ||
101 | /* |
101 | /* |
102 | * Deliver IPI to all processors except the current one. |
102 | * Deliver IPI to all processors except the current one. |
103 | * |
103 | * |
104 | * The sparc64 architecture does not support any group addressing |
104 | * The sparc64 architecture does not support any group addressing |
105 | * which is found, for instance, on ia32 and amd64. Therefore we |
105 | * which is found, for instance, on ia32 and amd64. Therefore we |
106 | * need to simulate the broadcast by sending the message to |
106 | * need to simulate the broadcast by sending the message to |
107 | * all target processors step by step. |
107 | * all target processors step by step. |
108 | * |
108 | * |
109 | * We assume that interrupts are disabled. |
109 | * We assume that interrupts are disabled. |
110 | * |
110 | * |
111 | * @param ipi IPI number. |
111 | * @param ipi IPI number. |
112 | */ |
112 | */ |
113 | void ipi_broadcast_arch(int ipi) |
113 | void ipi_broadcast_arch(int ipi) |
114 | { |
114 | { |
115 | int i; |
115 | int i; |
116 | 116 | ||
117 | void (* func)(void); |
117 | void (* func)(void); |
118 | 118 | ||
119 | switch (ipi) { |
119 | switch (ipi) { |
120 | case IPI_TLB_SHOOTDOWN: |
120 | case IPI_TLB_SHOOTDOWN: |
121 | func = tlb_shootdown_ipi_recv; |
121 | func = tlb_shootdown_ipi_recv; |
122 | break; |
122 | break; |
123 | default: |
123 | default: |
124 | panic("Unknown IPI (%d).\n", ipi); |
124 | panic("Unknown IPI (%d).\n", ipi); |
125 | break; |
125 | break; |
126 | } |
126 | } |
127 | 127 | ||
128 | /* |
128 | /* |
129 | * As long as we don't support hot-plugging |
129 | * As long as we don't support hot-plugging |
130 | * or hot-unplugging of CPUs, we can walk |
130 | * or hot-unplugging of CPUs, we can walk |
131 | * the cpus array and read processor's MID |
131 | * the cpus array and read processor's MID |
132 | * without locking. |
132 | * without locking. |
133 | */ |
133 | */ |
134 | 134 | ||
135 | for (i = 0; i < config.cpu_active; i++) { |
135 | for (i = 0; i < config.cpu_active; i++) { |
136 | if (&cpus[i] == CPU) |
136 | if (&cpus[i] == CPU) |
137 | continue; /* skip the current CPU */ |
137 | continue; /* skip the current CPU */ |
138 | 138 | ||
139 | cross_call(cpus[i].arch.mid, func); |
139 | cross_call(cpus[i].arch.mid, func); |
140 | } |
140 | } |
141 | } |
141 | } |
142 | 142 | ||
143 | /** @} |
143 | /** @} |
144 | */ |
144 | */ |
145 | 145 |