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1 | /* |
1 | /* |
2 | * Copyright (C) 2005 Jakub Jermar |
2 | * Copyright (C) 2005 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup sparc64mm |
29 | /** @addtogroup sparc64mm |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | */ |
33 | */ |
34 | 34 | ||
35 | #include <arch/mm/tlb.h> |
35 | #include <arch/mm/tlb.h> |
36 | #include <mm/tlb.h> |
36 | #include <mm/tlb.h> |
37 | #include <mm/as.h> |
37 | #include <mm/as.h> |
38 | #include <mm/asid.h> |
38 | #include <mm/asid.h> |
39 | #include <arch/mm/frame.h> |
39 | #include <arch/mm/frame.h> |
40 | #include <arch/mm/page.h> |
40 | #include <arch/mm/page.h> |
41 | #include <arch/mm/mmu.h> |
41 | #include <arch/mm/mmu.h> |
42 | #include <arch/interrupt.h> |
42 | #include <arch/interrupt.h> |
- | 43 | #include <interrupt.h> |
|
43 | #include <arch.h> |
44 | #include <arch.h> |
44 | #include <print.h> |
45 | #include <print.h> |
45 | #include <arch/types.h> |
46 | #include <arch/types.h> |
46 | #include <typedefs.h> |
47 | #include <typedefs.h> |
47 | #include <config.h> |
48 | #include <config.h> |
48 | #include <arch/trap/trap.h> |
49 | #include <arch/trap/trap.h> |
49 | #include <panic.h> |
50 | #include <panic.h> |
50 | #include <arch/asm.h> |
51 | #include <arch/asm.h> |
51 | #include <symtab.h> |
52 | #include <symtab.h> |
52 | 53 | ||
53 | static void dtlb_pte_copy(pte_t *t, bool ro); |
54 | static void dtlb_pte_copy(pte_t *t, bool ro); |
54 | static void itlb_pte_copy(pte_t *t); |
55 | static void itlb_pte_copy(pte_t *t); |
55 | static void do_fast_instruction_access_mmu_miss_fault(istate_t *istate, const char *str); |
56 | static void do_fast_instruction_access_mmu_miss_fault(istate_t *istate, const char *str); |
56 | static void do_fast_data_access_mmu_miss_fault(istate_t *istate, tlb_tag_access_reg_t tag, const char *str); |
57 | static void do_fast_data_access_mmu_miss_fault(istate_t *istate, tlb_tag_access_reg_t tag, const char *str); |
57 | static void do_fast_data_access_protection_fault(istate_t *istate, tlb_tag_access_reg_t tag, const char *str); |
58 | static void do_fast_data_access_protection_fault(istate_t *istate, tlb_tag_access_reg_t tag, const char *str); |
58 | 59 | ||
59 | char *context_encoding[] = { |
60 | char *context_encoding[] = { |
60 | "Primary", |
61 | "Primary", |
61 | "Secondary", |
62 | "Secondary", |
62 | "Nucleus", |
63 | "Nucleus", |
63 | "Reserved" |
64 | "Reserved" |
64 | }; |
65 | }; |
65 | 66 | ||
66 | void tlb_arch_init(void) |
67 | void tlb_arch_init(void) |
67 | { |
68 | { |
68 | /* |
69 | /* |
69 | * TLBs are actually initialized early |
70 | * TLBs are actually initialized early |
70 | * in start.S. |
71 | * in start.S. |
71 | */ |
72 | */ |
72 | } |
73 | } |
73 | 74 | ||
74 | /** Insert privileged mapping into DMMU TLB. |
75 | /** Insert privileged mapping into DMMU TLB. |
75 | * |
76 | * |
76 | * @param page Virtual page address. |
77 | * @param page Virtual page address. |
77 | * @param frame Physical frame address. |
78 | * @param frame Physical frame address. |
78 | * @param pagesize Page size. |
79 | * @param pagesize Page size. |
79 | * @param locked True for permanent mappings, false otherwise. |
80 | * @param locked True for permanent mappings, false otherwise. |
80 | * @param cacheable True if the mapping is cacheable, false otherwise. |
81 | * @param cacheable True if the mapping is cacheable, false otherwise. |
81 | */ |
82 | */ |
82 | void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable) |
83 | void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable) |
83 | { |
84 | { |
84 | tlb_tag_access_reg_t tag; |
85 | tlb_tag_access_reg_t tag; |
85 | tlb_data_t data; |
86 | tlb_data_t data; |
86 | page_address_t pg; |
87 | page_address_t pg; |
87 | frame_address_t fr; |
88 | frame_address_t fr; |
88 | 89 | ||
89 | pg.address = page; |
90 | pg.address = page; |
90 | fr.address = frame; |
91 | fr.address = frame; |
91 | 92 | ||
92 | tag.value = ASID_KERNEL; |
93 | tag.value = ASID_KERNEL; |
93 | tag.vpn = pg.vpn; |
94 | tag.vpn = pg.vpn; |
94 | 95 | ||
95 | dtlb_tag_access_write(tag.value); |
96 | dtlb_tag_access_write(tag.value); |
96 | 97 | ||
97 | data.value = 0; |
98 | data.value = 0; |
98 | data.v = true; |
99 | data.v = true; |
99 | data.size = pagesize; |
100 | data.size = pagesize; |
100 | data.pfn = fr.pfn; |
101 | data.pfn = fr.pfn; |
101 | data.l = locked; |
102 | data.l = locked; |
102 | data.cp = cacheable; |
103 | data.cp = cacheable; |
103 | data.cv = cacheable; |
104 | data.cv = cacheable; |
104 | data.p = true; |
105 | data.p = true; |
105 | data.w = true; |
106 | data.w = true; |
106 | data.g = false; |
107 | data.g = false; |
107 | 108 | ||
108 | dtlb_data_in_write(data.value); |
109 | dtlb_data_in_write(data.value); |
109 | } |
110 | } |
110 | 111 | ||
111 | /** Copy PTE to TLB. |
112 | /** Copy PTE to TLB. |
112 | * |
113 | * |
113 | * @param t Page Table Entry to be copied. |
114 | * @param t Page Table Entry to be copied. |
114 | * @param ro If true, the entry will be created read-only, regardless of its w field. |
115 | * @param ro If true, the entry will be created read-only, regardless of its w field. |
115 | */ |
116 | */ |
116 | void dtlb_pte_copy(pte_t *t, bool ro) |
117 | void dtlb_pte_copy(pte_t *t, bool ro) |
117 | { |
118 | { |
118 | tlb_tag_access_reg_t tag; |
119 | tlb_tag_access_reg_t tag; |
119 | tlb_data_t data; |
120 | tlb_data_t data; |
120 | page_address_t pg; |
121 | page_address_t pg; |
121 | frame_address_t fr; |
122 | frame_address_t fr; |
122 | 123 | ||
123 | pg.address = t->page; |
124 | pg.address = t->page; |
124 | fr.address = t->frame; |
125 | fr.address = t->frame; |
125 | 126 | ||
126 | tag.value = 0; |
127 | tag.value = 0; |
127 | tag.context = t->as->asid; |
128 | tag.context = t->as->asid; |
128 | tag.vpn = pg.vpn; |
129 | tag.vpn = pg.vpn; |
129 | 130 | ||
130 | dtlb_tag_access_write(tag.value); |
131 | dtlb_tag_access_write(tag.value); |
131 | 132 | ||
132 | data.value = 0; |
133 | data.value = 0; |
133 | data.v = true; |
134 | data.v = true; |
134 | data.size = PAGESIZE_8K; |
135 | data.size = PAGESIZE_8K; |
135 | data.pfn = fr.pfn; |
136 | data.pfn = fr.pfn; |
136 | data.l = false; |
137 | data.l = false; |
137 | data.cp = t->c; |
138 | data.cp = t->c; |
138 | data.cv = t->c; |
139 | data.cv = t->c; |
139 | data.p = t->k; /* p like privileged */ |
140 | data.p = t->k; /* p like privileged */ |
140 | data.w = ro ? false : t->w; |
141 | data.w = ro ? false : t->w; |
141 | data.g = t->g; |
142 | data.g = t->g; |
142 | 143 | ||
143 | dtlb_data_in_write(data.value); |
144 | dtlb_data_in_write(data.value); |
144 | } |
145 | } |
145 | 146 | ||
146 | void itlb_pte_copy(pte_t *t) |
147 | void itlb_pte_copy(pte_t *t) |
147 | { |
148 | { |
148 | tlb_tag_access_reg_t tag; |
149 | tlb_tag_access_reg_t tag; |
149 | tlb_data_t data; |
150 | tlb_data_t data; |
150 | page_address_t pg; |
151 | page_address_t pg; |
151 | frame_address_t fr; |
152 | frame_address_t fr; |
152 | 153 | ||
153 | pg.address = t->page; |
154 | pg.address = t->page; |
154 | fr.address = t->frame; |
155 | fr.address = t->frame; |
155 | 156 | ||
156 | tag.value = 0; |
157 | tag.value = 0; |
157 | tag.context = t->as->asid; |
158 | tag.context = t->as->asid; |
158 | tag.vpn = pg.vpn; |
159 | tag.vpn = pg.vpn; |
159 | 160 | ||
160 | itlb_tag_access_write(tag.value); |
161 | itlb_tag_access_write(tag.value); |
161 | 162 | ||
162 | data.value = 0; |
163 | data.value = 0; |
163 | data.v = true; |
164 | data.v = true; |
164 | data.size = PAGESIZE_8K; |
165 | data.size = PAGESIZE_8K; |
165 | data.pfn = fr.pfn; |
166 | data.pfn = fr.pfn; |
166 | data.l = false; |
167 | data.l = false; |
167 | data.cp = t->c; |
168 | data.cp = t->c; |
168 | data.cv = t->c; |
169 | data.cv = t->c; |
169 | data.p = t->k; /* p like privileged */ |
170 | data.p = t->k; /* p like privileged */ |
170 | data.w = false; |
171 | data.w = false; |
171 | data.g = t->g; |
172 | data.g = t->g; |
172 | 173 | ||
173 | itlb_data_in_write(data.value); |
174 | itlb_data_in_write(data.value); |
174 | } |
175 | } |
175 | 176 | ||
176 | /** ITLB miss handler. */ |
177 | /** ITLB miss handler. */ |
177 | void fast_instruction_access_mmu_miss(int n, istate_t *istate) |
178 | void fast_instruction_access_mmu_miss(int n, istate_t *istate) |
178 | { |
179 | { |
179 | uintptr_t va = ALIGN_DOWN(istate->tpc, PAGE_SIZE); |
180 | uintptr_t va = ALIGN_DOWN(istate->tpc, PAGE_SIZE); |
180 | pte_t *t; |
181 | pte_t *t; |
181 | 182 | ||
182 | page_table_lock(AS, true); |
183 | page_table_lock(AS, true); |
183 | t = page_mapping_find(AS, va); |
184 | t = page_mapping_find(AS, va); |
184 | if (t && PTE_EXECUTABLE(t)) { |
185 | if (t && PTE_EXECUTABLE(t)) { |
185 | /* |
186 | /* |
186 | * The mapping was found in the software page hash table. |
187 | * The mapping was found in the software page hash table. |
187 | * Insert it into ITLB. |
188 | * Insert it into ITLB. |
188 | */ |
189 | */ |
189 | t->a = true; |
190 | t->a = true; |
190 | itlb_pte_copy(t); |
191 | itlb_pte_copy(t); |
191 | page_table_unlock(AS, true); |
192 | page_table_unlock(AS, true); |
192 | } else { |
193 | } else { |
193 | /* |
194 | /* |
194 | * Forward the page fault to the address space page fault handler. |
195 | * Forward the page fault to the address space page fault handler. |
195 | */ |
196 | */ |
196 | page_table_unlock(AS, true); |
197 | page_table_unlock(AS, true); |
197 | if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) { |
198 | if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) { |
198 | do_fast_instruction_access_mmu_miss_fault(istate, __FUNCTION__); |
199 | do_fast_instruction_access_mmu_miss_fault(istate, __FUNCTION__); |
199 | } |
200 | } |
200 | } |
201 | } |
201 | } |
202 | } |
202 | 203 | ||
203 | /** DTLB miss handler. |
204 | /** DTLB miss handler. |
204 | * |
205 | * |
205 | * Note that some faults (e.g. kernel faults) were already resolved |
206 | * Note that some faults (e.g. kernel faults) were already resolved |
206 | * by the low-level, assembly language part of the fast_data_access_mmu_miss |
207 | * by the low-level, assembly language part of the fast_data_access_mmu_miss |
207 | * handler. |
208 | * handler. |
208 | */ |
209 | */ |
209 | void fast_data_access_mmu_miss(int n, istate_t *istate) |
210 | void fast_data_access_mmu_miss(int n, istate_t *istate) |
210 | { |
211 | { |
211 | tlb_tag_access_reg_t tag; |
212 | tlb_tag_access_reg_t tag; |
212 | uintptr_t va; |
213 | uintptr_t va; |
213 | pte_t *t; |
214 | pte_t *t; |
214 | 215 | ||
215 | tag.value = dtlb_tag_access_read(); |
216 | tag.value = dtlb_tag_access_read(); |
216 | va = tag.vpn << PAGE_WIDTH; |
217 | va = tag.vpn << PAGE_WIDTH; |
217 | 218 | ||
218 | if (tag.context == ASID_KERNEL) { |
219 | if (tag.context == ASID_KERNEL) { |
219 | if (!tag.vpn) { |
220 | if (!tag.vpn) { |
220 | /* NULL access in kernel */ |
221 | /* NULL access in kernel */ |
221 | do_fast_data_access_mmu_miss_fault(istate, tag, __FUNCTION__); |
222 | do_fast_data_access_mmu_miss_fault(istate, tag, __FUNCTION__); |
222 | } |
223 | } |
223 | do_fast_data_access_mmu_miss_fault(istate, tag, "Unexpected kernel page fault."); |
224 | do_fast_data_access_mmu_miss_fault(istate, tag, "Unexpected kernel page fault."); |
224 | } |
225 | } |
225 | 226 | ||
226 | page_table_lock(AS, true); |
227 | page_table_lock(AS, true); |
227 | t = page_mapping_find(AS, va); |
228 | t = page_mapping_find(AS, va); |
228 | if (t) { |
229 | if (t) { |
229 | /* |
230 | /* |
230 | * The mapping was found in the software page hash table. |
231 | * The mapping was found in the software page hash table. |
231 | * Insert it into DTLB. |
232 | * Insert it into DTLB. |
232 | */ |
233 | */ |
233 | t->a = true; |
234 | t->a = true; |
234 | dtlb_pte_copy(t, true); |
235 | dtlb_pte_copy(t, true); |
235 | page_table_unlock(AS, true); |
236 | page_table_unlock(AS, true); |
236 | } else { |
237 | } else { |
237 | /* |
238 | /* |
238 | * Forward the page fault to the address space page fault handler. |
239 | * Forward the page fault to the address space page fault handler. |
239 | */ |
240 | */ |
240 | page_table_unlock(AS, true); |
241 | page_table_unlock(AS, true); |
241 | if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) { |
242 | if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) { |
242 | do_fast_data_access_mmu_miss_fault(istate, tag, __FUNCTION__); |
243 | do_fast_data_access_mmu_miss_fault(istate, tag, __FUNCTION__); |
243 | } |
244 | } |
244 | } |
245 | } |
245 | } |
246 | } |
246 | 247 | ||
247 | /** DTLB protection fault handler. */ |
248 | /** DTLB protection fault handler. */ |
248 | void fast_data_access_protection(int n, istate_t *istate) |
249 | void fast_data_access_protection(int n, istate_t *istate) |
249 | { |
250 | { |
250 | tlb_tag_access_reg_t tag; |
251 | tlb_tag_access_reg_t tag; |
251 | uintptr_t va; |
252 | uintptr_t va; |
252 | pte_t *t; |
253 | pte_t *t; |
253 | 254 | ||
254 | tag.value = dtlb_tag_access_read(); |
255 | tag.value = dtlb_tag_access_read(); |
255 | va = tag.vpn << PAGE_WIDTH; |
256 | va = tag.vpn << PAGE_WIDTH; |
256 | 257 | ||
257 | page_table_lock(AS, true); |
258 | page_table_lock(AS, true); |
258 | t = page_mapping_find(AS, va); |
259 | t = page_mapping_find(AS, va); |
259 | if (t && PTE_WRITABLE(t)) { |
260 | if (t && PTE_WRITABLE(t)) { |
260 | /* |
261 | /* |
261 | * The mapping was found in the software page hash table and is writable. |
262 | * The mapping was found in the software page hash table and is writable. |
262 | * Demap the old mapping and insert an updated mapping into DTLB. |
263 | * Demap the old mapping and insert an updated mapping into DTLB. |
263 | */ |
264 | */ |
264 | t->a = true; |
265 | t->a = true; |
265 | t->d = true; |
266 | t->d = true; |
266 | dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_SECONDARY, va); |
267 | dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_SECONDARY, va); |
267 | dtlb_pte_copy(t, false); |
268 | dtlb_pte_copy(t, false); |
268 | page_table_unlock(AS, true); |
269 | page_table_unlock(AS, true); |
269 | } else { |
270 | } else { |
270 | /* |
271 | /* |
271 | * Forward the page fault to the address space page fault handler. |
272 | * Forward the page fault to the address space page fault handler. |
272 | */ |
273 | */ |
273 | page_table_unlock(AS, true); |
274 | page_table_unlock(AS, true); |
274 | if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) { |
275 | if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) { |
275 | do_fast_data_access_protection_fault(istate, tag, __FUNCTION__); |
276 | do_fast_data_access_protection_fault(istate, tag, __FUNCTION__); |
276 | } |
277 | } |
277 | } |
278 | } |
278 | } |
279 | } |
279 | 280 | ||
280 | /** Print contents of both TLBs. */ |
281 | /** Print contents of both TLBs. */ |
281 | void tlb_print(void) |
282 | void tlb_print(void) |
282 | { |
283 | { |
283 | int i; |
284 | int i; |
284 | tlb_data_t d; |
285 | tlb_data_t d; |
285 | tlb_tag_read_reg_t t; |
286 | tlb_tag_read_reg_t t; |
286 | 287 | ||
287 | printf("I-TLB contents:\n"); |
288 | printf("I-TLB contents:\n"); |
288 | for (i = 0; i < ITLB_ENTRY_COUNT; i++) { |
289 | for (i = 0; i < ITLB_ENTRY_COUNT; i++) { |
289 | d.value = itlb_data_access_read(i); |
290 | d.value = itlb_data_access_read(i); |
290 | t.value = itlb_tag_read_read(i); |
291 | t.value = itlb_tag_read_read(i); |
291 | 292 | ||
292 | printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", |
293 | printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", |
293 | i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g); |
294 | i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g); |
294 | } |
295 | } |
295 | 296 | ||
296 | printf("D-TLB contents:\n"); |
297 | printf("D-TLB contents:\n"); |
297 | for (i = 0; i < DTLB_ENTRY_COUNT; i++) { |
298 | for (i = 0; i < DTLB_ENTRY_COUNT; i++) { |
298 | d.value = dtlb_data_access_read(i); |
299 | d.value = dtlb_data_access_read(i); |
299 | t.value = dtlb_tag_read_read(i); |
300 | t.value = dtlb_tag_read_read(i); |
300 | 301 | ||
301 | printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", |
302 | printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", |
302 | i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g); |
303 | i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g); |
303 | } |
304 | } |
304 | 305 | ||
305 | } |
306 | } |
306 | 307 | ||
307 | void do_fast_instruction_access_mmu_miss_fault(istate_t *istate, const char *str) |
308 | void do_fast_instruction_access_mmu_miss_fault(istate_t *istate, const char *str) |
308 | { |
309 | { |
309 | char *tpc_str = get_symtab_entry(istate->tpc); |
310 | char *tpc_str = get_symtab_entry(istate->tpc); |
310 | 311 | ||
- | 312 | fault_if_from_uspace(istate, "%s\n", str); |
|
311 | printf("TPC=%p, (%s)\n", istate->tpc, tpc_str); |
313 | printf("TPC=%p, (%s)\n", istate->tpc, tpc_str); |
312 | panic("%s\n", str); |
314 | panic("%s\n", str); |
313 | } |
315 | } |
314 | 316 | ||
315 | void do_fast_data_access_mmu_miss_fault(istate_t *istate, tlb_tag_access_reg_t tag, const char *str) |
317 | void do_fast_data_access_mmu_miss_fault(istate_t *istate, tlb_tag_access_reg_t tag, const char *str) |
316 | { |
318 | { |
317 | uintptr_t va; |
319 | uintptr_t va; |
318 | char *tpc_str = get_symtab_entry(istate->tpc); |
320 | char *tpc_str = get_symtab_entry(istate->tpc); |
319 | 321 | ||
320 | va = tag.vpn << PAGE_WIDTH; |
322 | va = tag.vpn << PAGE_WIDTH; |
321 | 323 | ||
- | 324 | fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va, tag.context); |
|
322 | printf("Faulting page: %p, ASID=%d\n", va, tag.context); |
325 | printf("Faulting page: %p, ASID=%d\n", va, tag.context); |
323 | printf("TPC=%p, (%s)\n", istate->tpc, tpc_str); |
326 | printf("TPC=%p, (%s)\n", istate->tpc, tpc_str); |
324 | panic("%s\n", str); |
327 | panic("%s\n", str); |
325 | } |
328 | } |
326 | 329 | ||
327 | void do_fast_data_access_protection_fault(istate_t *istate, tlb_tag_access_reg_t tag, const char *str) |
330 | void do_fast_data_access_protection_fault(istate_t *istate, tlb_tag_access_reg_t tag, const char *str) |
328 | { |
331 | { |
329 | uintptr_t va; |
332 | uintptr_t va; |
330 | char *tpc_str = get_symtab_entry(istate->tpc); |
333 | char *tpc_str = get_symtab_entry(istate->tpc); |
331 | 334 | ||
332 | va = tag.vpn << PAGE_WIDTH; |
335 | va = tag.vpn << PAGE_WIDTH; |
333 | 336 | ||
- | 337 | fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va, tag.context); |
|
334 | printf("Faulting page: %p, ASID=%d\n", va, tag.context); |
338 | printf("Faulting page: %p, ASID=%d\n", va, tag.context); |
335 | printf("TPC=%p, (%s)\n", istate->tpc, tpc_str); |
339 | printf("TPC=%p, (%s)\n", istate->tpc, tpc_str); |
336 | panic("%s\n", str); |
340 | panic("%s\n", str); |
337 | } |
341 | } |
338 | 342 | ||
339 | /** Invalidate all unlocked ITLB and DTLB entries. */ |
343 | /** Invalidate all unlocked ITLB and DTLB entries. */ |
340 | void tlb_invalidate_all(void) |
344 | void tlb_invalidate_all(void) |
341 | { |
345 | { |
342 | int i; |
346 | int i; |
343 | tlb_data_t d; |
347 | tlb_data_t d; |
344 | tlb_tag_read_reg_t t; |
348 | tlb_tag_read_reg_t t; |
345 | 349 | ||
346 | for (i = 0; i < ITLB_ENTRY_COUNT; i++) { |
350 | for (i = 0; i < ITLB_ENTRY_COUNT; i++) { |
347 | d.value = itlb_data_access_read(i); |
351 | d.value = itlb_data_access_read(i); |
348 | if (!d.l) { |
352 | if (!d.l) { |
349 | t.value = itlb_tag_read_read(i); |
353 | t.value = itlb_tag_read_read(i); |
350 | d.v = false; |
354 | d.v = false; |
351 | itlb_tag_access_write(t.value); |
355 | itlb_tag_access_write(t.value); |
352 | itlb_data_access_write(i, d.value); |
356 | itlb_data_access_write(i, d.value); |
353 | } |
357 | } |
354 | } |
358 | } |
355 | 359 | ||
356 | for (i = 0; i < DTLB_ENTRY_COUNT; i++) { |
360 | for (i = 0; i < DTLB_ENTRY_COUNT; i++) { |
357 | d.value = dtlb_data_access_read(i); |
361 | d.value = dtlb_data_access_read(i); |
358 | if (!d.l) { |
362 | if (!d.l) { |
359 | t.value = dtlb_tag_read_read(i); |
363 | t.value = dtlb_tag_read_read(i); |
360 | d.v = false; |
364 | d.v = false; |
361 | dtlb_tag_access_write(t.value); |
365 | dtlb_tag_access_write(t.value); |
362 | dtlb_data_access_write(i, d.value); |
366 | dtlb_data_access_write(i, d.value); |
363 | } |
367 | } |
364 | } |
368 | } |
365 | 369 | ||
366 | } |
370 | } |
367 | 371 | ||
368 | /** Invalidate all ITLB and DTLB entries that belong to specified ASID (Context). |
372 | /** Invalidate all ITLB and DTLB entries that belong to specified ASID (Context). |
369 | * |
373 | * |
370 | * @param asid Address Space ID. |
374 | * @param asid Address Space ID. |
371 | */ |
375 | */ |
372 | void tlb_invalidate_asid(asid_t asid) |
376 | void tlb_invalidate_asid(asid_t asid) |
373 | { |
377 | { |
374 | tlb_context_reg_t pc_save, ctx; |
378 | tlb_context_reg_t pc_save, ctx; |
375 | 379 | ||
376 | /* switch to nucleus because we are mapped by the primary context */ |
380 | /* switch to nucleus because we are mapped by the primary context */ |
377 | nucleus_enter(); |
381 | nucleus_enter(); |
378 | 382 | ||
379 | ctx.v = pc_save.v = mmu_primary_context_read(); |
383 | ctx.v = pc_save.v = mmu_primary_context_read(); |
380 | ctx.context = asid; |
384 | ctx.context = asid; |
381 | mmu_primary_context_write(ctx.v); |
385 | mmu_primary_context_write(ctx.v); |
382 | 386 | ||
383 | itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0); |
387 | itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0); |
384 | dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0); |
388 | dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0); |
385 | 389 | ||
386 | mmu_primary_context_write(pc_save.v); |
390 | mmu_primary_context_write(pc_save.v); |
387 | 391 | ||
388 | nucleus_leave(); |
392 | nucleus_leave(); |
389 | } |
393 | } |
390 | 394 | ||
391 | /** Invalidate all ITLB and DTLB entries for specified page range in specified address space. |
395 | /** Invalidate all ITLB and DTLB entries for specified page range in specified address space. |
392 | * |
396 | * |
393 | * @param asid Address Space ID. |
397 | * @param asid Address Space ID. |
394 | * @param page First page which to sweep out from ITLB and DTLB. |
398 | * @param page First page which to sweep out from ITLB and DTLB. |
395 | * @param cnt Number of ITLB and DTLB entries to invalidate. |
399 | * @param cnt Number of ITLB and DTLB entries to invalidate. |
396 | */ |
400 | */ |
397 | void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt) |
401 | void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt) |
398 | { |
402 | { |
399 | int i; |
403 | int i; |
400 | tlb_context_reg_t pc_save, ctx; |
404 | tlb_context_reg_t pc_save, ctx; |
401 | 405 | ||
402 | /* switch to nucleus because we are mapped by the primary context */ |
406 | /* switch to nucleus because we are mapped by the primary context */ |
403 | nucleus_enter(); |
407 | nucleus_enter(); |
404 | 408 | ||
405 | ctx.v = pc_save.v = mmu_primary_context_read(); |
409 | ctx.v = pc_save.v = mmu_primary_context_read(); |
406 | ctx.context = asid; |
410 | ctx.context = asid; |
407 | mmu_primary_context_write(ctx.v); |
411 | mmu_primary_context_write(ctx.v); |
408 | 412 | ||
409 | for (i = 0; i < cnt; i++) { |
413 | for (i = 0; i < cnt; i++) { |
410 | itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY, page + i * PAGE_SIZE); |
414 | itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY, page + i * PAGE_SIZE); |
411 | dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY, page + i * PAGE_SIZE); |
415 | dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY, page + i * PAGE_SIZE); |
412 | } |
416 | } |
413 | 417 | ||
414 | mmu_primary_context_write(pc_save.v); |
418 | mmu_primary_context_write(pc_save.v); |
415 | 419 | ||
416 | nucleus_leave(); |
420 | nucleus_leave(); |
417 | } |
421 | } |
418 | 422 | ||
419 | /** @} |
423 | /** @} |
420 | */ |
424 | */ |
421 | 425 |