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1 | /* |
1 | /* |
2 | * Copyright (C) 2005 Jakub Jermar |
2 | * Copyright (C) 2005 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup sparc64mm |
29 | /** @addtogroup sparc64mm |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | */ |
33 | */ |
34 | 34 | ||
35 | #include <arch/mm/tlb.h> |
35 | #include <arch/mm/tlb.h> |
36 | #include <mm/tlb.h> |
36 | #include <mm/tlb.h> |
- | 37 | #include <mm/as.h> |
|
- | 38 | #include <mm/asid.h> |
|
37 | #include <arch/mm/frame.h> |
39 | #include <arch/mm/frame.h> |
38 | #include <arch/mm/page.h> |
40 | #include <arch/mm/page.h> |
39 | #include <arch/mm/mmu.h> |
41 | #include <arch/mm/mmu.h> |
- | 42 | #include <arch/interrupt.h> |
|
40 | #include <mm/asid.h> |
43 | #include <arch.h> |
41 | #include <print.h> |
44 | #include <print.h> |
42 | #include <arch/types.h> |
45 | #include <arch/types.h> |
43 | #include <typedefs.h> |
46 | #include <typedefs.h> |
44 | #include <config.h> |
47 | #include <config.h> |
45 | #include <arch/trap/trap.h> |
48 | #include <arch/trap/trap.h> |
46 | #include <panic.h> |
49 | #include <panic.h> |
47 | #include <arch/asm.h> |
50 | #include <arch/asm.h> |
48 | #include <symtab.h> |
51 | #include <symtab.h> |
49 | 52 | ||
- | 53 | static void dtlb_pte_copy(pte_t *t); |
|
- | 54 | static void do_fast_data_access_mmu_miss_fault(istate_t *istate, const char *str); |
|
- | 55 | ||
50 | char *context_encoding[] = { |
56 | char *context_encoding[] = { |
51 | "Primary", |
57 | "Primary", |
52 | "Secondary", |
58 | "Secondary", |
53 | "Nucleus", |
59 | "Nucleus", |
54 | "Reserved" |
60 | "Reserved" |
55 | }; |
61 | }; |
56 | 62 | ||
57 | void tlb_arch_init(void) |
63 | void tlb_arch_init(void) |
58 | { |
64 | { |
59 | /* |
65 | /* |
60 | * TLBs are actually initialized early |
66 | * TLBs are actually initialized early |
61 | * in start.S. |
67 | * in start.S. |
62 | */ |
68 | */ |
63 | } |
69 | } |
64 | 70 | ||
65 | /** Insert privileged mapping into DMMU TLB. |
71 | /** Insert privileged mapping into DMMU TLB. |
66 | * |
72 | * |
67 | * @param page Virtual page address. |
73 | * @param page Virtual page address. |
68 | * @param frame Physical frame address. |
74 | * @param frame Physical frame address. |
69 | * @param pagesize Page size. |
75 | * @param pagesize Page size. |
70 | * @param locked True for permanent mappings, false otherwise. |
76 | * @param locked True for permanent mappings, false otherwise. |
71 | * @param cacheable True if the mapping is cacheable, false otherwise. |
77 | * @param cacheable True if the mapping is cacheable, false otherwise. |
72 | */ |
78 | */ |
73 | void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable) |
79 | void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable) |
74 | { |
80 | { |
75 | tlb_tag_access_reg_t tag; |
81 | tlb_tag_access_reg_t tag; |
76 | tlb_data_t data; |
82 | tlb_data_t data; |
77 | page_address_t pg; |
83 | page_address_t pg; |
78 | frame_address_t fr; |
84 | frame_address_t fr; |
79 | 85 | ||
80 | pg.address = page; |
86 | pg.address = page; |
81 | fr.address = frame; |
87 | fr.address = frame; |
82 | 88 | ||
83 | tag.value = ASID_KERNEL; |
89 | tag.value = ASID_KERNEL; |
84 | tag.vpn = pg.vpn; |
90 | tag.vpn = pg.vpn; |
85 | 91 | ||
86 | dtlb_tag_access_write(tag.value); |
92 | dtlb_tag_access_write(tag.value); |
87 | 93 | ||
88 | data.value = 0; |
94 | data.value = 0; |
89 | data.v = true; |
95 | data.v = true; |
90 | data.size = pagesize; |
96 | data.size = pagesize; |
91 | data.pfn = fr.pfn; |
97 | data.pfn = fr.pfn; |
92 | data.l = locked; |
98 | data.l = locked; |
93 | data.cp = cacheable; |
99 | data.cp = cacheable; |
94 | data.cv = cacheable; |
100 | data.cv = cacheable; |
95 | data.p = true; |
101 | data.p = true; |
96 | data.w = true; |
102 | data.w = true; |
97 | data.g = true; |
103 | data.g = true; |
98 | 104 | ||
99 | dtlb_data_in_write(data.value); |
105 | dtlb_data_in_write(data.value); |
100 | } |
106 | } |
101 | 107 | ||
- | 108 | void dtlb_pte_copy(pte_t *t) |
|
- | 109 | { |
|
- | 110 | } |
|
- | 111 | ||
102 | /** ITLB miss handler. */ |
112 | /** ITLB miss handler. */ |
103 | void fast_instruction_access_mmu_miss(void) |
113 | void fast_instruction_access_mmu_miss(int n, istate_t *istate) |
104 | { |
114 | { |
105 | panic("%s\n", __FUNCTION__); |
115 | panic("%s\n", __FUNCTION__); |
106 | } |
116 | } |
107 | 117 | ||
108 | /** DTLB miss handler. */ |
118 | /** DTLB miss handler. |
- | 119 | * |
|
- | 120 | * Note that some faults (e.g. kernel faults) were already resolved |
|
- | 121 | * by the low-level, assembly language part of the fast_data_access_mmu_miss |
|
- | 122 | * handler. |
|
- | 123 | */ |
|
109 | void fast_data_access_mmu_miss(void) |
124 | void fast_data_access_mmu_miss(int n, istate_t *istate) |
110 | { |
125 | { |
111 | tlb_tag_access_reg_t tag; |
126 | tlb_tag_access_reg_t tag; |
112 | uintptr_t tpc; |
127 | uintptr_t va; |
113 | char *tpc_str; |
128 | pte_t *t; |
114 | 129 | ||
115 | tag.value = dtlb_tag_access_read(); |
130 | tag.value = dtlb_tag_access_read(); |
- | 131 | va = tag.vpn * PAGE_SIZE; |
|
116 | if (tag.context != ASID_KERNEL || tag.vpn == 0) { |
132 | if (tag.context == ASID_KERNEL) { |
117 | tpc = tpc_read(); |
133 | if (!tag.vpn) { |
118 | tpc_str = get_symtab_entry(tpc); |
134 | /* NULL access in kernel */ |
- | 135 | do_fast_data_access_mmu_miss_fault(istate, __FUNCTION__); |
|
119 | 136 | } |
|
120 | printf("Faulting page: %p, ASID=%d\n", tag.vpn * PAGE_SIZE, tag.context); |
137 | do_fast_data_access_mmu_miss_fault(istate, "Unexpected kernel page fault."); |
121 | printf("TPC=%p, (%s)\n", tpc, tpc_str ? tpc_str : "?"); |
- | |
122 | panic("%s\n", __FUNCTION__); |
- | |
123 | } |
138 | } |
124 | 139 | ||
- | 140 | page_table_lock(AS, true); |
|
- | 141 | t = page_mapping_find(AS, va); |
|
- | 142 | if (t) { |
|
125 | /* |
143 | /* |
126 | * Identity map piece of faulting kernel address space. |
144 | * The mapping was found in the software page hash table. |
- | 145 | * Insert it into DTLB. |
|
127 | */ |
146 | */ |
- | 147 | dtlb_pte_copy(t); |
|
- | 148 | page_table_unlock(AS, true); |
|
- | 149 | } else { |
|
- | 150 | /* |
|
128 | dtlb_insert_mapping(tag.vpn * PAGE_SIZE, tag.vpn * FRAME_SIZE, PAGESIZE_8K, false, true); |
151 | * Forward the page fault to the address space page fault handler. |
- | 152 | */ |
|
- | 153 | page_table_unlock(AS, true); |
|
- | 154 | if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) { |
|
- | 155 | do_fast_data_access_mmu_miss_fault(istate, __FUNCTION__); |
|
- | 156 | } |
|
- | 157 | } |
|
129 | } |
158 | } |
130 | 159 | ||
131 | /** DTLB protection fault handler. */ |
160 | /** DTLB protection fault handler. */ |
132 | void fast_data_access_protection(void) |
161 | void fast_data_access_protection(int n, istate_t *istate) |
133 | { |
162 | { |
134 | panic("%s\n", __FUNCTION__); |
163 | panic("%s\n", __FUNCTION__); |
135 | } |
164 | } |
136 | 165 | ||
137 | /** Print contents of both TLBs. */ |
166 | /** Print contents of both TLBs. */ |
138 | void tlb_print(void) |
167 | void tlb_print(void) |
139 | { |
168 | { |
140 | int i; |
169 | int i; |
141 | tlb_data_t d; |
170 | tlb_data_t d; |
142 | tlb_tag_read_reg_t t; |
171 | tlb_tag_read_reg_t t; |
143 | 172 | ||
144 | printf("I-TLB contents:\n"); |
173 | printf("I-TLB contents:\n"); |
145 | for (i = 0; i < ITLB_ENTRY_COUNT; i++) { |
174 | for (i = 0; i < ITLB_ENTRY_COUNT; i++) { |
146 | d.value = itlb_data_access_read(i); |
175 | d.value = itlb_data_access_read(i); |
147 | t.value = itlb_tag_read_read(i); |
176 | t.value = itlb_tag_read_read(i); |
148 | 177 | ||
149 | printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", |
178 | printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", |
150 | i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g); |
179 | i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g); |
151 | } |
180 | } |
152 | 181 | ||
153 | printf("D-TLB contents:\n"); |
182 | printf("D-TLB contents:\n"); |
154 | for (i = 0; i < DTLB_ENTRY_COUNT; i++) { |
183 | for (i = 0; i < DTLB_ENTRY_COUNT; i++) { |
155 | d.value = dtlb_data_access_read(i); |
184 | d.value = dtlb_data_access_read(i); |
156 | t.value = dtlb_tag_read_read(i); |
185 | t.value = dtlb_tag_read_read(i); |
157 | 186 | ||
158 | printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", |
187 | printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", |
159 | i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g); |
188 | i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g); |
160 | } |
189 | } |
161 | 190 | ||
162 | } |
191 | } |
- | 192 | ||
- | 193 | void do_fast_data_access_mmu_miss_fault(istate_t *istate, const char *str) |
|
- | 194 | { |
|
- | 195 | tlb_tag_access_reg_t tag; |
|
- | 196 | uintptr_t va; |
|
- | 197 | char *tpc_str = get_symtab_entry(istate->tpc); |
|
- | 198 | ||
- | 199 | tag.value = dtlb_tag_access_read(); |
|
- | 200 | va = tag.vpn * PAGE_SIZE; |
|
- | 201 | ||
- | 202 | printf("Faulting page: %p, ASID=%d\n", va, tag.context); |
|
- | 203 | printf("TPC=%p, (%s)\n", istate->tpc, tpc_str); |
|
- | 204 | panic("%s\n", str); |
|
- | 205 | } |
|
163 | 206 | ||
164 | /** Invalidate all unlocked ITLB and DTLB entries. */ |
207 | /** Invalidate all unlocked ITLB and DTLB entries. */ |
165 | void tlb_invalidate_all(void) |
208 | void tlb_invalidate_all(void) |
166 | { |
209 | { |
167 | int i; |
210 | int i; |
168 | tlb_data_t d; |
211 | tlb_data_t d; |
169 | tlb_tag_read_reg_t t; |
212 | tlb_tag_read_reg_t t; |
170 | 213 | ||
171 | for (i = 0; i < ITLB_ENTRY_COUNT; i++) { |
214 | for (i = 0; i < ITLB_ENTRY_COUNT; i++) { |
172 | d.value = itlb_data_access_read(i); |
215 | d.value = itlb_data_access_read(i); |
173 | if (!d.l) { |
216 | if (!d.l) { |
174 | t.value = itlb_tag_read_read(i); |
217 | t.value = itlb_tag_read_read(i); |
175 | d.v = false; |
218 | d.v = false; |
176 | itlb_tag_access_write(t.value); |
219 | itlb_tag_access_write(t.value); |
177 | itlb_data_access_write(i, d.value); |
220 | itlb_data_access_write(i, d.value); |
178 | } |
221 | } |
179 | } |
222 | } |
180 | 223 | ||
181 | for (i = 0; i < DTLB_ENTRY_COUNT; i++) { |
224 | for (i = 0; i < DTLB_ENTRY_COUNT; i++) { |
182 | d.value = dtlb_data_access_read(i); |
225 | d.value = dtlb_data_access_read(i); |
183 | if (!d.l) { |
226 | if (!d.l) { |
184 | t.value = dtlb_tag_read_read(i); |
227 | t.value = dtlb_tag_read_read(i); |
185 | d.v = false; |
228 | d.v = false; |
186 | dtlb_tag_access_write(t.value); |
229 | dtlb_tag_access_write(t.value); |
187 | dtlb_data_access_write(i, d.value); |
230 | dtlb_data_access_write(i, d.value); |
188 | } |
231 | } |
189 | } |
232 | } |
190 | 233 | ||
191 | } |
234 | } |
192 | 235 | ||
193 | /** Invalidate all ITLB and DTLB entries that belong to specified ASID (Context). |
236 | /** Invalidate all ITLB and DTLB entries that belong to specified ASID (Context). |
194 | * |
237 | * |
195 | * @param asid Address Space ID. |
238 | * @param asid Address Space ID. |
196 | */ |
239 | */ |
197 | void tlb_invalidate_asid(asid_t asid) |
240 | void tlb_invalidate_asid(asid_t asid) |
198 | { |
241 | { |
199 | /* TODO: write asid to some Context register and encode the register in second parameter below. */ |
242 | /* TODO: write asid to some Context register and encode the register in second parameter below. */ |
200 | itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0); |
243 | itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0); |
201 | dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0); |
244 | dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0); |
202 | } |
245 | } |
203 | 246 | ||
204 | /** Invalidate all ITLB and DTLB entries for specified page range in specified address space. |
247 | /** Invalidate all ITLB and DTLB entries for specified page range in specified address space. |
205 | * |
248 | * |
206 | * @param asid Address Space ID. |
249 | * @param asid Address Space ID. |
207 | * @param page First page which to sweep out from ITLB and DTLB. |
250 | * @param page First page which to sweep out from ITLB and DTLB. |
208 | * @param cnt Number of ITLB and DTLB entries to invalidate. |
251 | * @param cnt Number of ITLB and DTLB entries to invalidate. |
209 | */ |
252 | */ |
210 | void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt) |
253 | void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt) |
211 | { |
254 | { |
212 | int i; |
255 | int i; |
213 | 256 | ||
214 | for (i = 0; i < cnt; i++) { |
257 | for (i = 0; i < cnt; i++) { |
215 | /* TODO: write asid to some Context register and encode the register in second parameter below. */ |
258 | /* TODO: write asid to some Context register and encode the register in second parameter below. */ |
216 | itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE); |
259 | itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE); |
217 | dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE); |
260 | dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE); |
218 | } |
261 | } |
219 | } |
262 | } |
220 | 263 | ||
221 | /** @} |
264 | /** @} |
222 | */ |
265 | */ |
223 | 266 |