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1 | /* |
1 | /* |
2 | * Copyright (C) 2005 Jakub Jermar |
2 | * Copyright (C) 2005 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup sparc64mm |
29 | /** @addtogroup sparc64mm |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | */ |
33 | */ |
34 | 34 | ||
35 | #ifndef __sparc64_TLB_H__ |
35 | #ifndef KERN_sparc64_TLB_H_ |
36 | #define __sparc64_TLB_H__ |
36 | #define KERN_sparc64_TLB_H_ |
37 | - | ||
38 | 37 | ||
39 | #define ITLB_ENTRY_COUNT 64 |
38 | #define ITLB_ENTRY_COUNT 64 |
40 | #define DTLB_ENTRY_COUNT 64 |
39 | #define DTLB_ENTRY_COUNT 64 |
41 | 40 | ||
42 | #define MEM_CONTEXT_KERNEL 0 |
41 | #define MEM_CONTEXT_KERNEL 0 |
43 | #define MEM_CONTEXT_TEMP 1 |
42 | #define MEM_CONTEXT_TEMP 1 |
44 | 43 | ||
45 | /** Page sizes. */ |
44 | /** Page sizes. */ |
46 | #define PAGESIZE_8K 0 |
45 | #define PAGESIZE_8K 0 |
47 | #define PAGESIZE_64K 1 |
46 | #define PAGESIZE_64K 1 |
48 | #define PAGESIZE_512K 2 |
47 | #define PAGESIZE_512K 2 |
49 | #define PAGESIZE_4M 3 |
48 | #define PAGESIZE_4M 3 |
50 | 49 | ||
51 | /** Bit width of the TLB-locked portion of kernel address space. */ |
50 | /** Bit width of the TLB-locked portion of kernel address space. */ |
52 | #define KERNEL_PAGE_WIDTH 22 /* 4M */ |
51 | #define KERNEL_PAGE_WIDTH 22 /* 4M */ |
53 | 52 | ||
54 | /* TLB Demap Operation types. */ |
53 | /* TLB Demap Operation types. */ |
55 | #define TLB_DEMAP_PAGE 0 |
54 | #define TLB_DEMAP_PAGE 0 |
56 | #define TLB_DEMAP_CONTEXT 1 |
55 | #define TLB_DEMAP_CONTEXT 1 |
57 | 56 | ||
58 | #define TLB_DEMAP_TYPE_SHIFT 6 |
57 | #define TLB_DEMAP_TYPE_SHIFT 6 |
59 | 58 | ||
60 | /* TLB Demap Operation Context register encodings. */ |
59 | /* TLB Demap Operation Context register encodings. */ |
61 | #define TLB_DEMAP_PRIMARY 0 |
60 | #define TLB_DEMAP_PRIMARY 0 |
62 | #define TLB_DEMAP_SECONDARY 1 |
61 | #define TLB_DEMAP_SECONDARY 1 |
63 | #define TLB_DEMAP_NUCLEUS 2 |
62 | #define TLB_DEMAP_NUCLEUS 2 |
64 | 63 | ||
65 | #define TLB_DEMAP_CONTEXT_SHIFT 4 |
64 | #define TLB_DEMAP_CONTEXT_SHIFT 4 |
66 | 65 | ||
67 | /* TLB Tag Access shifts */ |
66 | /* TLB Tag Access shifts */ |
68 | #define TLB_TAG_ACCESS_CONTEXT_SHIFT 0 |
67 | #define TLB_TAG_ACCESS_CONTEXT_SHIFT 0 |
69 | #define TLB_TAG_ACCESS_CONTEXT_MASK ((1<<13)-1) |
68 | #define TLB_TAG_ACCESS_CONTEXT_MASK ((1<<13)-1) |
70 | #define TLB_TAG_ACCESS_VPN_SHIFT 13 |
69 | #define TLB_TAG_ACCESS_VPN_SHIFT 13 |
71 | 70 | ||
72 | #ifndef __ASM__ |
71 | #ifndef __ASM__ |
73 | 72 | ||
74 | #include <arch/mm/tte.h> |
73 | #include <arch/mm/tte.h> |
75 | #include <arch/mm/mmu.h> |
74 | #include <arch/mm/mmu.h> |
76 | #include <arch/mm/page.h> |
75 | #include <arch/mm/page.h> |
77 | #include <arch/asm.h> |
76 | #include <arch/asm.h> |
78 | #include <arch/barrier.h> |
77 | #include <arch/barrier.h> |
79 | #include <arch/types.h> |
78 | #include <arch/types.h> |
80 | #include <typedefs.h> |
79 | #include <typedefs.h> |
81 | 80 | ||
82 | union tlb_context_reg { |
81 | union tlb_context_reg { |
83 | uint64_t v; |
82 | uint64_t v; |
84 | struct { |
83 | struct { |
85 | unsigned long : 51; |
84 | unsigned long : 51; |
86 | unsigned context : 13; /**< Context/ASID. */ |
85 | unsigned context : 13; /**< Context/ASID. */ |
87 | } __attribute__ ((packed)); |
86 | } __attribute__ ((packed)); |
88 | }; |
87 | }; |
89 | typedef union tlb_context_reg tlb_context_reg_t; |
88 | typedef union tlb_context_reg tlb_context_reg_t; |
90 | 89 | ||
91 | /** I-/D-TLB Data In/Access Register type. */ |
90 | /** I-/D-TLB Data In/Access Register type. */ |
92 | typedef tte_data_t tlb_data_t; |
91 | typedef tte_data_t tlb_data_t; |
93 | 92 | ||
94 | /** I-/D-TLB Data Access Address in Alternate Space. */ |
93 | /** I-/D-TLB Data Access Address in Alternate Space. */ |
95 | union tlb_data_access_addr { |
94 | union tlb_data_access_addr { |
96 | uint64_t value; |
95 | uint64_t value; |
97 | struct { |
96 | struct { |
98 | uint64_t : 55; |
97 | uint64_t : 55; |
99 | unsigned tlb_entry : 6; |
98 | unsigned tlb_entry : 6; |
100 | unsigned : 3; |
99 | unsigned : 3; |
101 | } __attribute__ ((packed)); |
100 | } __attribute__ ((packed)); |
102 | }; |
101 | }; |
103 | typedef union tlb_data_access_addr tlb_data_access_addr_t; |
102 | typedef union tlb_data_access_addr tlb_data_access_addr_t; |
104 | typedef union tlb_data_access_addr tlb_tag_read_addr_t; |
103 | typedef union tlb_data_access_addr tlb_tag_read_addr_t; |
105 | 104 | ||
106 | /** I-/D-TLB Tag Read Register. */ |
105 | /** I-/D-TLB Tag Read Register. */ |
107 | union tlb_tag_read_reg { |
106 | union tlb_tag_read_reg { |
108 | uint64_t value; |
107 | uint64_t value; |
109 | struct { |
108 | struct { |
110 | uint64_t vpn : 51; /**< Virtual Address bits 63:13. */ |
109 | uint64_t vpn : 51; /**< Virtual Address bits 63:13. */ |
111 | unsigned context : 13; /**< Context identifier. */ |
110 | unsigned context : 13; /**< Context identifier. */ |
112 | } __attribute__ ((packed)); |
111 | } __attribute__ ((packed)); |
113 | }; |
112 | }; |
114 | typedef union tlb_tag_read_reg tlb_tag_read_reg_t; |
113 | typedef union tlb_tag_read_reg tlb_tag_read_reg_t; |
115 | typedef union tlb_tag_read_reg tlb_tag_access_reg_t; |
114 | typedef union tlb_tag_read_reg tlb_tag_access_reg_t; |
116 | 115 | ||
117 | 116 | ||
118 | /** TLB Demap Operation Address. */ |
117 | /** TLB Demap Operation Address. */ |
119 | union tlb_demap_addr { |
118 | union tlb_demap_addr { |
120 | uint64_t value; |
119 | uint64_t value; |
121 | struct { |
120 | struct { |
122 | uint64_t vpn: 51; /**< Virtual Address bits 63:13. */ |
121 | uint64_t vpn: 51; /**< Virtual Address bits 63:13. */ |
123 | unsigned : 6; /**< Ignored. */ |
122 | unsigned : 6; /**< Ignored. */ |
124 | unsigned type : 1; /**< The type of demap operation. */ |
123 | unsigned type : 1; /**< The type of demap operation. */ |
125 | unsigned context : 2; /**< Context register selection. */ |
124 | unsigned context : 2; /**< Context register selection. */ |
126 | unsigned : 4; /**< Zero. */ |
125 | unsigned : 4; /**< Zero. */ |
127 | } __attribute__ ((packed)); |
126 | } __attribute__ ((packed)); |
128 | }; |
127 | }; |
129 | typedef union tlb_demap_addr tlb_demap_addr_t; |
128 | typedef union tlb_demap_addr tlb_demap_addr_t; |
130 | 129 | ||
131 | /** TLB Synchronous Fault Status Register. */ |
130 | /** TLB Synchronous Fault Status Register. */ |
132 | union tlb_sfsr_reg { |
131 | union tlb_sfsr_reg { |
133 | uint64_t value; |
132 | uint64_t value; |
134 | struct { |
133 | struct { |
135 | unsigned long : 40; /**< Implementation dependent. */ |
134 | unsigned long : 40; /**< Implementation dependent. */ |
136 | unsigned asi : 8; /**< ASI. */ |
135 | unsigned asi : 8; /**< ASI. */ |
137 | unsigned : 2; |
136 | unsigned : 2; |
138 | unsigned ft : 7; /**< Fault type. */ |
137 | unsigned ft : 7; /**< Fault type. */ |
139 | unsigned e : 1; /**< Side-effect bit. */ |
138 | unsigned e : 1; /**< Side-effect bit. */ |
140 | unsigned ct : 2; /**< Context Register selection. */ |
139 | unsigned ct : 2; /**< Context Register selection. */ |
141 | unsigned pr : 1; /**< Privilege bit. */ |
140 | unsigned pr : 1; /**< Privilege bit. */ |
142 | unsigned w : 1; /**< Write bit. */ |
141 | unsigned w : 1; /**< Write bit. */ |
143 | unsigned ow : 1; /**< Overwrite bit. */ |
142 | unsigned ow : 1; /**< Overwrite bit. */ |
144 | unsigned fv : 1; /**< Fault Valid bit. */ |
143 | unsigned fv : 1; /**< Fault Valid bit. */ |
145 | } __attribute__ ((packed)); |
144 | } __attribute__ ((packed)); |
146 | }; |
145 | }; |
147 | typedef union tlb_sfsr_reg tlb_sfsr_reg_t; |
146 | typedef union tlb_sfsr_reg tlb_sfsr_reg_t; |
148 | 147 | ||
149 | /** Read MMU Primary Context Register. |
148 | /** Read MMU Primary Context Register. |
150 | * |
149 | * |
151 | * @return Current value of Primary Context Register. |
150 | * @return Current value of Primary Context Register. |
152 | */ |
151 | */ |
153 | static inline uint64_t mmu_primary_context_read(void) |
152 | static inline uint64_t mmu_primary_context_read(void) |
154 | { |
153 | { |
155 | return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG); |
154 | return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG); |
156 | } |
155 | } |
157 | 156 | ||
158 | /** Write MMU Primary Context Register. |
157 | /** Write MMU Primary Context Register. |
159 | * |
158 | * |
160 | * @param v New value of Primary Context Register. |
159 | * @param v New value of Primary Context Register. |
161 | */ |
160 | */ |
162 | static inline void mmu_primary_context_write(uint64_t v) |
161 | static inline void mmu_primary_context_write(uint64_t v) |
163 | { |
162 | { |
164 | asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v); |
163 | asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v); |
165 | flush(); |
164 | flush(); |
166 | } |
165 | } |
167 | 166 | ||
168 | /** Read MMU Secondary Context Register. |
167 | /** Read MMU Secondary Context Register. |
169 | * |
168 | * |
170 | * @return Current value of Secondary Context Register. |
169 | * @return Current value of Secondary Context Register. |
171 | */ |
170 | */ |
172 | static inline uint64_t mmu_secondary_context_read(void) |
171 | static inline uint64_t mmu_secondary_context_read(void) |
173 | { |
172 | { |
174 | return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG); |
173 | return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG); |
175 | } |
174 | } |
176 | 175 | ||
177 | /** Write MMU Primary Context Register. |
176 | /** Write MMU Primary Context Register. |
178 | * |
177 | * |
179 | * @param v New value of Primary Context Register. |
178 | * @param v New value of Primary Context Register. |
180 | */ |
179 | */ |
181 | static inline void mmu_secondary_context_write(uint64_t v) |
180 | static inline void mmu_secondary_context_write(uint64_t v) |
182 | { |
181 | { |
183 | asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v); |
182 | asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v); |
184 | flush(); |
183 | flush(); |
185 | } |
184 | } |
186 | 185 | ||
187 | /** Read IMMU TLB Data Access Register. |
186 | /** Read IMMU TLB Data Access Register. |
188 | * |
187 | * |
189 | * @param entry TLB Entry index. |
188 | * @param entry TLB Entry index. |
190 | * |
189 | * |
191 | * @return Current value of specified IMMU TLB Data Access Register. |
190 | * @return Current value of specified IMMU TLB Data Access Register. |
192 | */ |
191 | */ |
193 | static inline uint64_t itlb_data_access_read(index_t entry) |
192 | static inline uint64_t itlb_data_access_read(index_t entry) |
194 | { |
193 | { |
195 | tlb_data_access_addr_t reg; |
194 | tlb_data_access_addr_t reg; |
196 | 195 | ||
197 | reg.value = 0; |
196 | reg.value = 0; |
198 | reg.tlb_entry = entry; |
197 | reg.tlb_entry = entry; |
199 | return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value); |
198 | return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value); |
200 | } |
199 | } |
201 | 200 | ||
202 | /** Write IMMU TLB Data Access Register. |
201 | /** Write IMMU TLB Data Access Register. |
203 | * |
202 | * |
204 | * @param entry TLB Entry index. |
203 | * @param entry TLB Entry index. |
205 | * @param value Value to be written. |
204 | * @param value Value to be written. |
206 | */ |
205 | */ |
207 | static inline void itlb_data_access_write(index_t entry, uint64_t value) |
206 | static inline void itlb_data_access_write(index_t entry, uint64_t value) |
208 | { |
207 | { |
209 | tlb_data_access_addr_t reg; |
208 | tlb_data_access_addr_t reg; |
210 | 209 | ||
211 | reg.value = 0; |
210 | reg.value = 0; |
212 | reg.tlb_entry = entry; |
211 | reg.tlb_entry = entry; |
213 | asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value); |
212 | asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value); |
214 | flush(); |
213 | flush(); |
215 | } |
214 | } |
216 | 215 | ||
217 | /** Read DMMU TLB Data Access Register. |
216 | /** Read DMMU TLB Data Access Register. |
218 | * |
217 | * |
219 | * @param entry TLB Entry index. |
218 | * @param entry TLB Entry index. |
220 | * |
219 | * |
221 | * @return Current value of specified DMMU TLB Data Access Register. |
220 | * @return Current value of specified DMMU TLB Data Access Register. |
222 | */ |
221 | */ |
223 | static inline uint64_t dtlb_data_access_read(index_t entry) |
222 | static inline uint64_t dtlb_data_access_read(index_t entry) |
224 | { |
223 | { |
225 | tlb_data_access_addr_t reg; |
224 | tlb_data_access_addr_t reg; |
226 | 225 | ||
227 | reg.value = 0; |
226 | reg.value = 0; |
228 | reg.tlb_entry = entry; |
227 | reg.tlb_entry = entry; |
229 | return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value); |
228 | return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value); |
230 | } |
229 | } |
231 | 230 | ||
232 | /** Write DMMU TLB Data Access Register. |
231 | /** Write DMMU TLB Data Access Register. |
233 | * |
232 | * |
234 | * @param entry TLB Entry index. |
233 | * @param entry TLB Entry index. |
235 | * @param value Value to be written. |
234 | * @param value Value to be written. |
236 | */ |
235 | */ |
237 | static inline void dtlb_data_access_write(index_t entry, uint64_t value) |
236 | static inline void dtlb_data_access_write(index_t entry, uint64_t value) |
238 | { |
237 | { |
239 | tlb_data_access_addr_t reg; |
238 | tlb_data_access_addr_t reg; |
240 | 239 | ||
241 | reg.value = 0; |
240 | reg.value = 0; |
242 | reg.tlb_entry = entry; |
241 | reg.tlb_entry = entry; |
243 | asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value); |
242 | asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value); |
244 | membar(); |
243 | membar(); |
245 | } |
244 | } |
246 | 245 | ||
247 | /** Read IMMU TLB Tag Read Register. |
246 | /** Read IMMU TLB Tag Read Register. |
248 | * |
247 | * |
249 | * @param entry TLB Entry index. |
248 | * @param entry TLB Entry index. |
250 | * |
249 | * |
251 | * @return Current value of specified IMMU TLB Tag Read Register. |
250 | * @return Current value of specified IMMU TLB Tag Read Register. |
252 | */ |
251 | */ |
253 | static inline uint64_t itlb_tag_read_read(index_t entry) |
252 | static inline uint64_t itlb_tag_read_read(index_t entry) |
254 | { |
253 | { |
255 | tlb_tag_read_addr_t tag; |
254 | tlb_tag_read_addr_t tag; |
256 | 255 | ||
257 | tag.value = 0; |
256 | tag.value = 0; |
258 | tag.tlb_entry = entry; |
257 | tag.tlb_entry = entry; |
259 | return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value); |
258 | return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value); |
260 | } |
259 | } |
261 | 260 | ||
262 | /** Read DMMU TLB Tag Read Register. |
261 | /** Read DMMU TLB Tag Read Register. |
263 | * |
262 | * |
264 | * @param entry TLB Entry index. |
263 | * @param entry TLB Entry index. |
265 | * |
264 | * |
266 | * @return Current value of specified DMMU TLB Tag Read Register. |
265 | * @return Current value of specified DMMU TLB Tag Read Register. |
267 | */ |
266 | */ |
268 | static inline uint64_t dtlb_tag_read_read(index_t entry) |
267 | static inline uint64_t dtlb_tag_read_read(index_t entry) |
269 | { |
268 | { |
270 | tlb_tag_read_addr_t tag; |
269 | tlb_tag_read_addr_t tag; |
271 | 270 | ||
272 | tag.value = 0; |
271 | tag.value = 0; |
273 | tag.tlb_entry = entry; |
272 | tag.tlb_entry = entry; |
274 | return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value); |
273 | return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value); |
275 | } |
274 | } |
276 | 275 | ||
277 | /** Write IMMU TLB Tag Access Register. |
276 | /** Write IMMU TLB Tag Access Register. |
278 | * |
277 | * |
279 | * @param v Value to be written. |
278 | * @param v Value to be written. |
280 | */ |
279 | */ |
281 | static inline void itlb_tag_access_write(uint64_t v) |
280 | static inline void itlb_tag_access_write(uint64_t v) |
282 | { |
281 | { |
283 | asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v); |
282 | asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v); |
284 | flush(); |
283 | flush(); |
285 | } |
284 | } |
286 | 285 | ||
287 | /** Read IMMU TLB Tag Access Register. |
286 | /** Read IMMU TLB Tag Access Register. |
288 | * |
287 | * |
289 | * @return Current value of IMMU TLB Tag Access Register. |
288 | * @return Current value of IMMU TLB Tag Access Register. |
290 | */ |
289 | */ |
291 | static inline uint64_t itlb_tag_access_read(void) |
290 | static inline uint64_t itlb_tag_access_read(void) |
292 | { |
291 | { |
293 | return asi_u64_read(ASI_IMMU, VA_IMMU_TAG_ACCESS); |
292 | return asi_u64_read(ASI_IMMU, VA_IMMU_TAG_ACCESS); |
294 | } |
293 | } |
295 | 294 | ||
296 | /** Write DMMU TLB Tag Access Register. |
295 | /** Write DMMU TLB Tag Access Register. |
297 | * |
296 | * |
298 | * @param v Value to be written. |
297 | * @param v Value to be written. |
299 | */ |
298 | */ |
300 | static inline void dtlb_tag_access_write(uint64_t v) |
299 | static inline void dtlb_tag_access_write(uint64_t v) |
301 | { |
300 | { |
302 | asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v); |
301 | asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v); |
303 | membar(); |
302 | membar(); |
304 | } |
303 | } |
305 | 304 | ||
306 | /** Read DMMU TLB Tag Access Register. |
305 | /** Read DMMU TLB Tag Access Register. |
307 | * |
306 | * |
308 | * @return Current value of DMMU TLB Tag Access Register. |
307 | * @return Current value of DMMU TLB Tag Access Register. |
309 | */ |
308 | */ |
310 | static inline uint64_t dtlb_tag_access_read(void) |
309 | static inline uint64_t dtlb_tag_access_read(void) |
311 | { |
310 | { |
312 | return asi_u64_read(ASI_DMMU, VA_DMMU_TAG_ACCESS); |
311 | return asi_u64_read(ASI_DMMU, VA_DMMU_TAG_ACCESS); |
313 | } |
312 | } |
314 | 313 | ||
315 | 314 | ||
316 | /** Write IMMU TLB Data in Register. |
315 | /** Write IMMU TLB Data in Register. |
317 | * |
316 | * |
318 | * @param v Value to be written. |
317 | * @param v Value to be written. |
319 | */ |
318 | */ |
320 | static inline void itlb_data_in_write(uint64_t v) |
319 | static inline void itlb_data_in_write(uint64_t v) |
321 | { |
320 | { |
322 | asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v); |
321 | asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v); |
323 | flush(); |
322 | flush(); |
324 | } |
323 | } |
325 | 324 | ||
326 | /** Write DMMU TLB Data in Register. |
325 | /** Write DMMU TLB Data in Register. |
327 | * |
326 | * |
328 | * @param v Value to be written. |
327 | * @param v Value to be written. |
329 | */ |
328 | */ |
330 | static inline void dtlb_data_in_write(uint64_t v) |
329 | static inline void dtlb_data_in_write(uint64_t v) |
331 | { |
330 | { |
332 | asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v); |
331 | asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v); |
333 | membar(); |
332 | membar(); |
334 | } |
333 | } |
335 | 334 | ||
336 | /** Read ITLB Synchronous Fault Status Register. |
335 | /** Read ITLB Synchronous Fault Status Register. |
337 | * |
336 | * |
338 | * @return Current content of I-SFSR register. |
337 | * @return Current content of I-SFSR register. |
339 | */ |
338 | */ |
340 | static inline uint64_t itlb_sfsr_read(void) |
339 | static inline uint64_t itlb_sfsr_read(void) |
341 | { |
340 | { |
342 | return asi_u64_read(ASI_IMMU, VA_IMMU_SFSR); |
341 | return asi_u64_read(ASI_IMMU, VA_IMMU_SFSR); |
343 | } |
342 | } |
344 | 343 | ||
345 | /** Write ITLB Synchronous Fault Status Register. |
344 | /** Write ITLB Synchronous Fault Status Register. |
346 | * |
345 | * |
347 | * @param v New value of I-SFSR register. |
346 | * @param v New value of I-SFSR register. |
348 | */ |
347 | */ |
349 | static inline void itlb_sfsr_write(uint64_t v) |
348 | static inline void itlb_sfsr_write(uint64_t v) |
350 | { |
349 | { |
351 | asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v); |
350 | asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v); |
352 | flush(); |
351 | flush(); |
353 | } |
352 | } |
354 | 353 | ||
355 | /** Read DTLB Synchronous Fault Status Register. |
354 | /** Read DTLB Synchronous Fault Status Register. |
356 | * |
355 | * |
357 | * @return Current content of D-SFSR register. |
356 | * @return Current content of D-SFSR register. |
358 | */ |
357 | */ |
359 | static inline uint64_t dtlb_sfsr_read(void) |
358 | static inline uint64_t dtlb_sfsr_read(void) |
360 | { |
359 | { |
361 | return asi_u64_read(ASI_DMMU, VA_DMMU_SFSR); |
360 | return asi_u64_read(ASI_DMMU, VA_DMMU_SFSR); |
362 | } |
361 | } |
363 | 362 | ||
364 | /** Write DTLB Synchronous Fault Status Register. |
363 | /** Write DTLB Synchronous Fault Status Register. |
365 | * |
364 | * |
366 | * @param v New value of D-SFSR register. |
365 | * @param v New value of D-SFSR register. |
367 | */ |
366 | */ |
368 | static inline void dtlb_sfsr_write(uint64_t v) |
367 | static inline void dtlb_sfsr_write(uint64_t v) |
369 | { |
368 | { |
370 | asi_u64_write(ASI_DMMU, VA_DMMU_SFSR, v); |
369 | asi_u64_write(ASI_DMMU, VA_DMMU_SFSR, v); |
371 | membar(); |
370 | membar(); |
372 | } |
371 | } |
373 | 372 | ||
374 | /** Read DTLB Synchronous Fault Address Register. |
373 | /** Read DTLB Synchronous Fault Address Register. |
375 | * |
374 | * |
376 | * @return Current content of D-SFAR register. |
375 | * @return Current content of D-SFAR register. |
377 | */ |
376 | */ |
378 | static inline uint64_t dtlb_sfar_read(void) |
377 | static inline uint64_t dtlb_sfar_read(void) |
379 | { |
378 | { |
380 | return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR); |
379 | return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR); |
381 | } |
380 | } |
382 | 381 | ||
383 | /** Perform IMMU TLB Demap Operation. |
382 | /** Perform IMMU TLB Demap Operation. |
384 | * |
383 | * |
385 | * @param type Selects between context and page demap. |
384 | * @param type Selects between context and page demap. |
386 | * @param context_encoding Specifies which Context register has Context ID for demap. |
385 | * @param context_encoding Specifies which Context register has Context ID for demap. |
387 | * @param page Address which is on the page to be demapped. |
386 | * @param page Address which is on the page to be demapped. |
388 | */ |
387 | */ |
389 | static inline void itlb_demap(int type, int context_encoding, uintptr_t page) |
388 | static inline void itlb_demap(int type, int context_encoding, uintptr_t page) |
390 | { |
389 | { |
391 | tlb_demap_addr_t da; |
390 | tlb_demap_addr_t da; |
392 | page_address_t pg; |
391 | page_address_t pg; |
393 | 392 | ||
394 | da.value = 0; |
393 | da.value = 0; |
395 | pg.address = page; |
394 | pg.address = page; |
396 | 395 | ||
397 | da.type = type; |
396 | da.type = type; |
398 | da.context = context_encoding; |
397 | da.context = context_encoding; |
399 | da.vpn = pg.vpn; |
398 | da.vpn = pg.vpn; |
400 | 399 | ||
401 | asi_u64_write(ASI_IMMU_DEMAP, da.value, 0); /* da.value is the address within the ASI */ |
400 | asi_u64_write(ASI_IMMU_DEMAP, da.value, 0); /* da.value is the address within the ASI */ |
402 | flush(); |
401 | flush(); |
403 | } |
402 | } |
404 | 403 | ||
405 | /** Perform DMMU TLB Demap Operation. |
404 | /** Perform DMMU TLB Demap Operation. |
406 | * |
405 | * |
407 | * @param type Selects between context and page demap. |
406 | * @param type Selects between context and page demap. |
408 | * @param context_encoding Specifies which Context register has Context ID for demap. |
407 | * @param context_encoding Specifies which Context register has Context ID for demap. |
409 | * @param page Address which is on the page to be demapped. |
408 | * @param page Address which is on the page to be demapped. |
410 | */ |
409 | */ |
411 | static inline void dtlb_demap(int type, int context_encoding, uintptr_t page) |
410 | static inline void dtlb_demap(int type, int context_encoding, uintptr_t page) |
412 | { |
411 | { |
413 | tlb_demap_addr_t da; |
412 | tlb_demap_addr_t da; |
414 | page_address_t pg; |
413 | page_address_t pg; |
415 | 414 | ||
416 | da.value = 0; |
415 | da.value = 0; |
417 | pg.address = page; |
416 | pg.address = page; |
418 | 417 | ||
419 | da.type = type; |
418 | da.type = type; |
420 | da.context = context_encoding; |
419 | da.context = context_encoding; |
421 | da.vpn = pg.vpn; |
420 | da.vpn = pg.vpn; |
422 | 421 | ||
423 | asi_u64_write(ASI_DMMU_DEMAP, da.value, 0); /* da.value is the address within the ASI */ |
422 | asi_u64_write(ASI_DMMU_DEMAP, da.value, 0); /* da.value is the address within the ASI */ |
424 | membar(); |
423 | membar(); |
425 | } |
424 | } |
426 | 425 | ||
427 | extern void fast_instruction_access_mmu_miss(int n, istate_t *istate); |
426 | extern void fast_instruction_access_mmu_miss(int n, istate_t *istate); |
428 | extern void fast_data_access_mmu_miss(int n, istate_t *istate); |
427 | extern void fast_data_access_mmu_miss(int n, istate_t *istate); |
429 | extern void fast_data_access_protection(int n, istate_t *istate); |
428 | extern void fast_data_access_protection(int n, istate_t *istate); |
430 | 429 | ||
431 | extern void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable); |
430 | extern void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable); |
432 | 431 | ||
433 | #endif /* !def __ASM__ */ |
432 | #endif /* !def __ASM__ */ |
434 | 433 | ||
435 | #endif |
434 | #endif |
436 | 435 | ||
437 | /** @} |
436 | /** @} |
438 | */ |
437 | */ |
439 | 438 |