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1 | # |
1 | # |
2 | # Copyright (c) 2006 Martin Decky |
2 | # Copyright (c) 2006 Martin Decky |
3 | # All rights reserved. |
3 | # All rights reserved. |
4 | # |
4 | # |
5 | # Redistribution and use in source and binary forms, with or without |
5 | # Redistribution and use in source and binary forms, with or without |
6 | # modification, are permitted provided that the following conditions |
6 | # modification, are permitted provided that the following conditions |
7 | # are met: |
7 | # are met: |
8 | # |
8 | # |
9 | # - Redistributions of source code must retain the above copyright |
9 | # - Redistributions of source code must retain the above copyright |
10 | # notice, this list of conditions and the following disclaimer. |
10 | # notice, this list of conditions and the following disclaimer. |
11 | # - Redistributions in binary form must reproduce the above copyright |
11 | # - Redistributions in binary form must reproduce the above copyright |
12 | # notice, this list of conditions and the following disclaimer in the |
12 | # notice, this list of conditions and the following disclaimer in the |
13 | # documentation and/or other materials provided with the distribution. |
13 | # documentation and/or other materials provided with the distribution. |
14 | # - The name of the author may not be used to endorse or promote products |
14 | # - The name of the author may not be used to endorse or promote products |
15 | # derived from this software without specific prior written permission. |
15 | # derived from this software without specific prior written permission. |
16 | # |
16 | # |
17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | # |
27 | # |
28 | 28 | ||
29 | #include <arch/asm/regname.h> |
29 | #include <arch/asm/regname.h> |
30 | 30 | ||
31 | .text |
31 | .text |
32 | 32 | ||
33 | .global userspace_asm |
33 | .global userspace_asm |
34 | .global iret |
34 | .global iret |
35 | .global iret_syscall |
35 | .global iret_syscall |
36 | .global memsetb |
36 | .global memsetb |
37 | .global memcpy |
37 | .global memcpy |
38 | .global memcpy_from_uspace |
38 | .global memcpy_from_uspace |
39 | .global memcpy_to_uspace |
39 | .global memcpy_to_uspace |
40 | .global memcpy_from_uspace_failover_address |
40 | .global memcpy_from_uspace_failover_address |
41 | .global memcpy_to_uspace_failover_address |
41 | .global memcpy_to_uspace_failover_address |
42 | 42 | ||
43 | userspace_asm: |
43 | userspace_asm: |
44 | 44 | ||
45 | # r3 = uspace_uarg |
45 | # r3 = uspace_uarg |
46 | # r4 = stack |
46 | # r4 = stack |
47 | # r5 = entry |
47 | # r5 = entry |
48 | 48 | ||
49 | # disable interrupts |
49 | # disable interrupts |
50 | 50 | ||
51 | mfmsr r31 |
51 | mfmsr r31 |
52 | rlwinm r31, r31, 0, 17, 15 |
52 | rlwinm r31, r31, 0, 17, 15 |
53 | mtmsr r31 |
53 | mtmsr r31 |
54 | 54 | ||
55 | # set entry point |
55 | # set entry point |
56 | 56 | ||
57 | mtsrr0 r5 |
57 | mtsrr0 r5 |
58 | 58 | ||
59 | # set problem state, enable interrupts |
59 | # set problem state, enable interrupts |
60 | 60 | ||
61 | ori r31, r31, msr_pr |
61 | ori r31, r31, msr_pr |
62 | ori r31, r31, msr_ee |
62 | ori r31, r31, msr_ee |
63 | mtsrr1 r31 |
63 | mtsrr1 r31 |
64 | 64 | ||
65 | # set stack |
65 | # set stack |
66 | 66 | ||
67 | mr sp, r4 |
67 | mr sp, r4 |
68 | 68 | ||
- | 69 | # %r3 is defined to hold pcb_ptr - set it to 0 |
|
- | 70 | ||
- | 71 | xor r3, r3, r3 |
|
- | 72 | ||
69 | # jump to userspace |
73 | # jump to userspace |
70 | 74 | ||
71 | rfi |
75 | rfi |
72 | 76 | ||
73 | iret: |
77 | iret: |
74 | 78 | ||
75 | # disable interrupts |
79 | # disable interrupts |
76 | 80 | ||
77 | mfmsr r31 |
81 | mfmsr r31 |
78 | rlwinm r31, r31, 0, 17, 15 |
82 | rlwinm r31, r31, 0, 17, 15 |
79 | mtmsr r31 |
83 | mtmsr r31 |
80 | 84 | ||
81 | lwz r0, 8(sp) |
85 | lwz r0, 8(sp) |
82 | lwz r2, 12(sp) |
86 | lwz r2, 12(sp) |
83 | lwz r3, 16(sp) |
87 | lwz r3, 16(sp) |
84 | lwz r4, 20(sp) |
88 | lwz r4, 20(sp) |
85 | lwz r5, 24(sp) |
89 | lwz r5, 24(sp) |
86 | lwz r6, 28(sp) |
90 | lwz r6, 28(sp) |
87 | lwz r7, 32(sp) |
91 | lwz r7, 32(sp) |
88 | lwz r8, 36(sp) |
92 | lwz r8, 36(sp) |
89 | lwz r9, 40(sp) |
93 | lwz r9, 40(sp) |
90 | lwz r10, 44(sp) |
94 | lwz r10, 44(sp) |
91 | lwz r11, 48(sp) |
95 | lwz r11, 48(sp) |
92 | lwz r13, 52(sp) |
96 | lwz r13, 52(sp) |
93 | lwz r14, 56(sp) |
97 | lwz r14, 56(sp) |
94 | lwz r15, 60(sp) |
98 | lwz r15, 60(sp) |
95 | lwz r16, 64(sp) |
99 | lwz r16, 64(sp) |
96 | lwz r17, 68(sp) |
100 | lwz r17, 68(sp) |
97 | lwz r18, 72(sp) |
101 | lwz r18, 72(sp) |
98 | lwz r19, 76(sp) |
102 | lwz r19, 76(sp) |
99 | lwz r20, 80(sp) |
103 | lwz r20, 80(sp) |
100 | lwz r21, 84(sp) |
104 | lwz r21, 84(sp) |
101 | lwz r22, 88(sp) |
105 | lwz r22, 88(sp) |
102 | lwz r23, 92(sp) |
106 | lwz r23, 92(sp) |
103 | lwz r24, 96(sp) |
107 | lwz r24, 96(sp) |
104 | lwz r25, 100(sp) |
108 | lwz r25, 100(sp) |
105 | lwz r26, 104(sp) |
109 | lwz r26, 104(sp) |
106 | lwz r27, 108(sp) |
110 | lwz r27, 108(sp) |
107 | lwz r28, 112(sp) |
111 | lwz r28, 112(sp) |
108 | lwz r29, 116(sp) |
112 | lwz r29, 116(sp) |
109 | lwz r30, 120(sp) |
113 | lwz r30, 120(sp) |
110 | lwz r31, 124(sp) |
114 | lwz r31, 124(sp) |
111 | 115 | ||
112 | lwz r12, 128(sp) |
116 | lwz r12, 128(sp) |
113 | mtcr r12 |
117 | mtcr r12 |
114 | 118 | ||
115 | lwz r12, 132(sp) |
119 | lwz r12, 132(sp) |
116 | mtsrr0 r12 |
120 | mtsrr0 r12 |
117 | 121 | ||
118 | lwz r12, 136(sp) |
122 | lwz r12, 136(sp) |
119 | mtsrr1 r12 |
123 | mtsrr1 r12 |
120 | 124 | ||
121 | lwz r12, 140(sp) |
125 | lwz r12, 140(sp) |
122 | mtlr r12 |
126 | mtlr r12 |
123 | 127 | ||
124 | lwz r12, 144(sp) |
128 | lwz r12, 144(sp) |
125 | mtctr r12 |
129 | mtctr r12 |
126 | 130 | ||
127 | lwz r12, 148(sp) |
131 | lwz r12, 148(sp) |
128 | mtxer r12 |
132 | mtxer r12 |
129 | 133 | ||
130 | lwz r12, 152(sp) |
134 | lwz r12, 152(sp) |
131 | lwz sp, 156(sp) |
135 | lwz sp, 156(sp) |
132 | 136 | ||
133 | rfi |
137 | rfi |
134 | 138 | ||
135 | iret_syscall: |
139 | iret_syscall: |
136 | 140 | ||
137 | # reset decrementer |
141 | # reset decrementer |
138 | 142 | ||
139 | li r31, 1000 |
143 | li r31, 1000 |
140 | mtdec r31 |
144 | mtdec r31 |
141 | 145 | ||
142 | # disable interrupts |
146 | # disable interrupts |
143 | 147 | ||
144 | mfmsr r31 |
148 | mfmsr r31 |
145 | rlwinm r31, r31, 0, 17, 15 |
149 | rlwinm r31, r31, 0, 17, 15 |
146 | mtmsr r31 |
150 | mtmsr r31 |
147 | 151 | ||
148 | lwz r0, 8(sp) |
152 | lwz r0, 8(sp) |
149 | lwz r2, 12(sp) |
153 | lwz r2, 12(sp) |
150 | lwz r4, 20(sp) |
154 | lwz r4, 20(sp) |
151 | lwz r5, 24(sp) |
155 | lwz r5, 24(sp) |
152 | lwz r6, 28(sp) |
156 | lwz r6, 28(sp) |
153 | lwz r7, 32(sp) |
157 | lwz r7, 32(sp) |
154 | lwz r8, 36(sp) |
158 | lwz r8, 36(sp) |
155 | lwz r9, 40(sp) |
159 | lwz r9, 40(sp) |
156 | lwz r10, 44(sp) |
160 | lwz r10, 44(sp) |
157 | lwz r11, 48(sp) |
161 | lwz r11, 48(sp) |
158 | lwz r13, 52(sp) |
162 | lwz r13, 52(sp) |
159 | lwz r14, 56(sp) |
163 | lwz r14, 56(sp) |
160 | lwz r15, 60(sp) |
164 | lwz r15, 60(sp) |
161 | lwz r16, 64(sp) |
165 | lwz r16, 64(sp) |
162 | lwz r17, 68(sp) |
166 | lwz r17, 68(sp) |
163 | lwz r18, 72(sp) |
167 | lwz r18, 72(sp) |
164 | lwz r19, 76(sp) |
168 | lwz r19, 76(sp) |
165 | lwz r20, 80(sp) |
169 | lwz r20, 80(sp) |
166 | lwz r21, 84(sp) |
170 | lwz r21, 84(sp) |
167 | lwz r22, 88(sp) |
171 | lwz r22, 88(sp) |
168 | lwz r23, 92(sp) |
172 | lwz r23, 92(sp) |
169 | lwz r24, 96(sp) |
173 | lwz r24, 96(sp) |
170 | lwz r25, 100(sp) |
174 | lwz r25, 100(sp) |
171 | lwz r26, 104(sp) |
175 | lwz r26, 104(sp) |
172 | lwz r27, 108(sp) |
176 | lwz r27, 108(sp) |
173 | lwz r28, 112(sp) |
177 | lwz r28, 112(sp) |
174 | lwz r29, 116(sp) |
178 | lwz r29, 116(sp) |
175 | lwz r30, 120(sp) |
179 | lwz r30, 120(sp) |
176 | lwz r31, 124(sp) |
180 | lwz r31, 124(sp) |
177 | 181 | ||
178 | lwz r12, 128(sp) |
182 | lwz r12, 128(sp) |
179 | mtcr r12 |
183 | mtcr r12 |
180 | 184 | ||
181 | lwz r12, 132(sp) |
185 | lwz r12, 132(sp) |
182 | mtsrr0 r12 |
186 | mtsrr0 r12 |
183 | 187 | ||
184 | lwz r12, 136(sp) |
188 | lwz r12, 136(sp) |
185 | mtsrr1 r12 |
189 | mtsrr1 r12 |
186 | 190 | ||
187 | lwz r12, 140(sp) |
191 | lwz r12, 140(sp) |
188 | mtlr r12 |
192 | mtlr r12 |
189 | 193 | ||
190 | lwz r12, 144(sp) |
194 | lwz r12, 144(sp) |
191 | mtctr r12 |
195 | mtctr r12 |
192 | 196 | ||
193 | lwz r12, 148(sp) |
197 | lwz r12, 148(sp) |
194 | mtxer r12 |
198 | mtxer r12 |
195 | 199 | ||
196 | lwz r12, 152(sp) |
200 | lwz r12, 152(sp) |
197 | lwz sp, 156(sp) |
201 | lwz sp, 156(sp) |
198 | 202 | ||
199 | rfi |
203 | rfi |
200 | 204 | ||
201 | memsetb: |
205 | memsetb: |
202 | rlwimi r5, r5, 8, 16, 23 |
206 | rlwimi r5, r5, 8, 16, 23 |
203 | rlwimi r5, r5, 16, 0, 15 |
207 | rlwimi r5, r5, 16, 0, 15 |
204 | 208 | ||
205 | addi r14, r3, -4 |
209 | addi r14, r3, -4 |
206 | 210 | ||
207 | cmplwi 0, r4, 4 |
211 | cmplwi 0, r4, 4 |
208 | blt 7f |
212 | blt 7f |
209 | 213 | ||
210 | stwu r5, 4(r14) |
214 | stwu r5, 4(r14) |
211 | beqlr |
215 | beqlr |
212 | 216 | ||
213 | andi. r15, r14, 3 |
217 | andi. r15, r14, 3 |
214 | add r4, r15, r4 |
218 | add r4, r15, r4 |
215 | subf r14, r15, r14 |
219 | subf r14, r15, r14 |
216 | srwi r15, r4, 2 |
220 | srwi r15, r4, 2 |
217 | mtctr r15 |
221 | mtctr r15 |
218 | 222 | ||
219 | bdz 6f |
223 | bdz 6f |
220 | 224 | ||
221 | 1: |
225 | 1: |
222 | stwu r5, 4(r14) |
226 | stwu r5, 4(r14) |
223 | bdnz 1b |
227 | bdnz 1b |
224 | 228 | ||
225 | 6: |
229 | 6: |
226 | 230 | ||
227 | andi. r4, r4, 3 |
231 | andi. r4, r4, 3 |
228 | 232 | ||
229 | 7: |
233 | 7: |
230 | 234 | ||
231 | cmpwi 0, r4, 0 |
235 | cmpwi 0, r4, 0 |
232 | beqlr |
236 | beqlr |
233 | 237 | ||
234 | mtctr r4 |
238 | mtctr r4 |
235 | addi r6, r6, 3 |
239 | addi r6, r6, 3 |
236 | 240 | ||
237 | 8: |
241 | 8: |
238 | 242 | ||
239 | stbu r5, 1(r14) |
243 | stbu r5, 1(r14) |
240 | bdnz 8b |
244 | bdnz 8b |
241 | 245 | ||
242 | blr |
246 | blr |
243 | 247 | ||
244 | memcpy: |
248 | memcpy: |
245 | memcpy_from_uspace: |
249 | memcpy_from_uspace: |
246 | memcpy_to_uspace: |
250 | memcpy_to_uspace: |
247 | 251 | ||
248 | srwi. r7, r5, 3 |
252 | srwi. r7, r5, 3 |
249 | addi r6, r3, -4 |
253 | addi r6, r3, -4 |
250 | addi r4, r4, -4 |
254 | addi r4, r4, -4 |
251 | beq 2f |
255 | beq 2f |
252 | 256 | ||
253 | andi. r0, r6, 3 |
257 | andi. r0, r6, 3 |
254 | mtctr r7 |
258 | mtctr r7 |
255 | bne 5f |
259 | bne 5f |
256 | 260 | ||
257 | 1: |
261 | 1: |
258 | 262 | ||
259 | lwz r7, 4(r4) |
263 | lwz r7, 4(r4) |
260 | lwzu r8, 8(r4) |
264 | lwzu r8, 8(r4) |
261 | stw r7, 4(r6) |
265 | stw r7, 4(r6) |
262 | stwu r8, 8(r6) |
266 | stwu r8, 8(r6) |
263 | bdnz 1b |
267 | bdnz 1b |
264 | 268 | ||
265 | andi. r5, r5, 7 |
269 | andi. r5, r5, 7 |
266 | 270 | ||
267 | 2: |
271 | 2: |
268 | 272 | ||
269 | cmplwi 0, r5, 4 |
273 | cmplwi 0, r5, 4 |
270 | blt 3f |
274 | blt 3f |
271 | 275 | ||
272 | lwzu r0, 4(r4) |
276 | lwzu r0, 4(r4) |
273 | addi r5, r5, -4 |
277 | addi r5, r5, -4 |
274 | stwu r0, 4(r6) |
278 | stwu r0, 4(r6) |
275 | 279 | ||
276 | 3: |
280 | 3: |
277 | 281 | ||
278 | cmpwi 0, r5, 0 |
282 | cmpwi 0, r5, 0 |
279 | beqlr |
283 | beqlr |
280 | mtctr r5 |
284 | mtctr r5 |
281 | addi r4, r4, 3 |
285 | addi r4, r4, 3 |
282 | addi r6, r6, 3 |
286 | addi r6, r6, 3 |
283 | 287 | ||
284 | 4: |
288 | 4: |
285 | 289 | ||
286 | lbzu r0, 1(r4) |
290 | lbzu r0, 1(r4) |
287 | stbu r0, 1(r6) |
291 | stbu r0, 1(r6) |
288 | bdnz 4b |
292 | bdnz 4b |
289 | blr |
293 | blr |
290 | 294 | ||
291 | 5: |
295 | 5: |
292 | 296 | ||
293 | subfic r0, r0, 4 |
297 | subfic r0, r0, 4 |
294 | mtctr r0 |
298 | mtctr r0 |
295 | 299 | ||
296 | 6: |
300 | 6: |
297 | 301 | ||
298 | lbz r7, 4(r4) |
302 | lbz r7, 4(r4) |
299 | addi r4, r4, 1 |
303 | addi r4, r4, 1 |
300 | stb r7, 4(r6) |
304 | stb r7, 4(r6) |
301 | addi r6, r6, 1 |
305 | addi r6, r6, 1 |
302 | bdnz 6b |
306 | bdnz 6b |
303 | subf r5, r0, r5 |
307 | subf r5, r0, r5 |
304 | rlwinm. r7, r5, 32-3, 3, 31 |
308 | rlwinm. r7, r5, 32-3, 3, 31 |
305 | beq 2b |
309 | beq 2b |
306 | mtctr r7 |
310 | mtctr r7 |
307 | b 1b |
311 | b 1b |
308 | 312 | ||
309 | memcpy_from_uspace_failover_address: |
313 | memcpy_from_uspace_failover_address: |
310 | memcpy_to_uspace_failover_address: |
314 | memcpy_to_uspace_failover_address: |
311 | b memcpy_from_uspace_failover_address |
315 | b memcpy_from_uspace_failover_address |
312 | 316 |