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1 | /* |
1 | /* |
2 | * Copyright (c) 2005 Jakub Jermar |
2 | * Copyright (c) 2005 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup mips32mm |
29 | /** @addtogroup mips32mm |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | */ |
33 | */ |
34 | 34 | ||
35 | #include <macros.h> |
35 | #include <macros.h> |
36 | #include <arch/mm/frame.h> |
36 | #include <arch/mm/frame.h> |
37 | #include <arch/mm/tlb.h> |
37 | #include <arch/mm/tlb.h> |
38 | #include <interrupt.h> |
38 | #include <interrupt.h> |
39 | #include <mm/frame.h> |
39 | #include <mm/frame.h> |
40 | #include <mm/asid.h> |
40 | #include <mm/asid.h> |
41 | #include <config.h> |
41 | #include <config.h> |
42 | #include <arch/drivers/msim.h> |
42 | #include <arch/drivers/msim.h> |
43 | #include <arch/drivers/serial.h> |
43 | #include <arch/drivers/serial.h> |
44 | #include <print.h> |
44 | #include <print.h> |
45 | 45 | ||
46 | #define ZERO_PAGE_MASK TLB_PAGE_MASK_256K |
46 | #define ZERO_PAGE_MASK TLB_PAGE_MASK_256K |
47 | #define ZERO_FRAMES 16384 |
47 | #define ZERO_FRAMES 16384 |
48 | #define ZERO_PAGE_WIDTH 18 /* 256K */ |
48 | #define ZERO_PAGE_WIDTH 18 /* 256K */ |
49 | #define ZERO_PAGE_SIZE (1 << ZERO_PAGE_WIDTH) |
49 | #define ZERO_PAGE_SIZE (1 << ZERO_PAGE_WIDTH) |
50 | #define ZERO_PAGE_ASID ASID_INVALID |
50 | #define ZERO_PAGE_ASID ASID_INVALID |
51 | #define ZERO_PAGE_TLBI 0 |
51 | #define ZERO_PAGE_TLBI 0 |
52 | #define ZERO_PAGE_ADDR 0 |
52 | #define ZERO_PAGE_ADDR 0 |
53 | #define ZERO_PAGE_OFFSET (ZERO_PAGE_SIZE / sizeof(uint32_t) - 1) |
53 | #define ZERO_PAGE_OFFSET (ZERO_PAGE_SIZE / sizeof(uint32_t) - 1) |
54 | #define ZERO_PAGE_VALUE (((volatile uint32_t *) ZERO_PAGE_ADDR)[ZERO_PAGE_OFFSET]) |
54 | #define ZERO_PAGE_VALUE (((volatile uint32_t *) ZERO_PAGE_ADDR)[ZERO_PAGE_OFFSET]) |
55 | 55 | ||
56 | #define MAX_REGIONS 32 |
56 | #define MAX_REGIONS 32 |
57 | 57 | ||
58 | typedef struct { |
58 | typedef struct { |
59 | pfn_t start; |
59 | pfn_t start; |
60 | pfn_t count; |
60 | pfn_t count; |
61 | } phys_region_t; |
61 | } phys_region_t; |
62 | 62 | ||
63 | static count_t phys_regions_count = 0; |
63 | static count_t phys_regions_count = 0; |
64 | static phys_region_t phys_regions[MAX_REGIONS]; |
64 | static phys_region_t phys_regions[MAX_REGIONS]; |
65 | 65 | ||
66 | 66 | ||
67 | /** Check whether frame is available |
67 | /** Check whether frame is available |
68 | * |
68 | * |
69 | * Returns true if given frame is generally available for use. |
69 | * Returns true if given frame is generally available for use. |
70 | * Returns false if given frame is used for physical memory |
70 | * Returns false if given frame is used for physical memory |
71 | * mapped devices and cannot be used. |
71 | * mapped devices and cannot be used. |
72 | * |
72 | * |
73 | */ |
73 | */ |
74 | static bool frame_available(pfn_t frame) |
74 | static bool frame_available(pfn_t frame) |
75 | { |
75 | { |
76 | /* MSIM device (dprinter) */ |
76 | /* MSIM device (dprinter) */ |
77 | if (frame == (KA2PA(MSIM_VIDEORAM) >> ZERO_PAGE_WIDTH)) |
77 | if (frame == (KA2PA(MSIM_VIDEORAM) >> ZERO_PAGE_WIDTH)) |
78 | return false; |
78 | return false; |
79 | 79 | ||
80 | /* MSIM device (dkeyboard) */ |
80 | /* MSIM device (dkeyboard) */ |
81 | if (frame == (KA2PA(MSIM_KBD_ADDRESS) >> ZERO_PAGE_WIDTH)) |
81 | if (frame == (KA2PA(MSIM_KBD_ADDRESS) >> ZERO_PAGE_WIDTH)) |
82 | return false; |
82 | return false; |
83 | 83 | ||
84 | /* Simics device (serial line) */ |
84 | /* Simics device (serial line) */ |
85 | if (frame == (KA2PA(SERIAL_ADDRESS) >> ZERO_PAGE_WIDTH)) |
85 | if (frame == (KA2PA(SERIAL_ADDRESS) >> ZERO_PAGE_WIDTH)) |
86 | return false; |
86 | return false; |
87 | 87 | ||
88 | return true; |
88 | return true; |
89 | } |
89 | } |
90 | 90 | ||
91 | 91 | ||
92 | /** Check whether frame is safe to write |
92 | /** Check whether frame is safe to write |
93 | * |
93 | * |
94 | * Returns true if given frame is safe for read/write test. |
94 | * Returns true if given frame is safe for read/write test. |
95 | * Returns false if given frame should not be touched. |
95 | * Returns false if given frame should not be touched. |
96 | * |
96 | * |
97 | */ |
97 | */ |
98 | static bool frame_safe(pfn_t frame) |
98 | static bool frame_safe(pfn_t frame) |
99 | { |
99 | { |
100 | /* Kernel structures */ |
100 | /* Kernel structures */ |
101 | if ((frame << ZERO_PAGE_WIDTH) < KA2PA(config.base)) |
101 | if ((frame << ZERO_PAGE_WIDTH) < KA2PA(config.base)) |
102 | return false; |
102 | return false; |
103 | 103 | ||
104 | /* Kernel */ |
104 | /* Kernel */ |
105 | if (overlaps(frame << ZERO_PAGE_WIDTH, ZERO_PAGE_SIZE, |
105 | if (overlaps(frame << ZERO_PAGE_WIDTH, ZERO_PAGE_SIZE, |
106 | KA2PA(config.base), config.kernel_size)) |
106 | KA2PA(config.base), config.kernel_size)) |
107 | return false; |
107 | return false; |
108 | 108 | ||
109 | /* Kernel stack */ |
109 | /* Kernel stack */ |
110 | if (overlaps(frame << ZERO_PAGE_WIDTH, ZERO_PAGE_SIZE, |
110 | if (overlaps(frame << ZERO_PAGE_WIDTH, ZERO_PAGE_SIZE, |
111 | KA2PA(config.stack_base), config.stack_size)) |
111 | KA2PA(config.stack_base), config.stack_size)) |
112 | return false; |
112 | return false; |
113 | 113 | ||
114 | /* Init tasks */ |
114 | /* Init tasks */ |
115 | bool safe = true; |
115 | bool safe = true; |
116 | count_t i; |
116 | count_t i; |
117 | for (i = 0; i < init.cnt; i++) |
117 | for (i = 0; i < init.cnt; i++) |
118 | if (overlaps(frame << ZERO_PAGE_WIDTH, ZERO_PAGE_SIZE, |
118 | if (overlaps(frame << ZERO_PAGE_WIDTH, ZERO_PAGE_SIZE, |
119 | KA2PA(init.tasks[i].addr), init.tasks[i].size)) { |
119 | KA2PA(init.tasks[i].addr), init.tasks[i].size)) { |
120 | safe = false; |
120 | safe = false; |
121 | break; |
121 | break; |
122 | } |
122 | } |
123 | 123 | ||
124 | return safe; |
124 | return safe; |
125 | } |
125 | } |
126 | 126 | ||
127 | static void frame_add_region(pfn_t start_frame, pfn_t end_frame) |
127 | static void frame_add_region(pfn_t start_frame, pfn_t end_frame) |
128 | { |
128 | { |
129 | if (end_frame > start_frame) { |
129 | if (end_frame > start_frame) { |
130 | /* Convert 1M frames to 16K frames */ |
130 | /* Convert 1M frames to 16K frames */ |
131 | pfn_t first = ADDR2PFN(start_frame << ZERO_PAGE_WIDTH); |
131 | pfn_t first = ADDR2PFN(start_frame << ZERO_PAGE_WIDTH); |
132 | pfn_t count = ADDR2PFN((end_frame - start_frame) << ZERO_PAGE_WIDTH); |
132 | pfn_t count = ADDR2PFN((end_frame - start_frame) << ZERO_PAGE_WIDTH); |
133 | 133 | ||
134 | /* Interrupt vector frame is blacklisted */ |
134 | /* Interrupt vector frame is blacklisted */ |
135 | pfn_t conf_frame; |
135 | pfn_t conf_frame; |
136 | if (start_frame == 0) |
136 | if (first == 0) |
137 | conf_frame = 1; |
137 | conf_frame = 1; |
138 | else |
138 | else |
139 | conf_frame = first; |
139 | conf_frame = first; |
140 | 140 | ||
141 | zone_create(first, count, conf_frame, 0); |
141 | zone_create(first, count, conf_frame, 0); |
142 | 142 | ||
143 | if (phys_regions_count < MAX_REGIONS) { |
143 | if (phys_regions_count < MAX_REGIONS) { |
144 | phys_regions[phys_regions_count].start = first; |
144 | phys_regions[phys_regions_count].start = first; |
145 | phys_regions[phys_regions_count].count = count; |
145 | phys_regions[phys_regions_count].count = count; |
146 | phys_regions_count++; |
146 | phys_regions_count++; |
147 | } |
147 | } |
148 | } |
148 | } |
149 | } |
149 | } |
150 | 150 | ||
151 | 151 | ||
152 | /** Create memory zones |
152 | /** Create memory zones |
153 | * |
153 | * |
154 | * Walk through available 1 MB chunks of physical |
154 | * Walk through available 256 KB chunks of physical |
155 | * memory and create zones. |
155 | * memory and create zones. |
156 | * |
156 | * |
157 | * Note: It is assumed that the TLB is not yet being |
157 | * Note: It is assumed that the TLB is not yet being |
158 | * used in any way, thus there is no interference. |
158 | * used in any way, thus there is no interference. |
159 | * |
159 | * |
160 | */ |
160 | */ |
161 | void frame_arch_init(void) |
161 | void frame_arch_init(void) |
162 | { |
162 | { |
163 | ipl_t ipl = interrupts_disable(); |
163 | ipl_t ipl = interrupts_disable(); |
164 | 164 | ||
165 | /* Clear and initialize TLB */ |
165 | /* Clear and initialize TLB */ |
166 | cp0_pagemask_write(ZERO_PAGE_MASK); |
166 | cp0_pagemask_write(ZERO_PAGE_MASK); |
167 | cp0_entry_lo0_write(0); |
167 | cp0_entry_lo0_write(0); |
168 | cp0_entry_lo1_write(0); |
168 | cp0_entry_lo1_write(0); |
169 | cp0_entry_hi_write(0); |
169 | cp0_entry_hi_write(0); |
170 | 170 | ||
171 | count_t i; |
171 | count_t i; |
172 | for (i = 0; i < TLB_ENTRY_COUNT; i++) { |
172 | for (i = 0; i < TLB_ENTRY_COUNT; i++) { |
173 | cp0_index_write(i); |
173 | cp0_index_write(i); |
174 | tlbwi(); |
174 | tlbwi(); |
175 | } |
175 | } |
176 | 176 | ||
177 | pfn_t start_frame = 0; |
177 | pfn_t start_frame = 0; |
178 | pfn_t frame; |
178 | pfn_t frame; |
179 | bool avail = true; |
179 | bool avail = true; |
180 | 180 | ||
181 | /* Walk through all 1 MB frames */ |
181 | /* Walk through all 1 MB frames */ |
182 | for (frame = 0; frame < ZERO_FRAMES; frame++) { |
182 | for (frame = 0; frame < ZERO_FRAMES; frame++) { |
183 | if (!frame_available(frame)) |
183 | if (!frame_available(frame)) |
184 | avail = false; |
184 | avail = false; |
185 | else { |
185 | else { |
186 | if (frame_safe(frame)) { |
186 | if (frame_safe(frame)) { |
187 | entry_lo_t lo0; |
187 | entry_lo_t lo0; |
188 | entry_lo_t lo1; |
188 | entry_lo_t lo1; |
189 | entry_hi_t hi; |
189 | entry_hi_t hi; |
190 | tlb_prepare_entry_lo(&lo0, false, true, true, false, frame << (ZERO_PAGE_WIDTH - 12)); |
190 | tlb_prepare_entry_lo(&lo0, false, true, true, false, frame << (ZERO_PAGE_WIDTH - 12)); |
191 | tlb_prepare_entry_lo(&lo1, false, false, false, false, 0); |
191 | tlb_prepare_entry_lo(&lo1, false, false, false, false, 0); |
192 | tlb_prepare_entry_hi(&hi, ZERO_PAGE_ASID, ZERO_PAGE_ADDR); |
192 | tlb_prepare_entry_hi(&hi, ZERO_PAGE_ASID, ZERO_PAGE_ADDR); |
193 | 193 | ||
194 | cp0_pagemask_write(ZERO_PAGE_MASK); |
194 | cp0_pagemask_write(ZERO_PAGE_MASK); |
195 | cp0_entry_lo0_write(lo0.value); |
195 | cp0_entry_lo0_write(lo0.value); |
196 | cp0_entry_lo1_write(lo1.value); |
196 | cp0_entry_lo1_write(lo1.value); |
197 | cp0_entry_hi_write(hi.value); |
197 | cp0_entry_hi_write(hi.value); |
198 | cp0_index_write(ZERO_PAGE_TLBI); |
198 | cp0_index_write(ZERO_PAGE_TLBI); |
199 | tlbwi(); |
199 | tlbwi(); |
200 | 200 | ||
201 | ZERO_PAGE_VALUE = 0; |
201 | ZERO_PAGE_VALUE = 0; |
202 | if (ZERO_PAGE_VALUE != 0) |
202 | if (ZERO_PAGE_VALUE != 0) |
203 | avail = false; |
203 | avail = false; |
204 | else { |
204 | else { |
205 | ZERO_PAGE_VALUE = 0xdeadbeef; |
205 | ZERO_PAGE_VALUE = 0xdeadbeef; |
206 | if (ZERO_PAGE_VALUE != 0xdeadbeef) |
206 | if (ZERO_PAGE_VALUE != 0xdeadbeef) |
207 | avail = false; |
207 | avail = false; |
208 | } |
208 | } |
209 | } |
209 | } |
210 | } |
210 | } |
211 | 211 | ||
212 | if (!avail) { |
212 | if (!avail) { |
213 | frame_add_region(start_frame, frame); |
213 | frame_add_region(start_frame, frame); |
214 | start_frame = frame + 1; |
214 | start_frame = frame + 1; |
215 | avail = true; |
215 | avail = true; |
216 | } |
216 | } |
217 | } |
217 | } |
218 | 218 | ||
219 | frame_add_region(start_frame, frame); |
219 | frame_add_region(start_frame, frame); |
220 | 220 | ||
221 | /* Blacklist interrupt vector frame */ |
221 | /* Blacklist interrupt vector frame */ |
222 | frame_mark_unavailable(0, 1); |
222 | frame_mark_unavailable(0, 1); |
223 | 223 | ||
224 | /* Cleanup */ |
224 | /* Cleanup */ |
225 | cp0_pagemask_write(ZERO_PAGE_MASK); |
225 | cp0_pagemask_write(ZERO_PAGE_MASK); |
226 | cp0_entry_lo0_write(0); |
226 | cp0_entry_lo0_write(0); |
227 | cp0_entry_lo1_write(0); |
227 | cp0_entry_lo1_write(0); |
228 | cp0_entry_hi_write(0); |
228 | cp0_entry_hi_write(0); |
229 | cp0_index_write(ZERO_PAGE_TLBI); |
229 | cp0_index_write(ZERO_PAGE_TLBI); |
230 | tlbwi(); |
230 | tlbwi(); |
231 | 231 | ||
232 | interrupts_restore(ipl); |
232 | interrupts_restore(ipl); |
233 | } |
233 | } |
234 | 234 | ||
235 | 235 | ||
236 | void physmem_print(void) |
236 | void physmem_print(void) |
237 | { |
237 | { |
238 | printf("Base Size\n"); |
238 | printf("Base Size\n"); |
239 | printf("---------- ----------\n"); |
239 | printf("---------- ----------\n"); |
240 | 240 | ||
241 | count_t i; |
241 | count_t i; |
242 | for (i = 0; i < phys_regions_count; i++) { |
242 | for (i = 0; i < phys_regions_count; i++) { |
243 | printf("%#010x %10u\n", |
243 | printf("%#010x %10u\n", |
244 | PFN2ADDR(phys_regions[i].start), PFN2ADDR(phys_regions[i].count)); |
244 | PFN2ADDR(phys_regions[i].start), PFN2ADDR(phys_regions[i].count)); |
245 | } |
245 | } |
246 | } |
246 | } |
247 | 247 | ||
248 | /** @} |
248 | /** @} |
249 | */ |
249 | */ |
250 | 250 |