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1 | /* |
1 | /* |
2 | * Copyright (C) 2003-2004 Jakub Jermar |
2 | * Copyright (C) 2003-2004 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup mips32interrupt |
29 | /** @addtogroup mips32interrupt |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | */ |
33 | */ |
34 | 34 | ||
35 | #include <interrupt.h> |
35 | #include <interrupt.h> |
36 | #include <arch/interrupt.h> |
36 | #include <arch/interrupt.h> |
37 | #include <arch/types.h> |
37 | #include <arch/types.h> |
38 | #include <arch.h> |
38 | #include <arch.h> |
39 | #include <arch/cp0.h> |
39 | #include <arch/cp0.h> |
40 | #include <time/clock.h> |
40 | #include <time/clock.h> |
41 | #include <arch/drivers/arc.h> |
41 | #include <arch/drivers/arc.h> |
42 | - | ||
43 | #include <ipc/sysipc.h> |
42 | #include <ipc/sysipc.h> |
- | 43 | #include <ddi/device.h> |
|
- | 44 | #include <ddi/irq.h> |
|
- | 45 | ||
- | 46 | #define IRQ_COUNT 8 |
|
- | 47 | #define TIMER_IRQ 7 |
|
- | 48 | ||
- | 49 | function timer_fnc = NULL; |
|
- | 50 | static irq_t timer_irq; |
|
44 | 51 | ||
45 | /** Disable interrupts. |
52 | /** Disable interrupts. |
46 | * |
53 | * |
47 | * @return Old interrupt priority level. |
54 | * @return Old interrupt priority level. |
48 | */ |
55 | */ |
49 | ipl_t interrupts_disable(void) |
56 | ipl_t interrupts_disable(void) |
50 | { |
57 | { |
51 | ipl_t ipl = (ipl_t) cp0_status_read(); |
58 | ipl_t ipl = (ipl_t) cp0_status_read(); |
52 | cp0_status_write(ipl & ~cp0_status_ie_enabled_bit); |
59 | cp0_status_write(ipl & ~cp0_status_ie_enabled_bit); |
53 | return ipl; |
60 | return ipl; |
54 | } |
61 | } |
55 | 62 | ||
56 | /** Enable interrupts. |
63 | /** Enable interrupts. |
57 | * |
64 | * |
58 | * @return Old interrupt priority level. |
65 | * @return Old interrupt priority level. |
59 | */ |
66 | */ |
60 | ipl_t interrupts_enable(void) |
67 | ipl_t interrupts_enable(void) |
61 | { |
68 | { |
62 | ipl_t ipl = (ipl_t) cp0_status_read(); |
69 | ipl_t ipl = (ipl_t) cp0_status_read(); |
63 | cp0_status_write(ipl | cp0_status_ie_enabled_bit); |
70 | cp0_status_write(ipl | cp0_status_ie_enabled_bit); |
64 | return ipl; |
71 | return ipl; |
65 | } |
72 | } |
66 | 73 | ||
67 | /** Restore interrupt priority level. |
74 | /** Restore interrupt priority level. |
68 | * |
75 | * |
69 | * @param ipl Saved interrupt priority level. |
76 | * @param ipl Saved interrupt priority level. |
70 | */ |
77 | */ |
71 | void interrupts_restore(ipl_t ipl) |
78 | void interrupts_restore(ipl_t ipl) |
72 | { |
79 | { |
73 | cp0_status_write(cp0_status_read() | (ipl & cp0_status_ie_enabled_bit)); |
80 | cp0_status_write(cp0_status_read() | (ipl & cp0_status_ie_enabled_bit)); |
74 | } |
81 | } |
75 | 82 | ||
76 | /** Read interrupt priority level. |
83 | /** Read interrupt priority level. |
77 | * |
84 | * |
78 | * @return Current interrupt priority level. |
85 | * @return Current interrupt priority level. |
79 | */ |
86 | */ |
80 | ipl_t interrupts_read(void) |
87 | ipl_t interrupts_read(void) |
81 | { |
88 | { |
82 | return cp0_status_read(); |
89 | return cp0_status_read(); |
83 | } |
90 | } |
84 | 91 | ||
85 | /* TODO: This is SMP unsafe!!! */ |
92 | /* TODO: This is SMP unsafe!!! */ |
86 | static unsigned long nextcount; |
93 | static unsigned long nextcount; |
87 | /** Start hardware clock */ |
94 | /** Start hardware clock */ |
88 | static void timer_start(void) |
95 | static void timer_start(void) |
89 | { |
96 | { |
90 | nextcount = cp0_compare_value + cp0_count_read(); |
97 | nextcount = cp0_compare_value + cp0_count_read(); |
91 | cp0_compare_write(nextcount); |
98 | cp0_compare_write(nextcount); |
92 | } |
99 | } |
93 | 100 | ||
- | 101 | static irq_ownership_t timer_claim(void) |
|
- | 102 | { |
|
- | 103 | return IRQ_ACCEPT; |
|
- | 104 | } |
|
- | 105 | ||
94 | static void timer_exception(int n, istate_t *istate) |
106 | static void timer_irq_handler(irq_t *irq, void *arg, ...) |
95 | { |
107 | { |
96 | unsigned long drift; |
108 | unsigned long drift; |
97 | 109 | ||
98 | drift = cp0_count_read() - nextcount; |
110 | drift = cp0_count_read() - nextcount; |
99 | while (drift > cp0_compare_value) { |
111 | while (drift > cp0_compare_value) { |
100 | drift -= cp0_compare_value; |
112 | drift -= cp0_compare_value; |
101 | CPU->missed_clock_ticks++; |
113 | CPU->missed_clock_ticks++; |
102 | } |
114 | } |
103 | nextcount = cp0_count_read() + cp0_compare_value - drift; |
115 | nextcount = cp0_count_read() + cp0_compare_value - drift; |
104 | cp0_compare_write(nextcount); |
116 | cp0_compare_write(nextcount); |
105 | clock(); |
117 | clock(); |
106 | } |
- | |
107 | 118 | ||
108 | static void swint0(int n, istate_t *istate) |
- | |
109 | { |
- | |
110 | cp0_cause_write(cp0_cause_read() & ~(1 << 8)); /* clear SW0 interrupt */ |
- | |
111 | ipc_irq_send_notif(0); |
119 | if (timer_fnc != NULL) |
112 | } |
- | |
113 | - | ||
114 | static void swint1(int n, istate_t *istate) |
- | |
115 | { |
- | |
116 | cp0_cause_write(cp0_cause_read() & ~(1 << 9)); /* clear SW1 interrupt */ |
- | |
117 | ipc_irq_send_notif(1); |
120 | timer_fnc(); |
118 | } |
121 | } |
119 | 122 | ||
120 | /* Initialize basic tables for exception dispatching */ |
123 | /* Initialize basic tables for exception dispatching */ |
121 | void interrupt_init(void) |
124 | void interrupt_init(void) |
122 | { |
125 | { |
123 | int_register(TIMER_IRQ, "timer", timer_exception); |
- | |
124 | int_register(0, "swint0", swint0); |
- | |
125 | int_register(1, "swint1", swint1); |
126 | irq_init(IRQ_COUNT, IRQ_COUNT); |
126 | timer_start(); |
- | |
127 | } |
- | |
128 | 127 | ||
- | 128 | irq_initialize(&timer_irq); |
|
129 | static void ipc_int(int n, istate_t *istate) |
129 | timer_irq.devno = device_assign_devno(); |
130 | { |
- | |
- | 130 | timer_irq.inr = TIMER_IRQ; |
|
- | 131 | timer_irq.claim = timer_claim; |
|
131 | ipc_irq_send_notif(n-INT_OFFSET); |
132 | timer_irq.handler = timer_irq_handler; |
132 | } |
- | |
- | 133 | irq_register(&timer_irq); |
|
133 | 134 | ||
134 | /* Reregister irq to be IPC-ready */ |
- | |
135 | void irq_ipc_bind_arch(unative_t irq) |
- | |
136 | { |
- | |
137 | /* Do not allow to redefine timer */ |
- | |
138 | /* Swint0, Swint1 are already handled */ |
- | |
139 | if (irq == TIMER_IRQ || irq < 2) |
- | |
140 | return; |
135 | timer_start(); |
141 | int_register(irq, "ipc_int", ipc_int); |
136 | cp0_unmask_int(TIMER_IRQ); |
142 | } |
137 | } |
143 | 138 | ||
144 | /** @} |
139 | /** @} |
145 | */ |
140 | */ |
146 | 141 |