WebSVN – HelenOS – Diff – /trunk/kernel/arch/mips32/src/asm.S


#
# Copyright (c) 2003-2004 Jakub Jermar
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
#   notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
#   notice, this list of conditions and the following disclaimer in the
#   documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
#   derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
 
#include <arch/asm/regname.h>
 
.text
 
.macro cp0_read reg
	mfc0 $2,\reg
	j $31
	nop
.endm
 
.macro cp0_write reg
	mtc0 $4,\reg
	j $31
	nop
.endm
 
.set noat
.set noreorder
.set nomacro
 
.global asm_delay_loop
asm_delay_loop:
	j $31
	nop
 
.global cpu_halt
cpu_halt:
	j cpu_halt
	nop
 
 
.global memsetb
memsetb:
	j _memsetb
	nop
 
 
.global memcpy
.global memcpy_from_uspace
.global memcpy_to_uspace
.global memcpy_from_uspace_failover_address
.global memcpy_to_uspace_failover_address
memcpy:
memcpy_from_uspace:
memcpy_to_uspace:
	move	$t2,$a0			# save dst
	addiu	$v0,$a1,3
	li	$v1,-4			# 0xfffffffffffffffc
	and	$v0,$v0,$v1
	beq	$a1,$v0,3f
	move	$t0,$a0
 
 
0:
	beq	$a2,$zero,2f
	move	$a3,$zero
 
1:
	addu	$v0,$a1,$a3
	lbu	$a0,0($v0)
	addu	$v1,$t0,$a3
	addiu	$a3,$a3,1
	bne	$a3,$a2,1b
	sb	$a0,0($v1)
 
2:
	jr	$ra
	move	$v0,$t2
 
3:
	addiu	$v0,$a0,3
	and	$v0,$v0,$v1
	bne	$a0,$v0,0b
	srl	$t1,$a2,2
 
	beq	$t1,$zero,5f
	move	$a3,$zero
 
	move	$a3,$zero
	move	$a0,$zero
4:
	addu	$v0,$a1,$a0
	lw	$v1,0($v0)
	addiu	$a3,$a3,1
	addu	$v0,$t0,$a0
	sw	$v1,0($v0)
	bne	$a3,$t1,4b
	addiu	$a0,$a0,4
 
5:
	andi	$a2,$a2,0x3
	beq	$a2,$zero,2b
	nop
 
	sll	$v0,$a3,2
	addu	$t1,$v0,$t0
	move	$a3,$zero
	addu	$t0,$v0,$a1
6:
	addu	$v0,$t0,$a3
	lbu	$a0,0($v0)
	addu	$v1,$t1,$a3
	addiu	$a3,$a3,1
	bne	$a3,$a2,6b
	sb	$a0,0($v1)
 
	jr	$ra
	move	$v0,$t2
 
memcpy_from_uspace_failover_address:
memcpy_to_uspace_failover_address:
	jr	$ra
	move	$v0, $zero
 
 
 
.macro fpu_gp_save reg ctx
	mfc1 $t0,$\reg
	sw $t0, \reg*4(\ctx)
.endm
 
.macro fpu_gp_restore reg ctx
	lw $t0, \reg*4(\ctx)
	mtc1 $t0,$\reg
.endm
 
.macro fpu_ct_save reg ctx
	cfc1 $t0,$1
	sw $t0, (\reg+32)*4(\ctx)
.endm	
 
.macro fpu_ct_restore reg ctx
	lw $t0, (\reg+32)*4(\ctx)
	ctc1 $t0,$\reg
.endm
 
 
.global fpu_context_save
fpu_context_save:
#ifdef CONFIG_FPU
	fpu_gp_save 0,$a0
	fpu_gp_save 1,$a0
	fpu_gp_save 2,$a0
	fpu_gp_save 3,$a0
	fpu_gp_save 4,$a0
	fpu_gp_save 5,$a0
	fpu_gp_save 6,$a0
	fpu_gp_save 7,$a0
	fpu_gp_save 8,$a0
	fpu_gp_save 9,$a0
	fpu_gp_save 10,$a0
	fpu_gp_save 11,$a0
	fpu_gp_save 12,$a0
	fpu_gp_save 13,$a0
	fpu_gp_save 14,$a0
	fpu_gp_save 15,$a0
	fpu_gp_save 16,$a0
	fpu_gp_save 17,$a0
	fpu_gp_save 18,$a0
	fpu_gp_save 19,$a0
	fpu_gp_save 20,$a0
	fpu_gp_save 21,$a0
	fpu_gp_save 22,$a0
	fpu_gp_save 23,$a0
	fpu_gp_save 24,$a0
	fpu_gp_save 25,$a0
	fpu_gp_save 26,$a0
	fpu_gp_save 27,$a0
	fpu_gp_save 28,$a0
	fpu_gp_save 29,$a0
	fpu_gp_save 30,$a0
	fpu_gp_save 31,$a0
 
	fpu_ct_save 1,$a0
	fpu_ct_save 2,$a0
	fpu_ct_save 3,$a0
	fpu_ct_save 4,$a0
	fpu_ct_save 5,$a0
	fpu_ct_save 6,$a0
	fpu_ct_save 7,$a0
	fpu_ct_save 8,$a0
	fpu_ct_save 9,$a0
	fpu_ct_save 10,$a0
	fpu_ct_save 11,$a0
	fpu_ct_save 12,$a0
	fpu_ct_save 13,$a0
	fpu_ct_save 14,$a0
	fpu_ct_save 15,$a0
	fpu_ct_save 16,$a0
	fpu_ct_save 17,$a0
	fpu_ct_save 18,$a0
	fpu_ct_save 19,$a0
	fpu_ct_save 20,$a0
	fpu_ct_save 21,$a0
	fpu_ct_save 22,$a0
	fpu_ct_save 23,$a0
	fpu_ct_save 24,$a0
	fpu_ct_save 25,$a0
	fpu_ct_save 26,$a0
	fpu_ct_save 27,$a0
	fpu_ct_save 28,$a0
	fpu_ct_save 29,$a0
	fpu_ct_save 30,$a0
	fpu_ct_save 31,$a0
#endif		
	j $ra
	nop
 
.global fpu_context_restore
fpu_context_restore:
#ifdef CONFIG_FPU
	fpu_gp_restore 0,$a0
	fpu_gp_restore 1,$a0
	fpu_gp_restore 2,$a0
	fpu_gp_restore 3,$a0
	fpu_gp_restore 4,$a0
	fpu_gp_restore 5,$a0
	fpu_gp_restore 6,$a0
	fpu_gp_restore 7,$a0
	fpu_gp_restore 8,$a0
	fpu_gp_restore 9,$a0
	fpu_gp_restore 10,$a0
	fpu_gp_restore 11,$a0
	fpu_gp_restore 12,$a0
	fpu_gp_restore 13,$a0
	fpu_gp_restore 14,$a0
	fpu_gp_restore 15,$a0
	fpu_gp_restore 16,$a0
	fpu_gp_restore 17,$a0
	fpu_gp_restore 18,$a0
	fpu_gp_restore 19,$a0
	fpu_gp_restore 20,$a0
	fpu_gp_restore 21,$a0
	fpu_gp_restore 22,$a0
	fpu_gp_restore 23,$a0
	fpu_gp_restore 24,$a0
	fpu_gp_restore 25,$a0
	fpu_gp_restore 26,$a0
	fpu_gp_restore 27,$a0
	fpu_gp_restore 28,$a0
	fpu_gp_restore 29,$a0
	fpu_gp_restore 30,$a0
	fpu_gp_restore 31,$a0
 
	fpu_ct_restore 1,$a0
	fpu_ct_restore 2,$a0
	fpu_ct_restore 3,$a0
	fpu_ct_restore 4,$a0
	fpu_ct_restore 5,$a0
	fpu_ct_restore 6,$a0
	fpu_ct_restore 7,$a0
	fpu_ct_restore 8,$a0
	fpu_ct_restore 9,$a0
	fpu_ct_restore 10,$a0
	fpu_ct_restore 11,$a0
	fpu_ct_restore 12,$a0
	fpu_ct_restore 13,$a0
	fpu_ct_restore 14,$a0
	fpu_ct_restore 15,$a0
	fpu_ct_restore 16,$a0
	fpu_ct_restore 17,$a0
	fpu_ct_restore 18,$a0
	fpu_ct_restore 19,$a0
	fpu_ct_restore 20,$a0
	fpu_ct_restore 21,$a0
	fpu_ct_restore 22,$a0
	fpu_ct_restore 23,$a0
	fpu_ct_restore 24,$a0
	fpu_ct_restore 25,$a0
	fpu_ct_restore 26,$a0
	fpu_ct_restore 27,$a0
	fpu_ct_restore 28,$a0
	fpu_ct_restore 29,$a0
	fpu_ct_restore 30,$a0
	fpu_ct_restore 31,$a0
#endif	
	j $ra
	nop
 

Rev 3913	Rev 4038
1	#	1	#
2	# Copyright (c) 2003-2004 Jakub Jermar	2	# Copyright (c) 2003-2004 Jakub Jermar
3	# All rights reserved.	3	# All rights reserved.
4	#	4	#
5	# Redistribution and use in source and binary forms, with or without	5	# Redistribution and use in source and binary forms, with or without
6	# modification, are permitted provided that the following conditions	6	# modification, are permitted provided that the following conditions
7	# are met:	7	# are met:
8	#	8	#
9	# - Redistributions of source code must retain the above copyright	9	# - Redistributions of source code must retain the above copyright
10	# notice, this list of conditions and the following disclaimer.	10	# notice, this list of conditions and the following disclaimer.
11	# - Redistributions in binary form must reproduce the above copyright	11	# - Redistributions in binary form must reproduce the above copyright
12	# notice, this list of conditions and the following disclaimer in the	12	# notice, this list of conditions and the following disclaimer in the
13	# documentation and/or other materials provided with the distribution.	13	# documentation and/or other materials provided with the distribution.
14	# - The name of the author may not be used to endorse or promote products	14	# - The name of the author may not be used to endorse or promote products
15	# derived from this software without specific prior written permission.	15	# derived from this software without specific prior written permission.
16	#	16	#
17	# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	#	27	#
28		28
29	#include <arch/asm/regname.h>	29	#include <arch/asm/regname.h>
30		30
31	.text	31	.text
32		32
33	.macro cp0_read reg	33	.macro cp0_read reg
34	mfc0 $2,\reg	34	mfc0 $2,\reg
35	j $31	35	j $31
36	nop	36	nop
37	.endm	37	.endm
38		38
39	.macro cp0_write reg	39	.macro cp0_write reg
40	mtc0 $4,\reg	40	mtc0 $4,\reg
41	j $31	41	j $31
42	nop	42	nop
43	.endm	43	.endm
44		44
45	.set noat	45	.set noat
46	.set noreorder	46	.set noreorder
47	.set nomacro	47	.set nomacro
48		48
49	.global asm_delay_loop	49	.global asm_delay_loop
50	asm_delay_loop:	50	asm_delay_loop:
51	j $31	51	j $31
52	nop	52	nop
53		53
54	.global cpu_halt	54	.global cpu_halt
55	cpu_halt:	55	cpu_halt:
56	j cpu_halt	56	j cpu_halt
57	nop	57	nop
58		58
59		59
60	.global memsetb	60	.global memsetb
61	memsetb:	61	memsetb:
62	j _memsetb	62	j _memsetb
63	nop	63	nop
64		64
65		65
66	.global memcpy	66	.global memcpy
67	.global memcpy_from_uspace	67	.global memcpy_from_uspace
68	.global memcpy_to_uspace	68	.global memcpy_to_uspace
69	.global memcpy_from_uspace_failover_address	69	.global memcpy_from_uspace_failover_address
70	.global memcpy_to_uspace_failover_address	70	.global memcpy_to_uspace_failover_address
71	memcpy:	71	memcpy:
72	memcpy_from_uspace:	72	memcpy_from_uspace:
73	memcpy_to_uspace:	73	memcpy_to_uspace:
-		74	move $t2,$a0 # save dst
74	addiu $v0,$a1,3	75	addiu $v0,$a1,3
75	li $v1,-4 # 0xfffffffffffffffc	76	li $v1,-4 # 0xfffffffffffffffc
76	and $v0,$v0,$v1	77	and $v0,$v0,$v1
77	beq $a1,$v0,3f	78	beq $a1,$v0,3f
78	move $t0,$a0	79	move $t0,$a0
79	move $t2,$a0 # save dst	-
80		80
81	0:	81	0:
82	beq $a2,$zero,2f	82	beq $a2,$zero,2f
83	move $a3,$zero	83	move $a3,$zero
84		84
85	1:	85	1:
86	addu $v0,$a1,$a3	86	addu $v0,$a1,$a3
87	lbu $a0,0($v0)	87	lbu $a0,0($v0)
88	addu $v1,$t0,$a3	88	addu $v1,$t0,$a3
89	addiu $a3,$a3,1	89	addiu $a3,$a3,1
90	bne $a3,$a2,1b	90	bne $a3,$a2,1b
91	sb $a0,0($v1)	91	sb $a0,0($v1)
92		92
93	2:	93	2:
94	jr $ra	94	jr $ra
95	move $v0,$t2	95	move $v0,$t2
96		96
97	3:	97	3:
98	addiu $v0,$a0,3	98	addiu $v0,$a0,3
99	and $v0,$v0,$v1	99	and $v0,$v0,$v1
100	bne $a0,$v0,0b	100	bne $a0,$v0,0b
101	srl $t1,$a2,2	101	srl $t1,$a2,2
102		102
103	beq $t1,$zero,5f	103	beq $t1,$zero,5f
104	move $a3,$zero	104	move $a3,$zero
105		105
106	move $a3,$zero	106	move $a3,$zero
107	move $a0,$zero	107	move $a0,$zero
108	4:	108	4:
109	addu $v0,$a1,$a0	109	addu $v0,$a1,$a0
110	lw $v1,0($v0)	110	lw $v1,0($v0)
111	addiu $a3,$a3,1	111	addiu $a3,$a3,1
112	addu $v0,$t0,$a0	112	addu $v0,$t0,$a0
113	sw $v1,0($v0)	113	sw $v1,0($v0)
114	bne $a3,$t1,4b	114	bne $a3,$t1,4b
115	addiu $a0,$a0,4	115	addiu $a0,$a0,4
116		116
117	5:	117	5:
118	andi $a2,$a2,0x3	118	andi $a2,$a2,0x3
119	beq $a2,$zero,2b	119	beq $a2,$zero,2b
120	nop	120	nop
121		121
122	sll $v0,$a3,2	122	sll $v0,$a3,2
123	addu $t1,$v0,$t0	123	addu $t1,$v0,$t0
124	move $a3,$zero	124	move $a3,$zero
125	addu $t0,$v0,$a1	125	addu $t0,$v0,$a1
126	6:	126	6:
127	addu $v0,$t0,$a3	127	addu $v0,$t0,$a3
128	lbu $a0,0($v0)	128	lbu $a0,0($v0)
129	addu $v1,$t1,$a3	129	addu $v1,$t1,$a3
130	addiu $a3,$a3,1	130	addiu $a3,$a3,1
131	bne $a3,$a2,6b	131	bne $a3,$a2,6b
132	sb $a0,0($v1)	132	sb $a0,0($v1)
133		133
134	jr $ra	134	jr $ra
135	move $v0,$t2	135	move $v0,$t2
136		136
137	memcpy_from_uspace_failover_address:	137	memcpy_from_uspace_failover_address:
138	memcpy_to_uspace_failover_address:	138	memcpy_to_uspace_failover_address:
139	jr $ra	139	jr $ra
140	move $v0, $zero	140	move $v0, $zero
141		141
142		142
143		143
144	.macro fpu_gp_save reg ctx	144	.macro fpu_gp_save reg ctx
145	mfc1 $t0,$\reg	145	mfc1 $t0,$\reg
146	sw $t0, \reg*4(\ctx)	146	sw $t0, \reg*4(\ctx)
147	.endm	147	.endm
148		148
149	.macro fpu_gp_restore reg ctx	149	.macro fpu_gp_restore reg ctx
150	lw $t0, \reg*4(\ctx)	150	lw $t0, \reg*4(\ctx)
151	mtc1 $t0,$\reg	151	mtc1 $t0,$\reg
152	.endm	152	.endm
153		153
154	.macro fpu_ct_save reg ctx	154	.macro fpu_ct_save reg ctx
155	cfc1 $t0,$1	155	cfc1 $t0,$1
156	sw $t0, (\reg+32)*4(\ctx)	156	sw $t0, (\reg+32)*4(\ctx)
157	.endm	157	.endm
158		158
159	.macro fpu_ct_restore reg ctx	159	.macro fpu_ct_restore reg ctx
160	lw $t0, (\reg+32)*4(\ctx)	160	lw $t0, (\reg+32)*4(\ctx)
161	ctc1 $t0,$\reg	161	ctc1 $t0,$\reg
162	.endm	162	.endm
163		163
164		164
165	.global fpu_context_save	165	.global fpu_context_save
166	fpu_context_save:	166	fpu_context_save:
167	#ifdef CONFIG_FPU	167	#ifdef CONFIG_FPU
168	fpu_gp_save 0,$a0	168	fpu_gp_save 0,$a0
169	fpu_gp_save 1,$a0	169	fpu_gp_save 1,$a0
170	fpu_gp_save 2,$a0	170	fpu_gp_save 2,$a0
171	fpu_gp_save 3,$a0	171	fpu_gp_save 3,$a0
172	fpu_gp_save 4,$a0	172	fpu_gp_save 4,$a0
173	fpu_gp_save 5,$a0	173	fpu_gp_save 5,$a0
174	fpu_gp_save 6,$a0	174	fpu_gp_save 6,$a0
175	fpu_gp_save 7,$a0	175	fpu_gp_save 7,$a0
176	fpu_gp_save 8,$a0	176	fpu_gp_save 8,$a0
177	fpu_gp_save 9,$a0	177	fpu_gp_save 9,$a0
178	fpu_gp_save 10,$a0	178	fpu_gp_save 10,$a0
179	fpu_gp_save 11,$a0	179	fpu_gp_save 11,$a0
180	fpu_gp_save 12,$a0	180	fpu_gp_save 12,$a0
181	fpu_gp_save 13,$a0	181	fpu_gp_save 13,$a0
182	fpu_gp_save 14,$a0	182	fpu_gp_save 14,$a0
183	fpu_gp_save 15,$a0	183	fpu_gp_save 15,$a0
184	fpu_gp_save 16,$a0	184	fpu_gp_save 16,$a0
185	fpu_gp_save 17,$a0	185	fpu_gp_save 17,$a0
186	fpu_gp_save 18,$a0	186	fpu_gp_save 18,$a0
187	fpu_gp_save 19,$a0	187	fpu_gp_save 19,$a0
188	fpu_gp_save 20,$a0	188	fpu_gp_save 20,$a0
189	fpu_gp_save 21,$a0	189	fpu_gp_save 21,$a0
190	fpu_gp_save 22,$a0	190	fpu_gp_save 22,$a0
191	fpu_gp_save 23,$a0	191	fpu_gp_save 23,$a0
192	fpu_gp_save 24,$a0	192	fpu_gp_save 24,$a0
193	fpu_gp_save 25,$a0	193	fpu_gp_save 25,$a0
194	fpu_gp_save 26,$a0	194	fpu_gp_save 26,$a0
195	fpu_gp_save 27,$a0	195	fpu_gp_save 27,$a0
196	fpu_gp_save 28,$a0	196	fpu_gp_save 28,$a0
197	fpu_gp_save 29,$a0	197	fpu_gp_save 29,$a0
198	fpu_gp_save 30,$a0	198	fpu_gp_save 30,$a0
199	fpu_gp_save 31,$a0	199	fpu_gp_save 31,$a0
200		200
201	fpu_ct_save 1,$a0	201	fpu_ct_save 1,$a0
202	fpu_ct_save 2,$a0	202	fpu_ct_save 2,$a0
203	fpu_ct_save 3,$a0	203	fpu_ct_save 3,$a0
204	fpu_ct_save 4,$a0	204	fpu_ct_save 4,$a0
205	fpu_ct_save 5,$a0	205	fpu_ct_save 5,$a0
206	fpu_ct_save 6,$a0	206	fpu_ct_save 6,$a0
207	fpu_ct_save 7,$a0	207	fpu_ct_save 7,$a0
208	fpu_ct_save 8,$a0	208	fpu_ct_save 8,$a0
209	fpu_ct_save 9,$a0	209	fpu_ct_save 9,$a0
210	fpu_ct_save 10,$a0	210	fpu_ct_save 10,$a0
211	fpu_ct_save 11,$a0	211	fpu_ct_save 11,$a0
212	fpu_ct_save 12,$a0	212	fpu_ct_save 12,$a0
213	fpu_ct_save 13,$a0	213	fpu_ct_save 13,$a0
214	fpu_ct_save 14,$a0	214	fpu_ct_save 14,$a0
215	fpu_ct_save 15,$a0	215	fpu_ct_save 15,$a0
216	fpu_ct_save 16,$a0	216	fpu_ct_save 16,$a0
217	fpu_ct_save 17,$a0	217	fpu_ct_save 17,$a0
218	fpu_ct_save 18,$a0	218	fpu_ct_save 18,$a0
219	fpu_ct_save 19,$a0	219	fpu_ct_save 19,$a0
220	fpu_ct_save 20,$a0	220	fpu_ct_save 20,$a0
221	fpu_ct_save 21,$a0	221	fpu_ct_save 21,$a0
222	fpu_ct_save 22,$a0	222	fpu_ct_save 22,$a0
223	fpu_ct_save 23,$a0	223	fpu_ct_save 23,$a0
224	fpu_ct_save 24,$a0	224	fpu_ct_save 24,$a0
225	fpu_ct_save 25,$a0	225	fpu_ct_save 25,$a0
226	fpu_ct_save 26,$a0	226	fpu_ct_save 26,$a0
227	fpu_ct_save 27,$a0	227	fpu_ct_save 27,$a0
228	fpu_ct_save 28,$a0	228	fpu_ct_save 28,$a0
229	fpu_ct_save 29,$a0	229	fpu_ct_save 29,$a0
230	fpu_ct_save 30,$a0	230	fpu_ct_save 30,$a0
231	fpu_ct_save 31,$a0	231	fpu_ct_save 31,$a0
232	#endif	232	#endif
233	j $ra	233	j $ra
234	nop	234	nop
235		235
236	.global fpu_context_restore	236	.global fpu_context_restore
237	fpu_context_restore:	237	fpu_context_restore:
238	#ifdef CONFIG_FPU	238	#ifdef CONFIG_FPU
239	fpu_gp_restore 0,$a0	239	fpu_gp_restore 0,$a0
240	fpu_gp_restore 1,$a0	240	fpu_gp_restore 1,$a0
241	fpu_gp_restore 2,$a0	241	fpu_gp_restore 2,$a0
242	fpu_gp_restore 3,$a0	242	fpu_gp_restore 3,$a0
243	fpu_gp_restore 4,$a0	243	fpu_gp_restore 4,$a0
244	fpu_gp_restore 5,$a0	244	fpu_gp_restore 5,$a0
245	fpu_gp_restore 6,$a0	245	fpu_gp_restore 6,$a0
246	fpu_gp_restore 7,$a0	246	fpu_gp_restore 7,$a0
247	fpu_gp_restore 8,$a0	247	fpu_gp_restore 8,$a0
248	fpu_gp_restore 9,$a0	248	fpu_gp_restore 9,$a0
249	fpu_gp_restore 10,$a0	249	fpu_gp_restore 10,$a0
250	fpu_gp_restore 11,$a0	250	fpu_gp_restore 11,$a0
251	fpu_gp_restore 12,$a0	251	fpu_gp_restore 12,$a0
252	fpu_gp_restore 13,$a0	252	fpu_gp_restore 13,$a0
253	fpu_gp_restore 14,$a0	253	fpu_gp_restore 14,$a0
254	fpu_gp_restore 15,$a0	254	fpu_gp_restore 15,$a0
255	fpu_gp_restore 16,$a0	255	fpu_gp_restore 16,$a0
256	fpu_gp_restore 17,$a0	256	fpu_gp_restore 17,$a0
257	fpu_gp_restore 18,$a0	257	fpu_gp_restore 18,$a0
258	fpu_gp_restore 19,$a0	258	fpu_gp_restore 19,$a0
259	fpu_gp_restore 20,$a0	259	fpu_gp_restore 20,$a0
260	fpu_gp_restore 21,$a0	260	fpu_gp_restore 21,$a0
261	fpu_gp_restore 22,$a0	261	fpu_gp_restore 22,$a0
262	fpu_gp_restore 23,$a0	262	fpu_gp_restore 23,$a0
263	fpu_gp_restore 24,$a0	263	fpu_gp_restore 24,$a0
264	fpu_gp_restore 25,$a0	264	fpu_gp_restore 25,$a0
265	fpu_gp_restore 26,$a0	265	fpu_gp_restore 26,$a0
266	fpu_gp_restore 27,$a0	266	fpu_gp_restore 27,$a0
267	fpu_gp_restore 28,$a0	267	fpu_gp_restore 28,$a0
268	fpu_gp_restore 29,$a0	268	fpu_gp_restore 29,$a0
269	fpu_gp_restore 30,$a0	269	fpu_gp_restore 30,$a0
270	fpu_gp_restore 31,$a0	270	fpu_gp_restore 31,$a0
271		271
272	fpu_ct_restore 1,$a0	272	fpu_ct_restore 1,$a0
273	fpu_ct_restore 2,$a0	273	fpu_ct_restore 2,$a0
274	fpu_ct_restore 3,$a0	274	fpu_ct_restore 3,$a0
275	fpu_ct_restore 4,$a0	275	fpu_ct_restore 4,$a0
276	fpu_ct_restore 5,$a0	276	fpu_ct_restore 5,$a0
277	fpu_ct_restore 6,$a0	277	fpu_ct_restore 6,$a0
278	fpu_ct_restore 7,$a0	278	fpu_ct_restore 7,$a0
279	fpu_ct_restore 8,$a0	279	fpu_ct_restore 8,$a0
280	fpu_ct_restore 9,$a0	280	fpu_ct_restore 9,$a0
281	fpu_ct_restore 10,$a0	281	fpu_ct_restore 10,$a0
282	fpu_ct_restore 11,$a0	282	fpu_ct_restore 11,$a0
283	fpu_ct_restore 12,$a0	283	fpu_ct_restore 12,$a0
284	fpu_ct_restore 13,$a0	284	fpu_ct_restore 13,$a0
285	fpu_ct_restore 14,$a0	285	fpu_ct_restore 14,$a0
286	fpu_ct_restore 15,$a0	286	fpu_ct_restore 15,$a0
287	fpu_ct_restore 16,$a0	287	fpu_ct_restore 16,$a0
288	fpu_ct_restore 17,$a0	288	fpu_ct_restore 17,$a0
289	fpu_ct_restore 18,$a0	289	fpu_ct_restore 18,$a0
290	fpu_ct_restore 19,$a0	290	fpu_ct_restore 19,$a0
291	fpu_ct_restore 20,$a0	291	fpu_ct_restore 20,$a0
292	fpu_ct_restore 21,$a0	292	fpu_ct_restore 21,$a0
293	fpu_ct_restore 22,$a0	293	fpu_ct_restore 22,$a0
294	fpu_ct_restore 23,$a0	294	fpu_ct_restore 23,$a0
295	fpu_ct_restore 24,$a0	295	fpu_ct_restore 24,$a0
296	fpu_ct_restore 25,$a0	296	fpu_ct_restore 25,$a0
297	fpu_ct_restore 26,$a0	297	fpu_ct_restore 26,$a0
298	fpu_ct_restore 27,$a0	298	fpu_ct_restore 27,$a0
299	fpu_ct_restore 28,$a0	299	fpu_ct_restore 28,$a0
300	fpu_ct_restore 29,$a0	300	fpu_ct_restore 29,$a0
301	fpu_ct_restore 30,$a0	301	fpu_ct_restore 30,$a0
302	fpu_ct_restore 31,$a0	302	fpu_ct_restore 31,$a0
303	#endif	303	#endif
304	j $ra	304	j $ra
305	nop	305	nop
306		306

Subversion Repositories HelenOS

(root)/trunk/kernel/arch/mips32/src/asm.S – Rev 3913 → 4038