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1 | # |
1 | # |
2 | # Copyright (C) 2005 Jakub Vana |
2 | # Copyright (C) 2005 Jakub Vana |
3 | # All rights reserved. |
3 | # All rights reserved. |
4 | # |
4 | # |
5 | # Redistribution and use in source and binary forms, with or without |
5 | # Redistribution and use in source and binary forms, with or without |
6 | # modification, are permitted provided that the following conditions |
6 | # modification, are permitted provided that the following conditions |
7 | # are met: |
7 | # are met: |
8 | # |
8 | # |
9 | # - Redistributions of source code must retain the above copyright |
9 | # - Redistributions of source code must retain the above copyright |
10 | # notice, this list of conditions and the following disclaimer. |
10 | # notice, this list of conditions and the following disclaimer. |
11 | # - Redistributions in binary form must reproduce the above copyright |
11 | # - Redistributions in binary form must reproduce the above copyright |
12 | # notice, this list of conditions and the following disclaimer in the |
12 | # notice, this list of conditions and the following disclaimer in the |
13 | # documentation and/or other materials provided with the distribution. |
13 | # documentation and/or other materials provided with the distribution. |
14 | # - The name of the author may not be used to endorse or promote products |
14 | # - The name of the author may not be used to endorse or promote products |
15 | # derived from this software without specific prior written permission. |
15 | # derived from this software without specific prior written permission. |
16 | # |
16 | # |
17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | # |
27 | # |
28 | 28 | ||
29 | 29 | ||
30 | /** Heavyweight interrupt handler |
30 | /** Heavyweight interrupt handler |
31 | * |
31 | * |
32 | * This macro roughly follows steps from 1 to 19 described in |
32 | * This macro roughly follows steps from 1 to 19 described in |
33 | * Intel Itanium Architecture Software Developer's Manual, Chapter 3.4.2. |
33 | * Intel Itanium Architecture Software Developer's Manual, Chapter 3.4.2. |
34 | * |
34 | * |
35 | * HEAVYWEIGHT_HANDLER macro must cram into 16 bundles (48 instructions). |
35 | * HEAVYWEIGHT_HANDLER macro must cram into 16 bundles (48 instructions). |
36 | * This goal is achieved by using procedure calls after RSE becomes operational. |
36 | * This goal is achieved by using procedure calls after RSE becomes operational. |
37 | * |
37 | * |
38 | * Some steps are skipped (enabling and disabling interrupts). |
38 | * Some steps are skipped (enabling and disabling interrupts). |
39 | * Some steps are not fully supported yet (e.g. interruptions |
39 | * Some steps are not fully supported yet (e.g. interruptions |
40 | * from userspace and floating-point context). |
40 | * from userspace and floating-point context). |
41 | */ |
41 | */ |
42 | .macro HEAVYWEIGHT_HANDLER offs handler |
42 | .macro HEAVYWEIGHT_HANDLER offs handler |
43 | .org IVT + \offs |
43 | .org IVT + \offs |
44 | 44 | ||
45 | /* 1. copy interrupt registers into bank 0 */ |
45 | /* 1. copy interrupt registers into bank 0 */ |
46 | mov r24 = cr.iip |
46 | mov r24 = cr.iip |
47 | mov r25 = cr.ipsr |
47 | mov r25 = cr.ipsr |
48 | mov r26 = cr.iipa |
48 | mov r26 = cr.iipa |
49 | mov r27 = cr.isr |
49 | mov r27 = cr.isr |
50 | mov r28 = cr.ifa |
50 | mov r28 = cr.ifa |
51 | 51 | ||
52 | /* 2. preserve predicate register into bank 0 */ |
52 | /* 2. preserve predicate register into bank 0 */ |
53 | mov r29 = pr ;; |
53 | mov r29 = pr ;; |
54 | 54 | ||
55 | /* 3. switch to kernel memory stack */ |
55 | /* 3. switch to kernel memory stack */ |
56 | /* TODO: support interruptions from userspace */ |
56 | /* TODO: support interruptions from userspace */ |
57 | /* assume kernel stack */ |
57 | /* assume kernel stack */ |
58 | 58 | ||
59 | /* 4. save registers in bank 0 into memory stack */ |
59 | /* 4. save registers in bank 0 into memory stack */ |
- | 60 | add r12 = -8, r12 ;; |
|
- | 61 | ||
60 | st8 [r12] = r29, -8 ;; /* save predicate registers */ |
62 | st8 [r12] = r29, -8 ;; /* save predicate registers */ |
61 | 63 | ||
62 | st8 [r12] = r24, -8 ;; /* save cr.iip */ |
64 | st8 [r12] = r24, -8 ;; /* save cr.iip */ |
63 | st8 [r12] = r25, -8 ;; /* save cr.ipsr */ |
65 | st8 [r12] = r25, -8 ;; /* save cr.ipsr */ |
64 | st8 [r12] = r26, -8 ;; /* save cr.iipa */ |
66 | st8 [r12] = r26, -8 ;; /* save cr.iipa */ |
65 | st8 [r12] = r27, -8 ;; /* save cr.isr */ |
67 | st8 [r12] = r27, -8 ;; /* save cr.isr */ |
66 | st8 [r12] = r28, -8 ;; /* save cr.ifa */ |
68 | st8 [r12] = r28, -8 ;; /* save cr.ifa */ |
67 | 69 | ||
68 | /* 5. RSE switch from interrupted context */ |
70 | /* 5. RSE switch from interrupted context */ |
69 | .auto |
71 | .auto |
70 | mov r24 = ar.rsc |
72 | mov r24 = ar.rsc |
71 | mov r25 = ar.pfs |
73 | mov r25 = ar.pfs |
72 | cover |
74 | cover |
73 | mov r26 = cr.ifs |
75 | mov r26 = cr.ifs |
74 | 76 | ||
75 | st8 [r12] = r24, -8 /* save ar.rsc */ |
77 | st8 [r12] = r24, -8 /* save ar.rsc */ |
76 | st8 [r12] = r25, -8 /* save ar.pfs */ |
78 | st8 [r12] = r25, -8 /* save ar.pfs */ |
77 | st8 [r12] = r26, -8 /* save ar.ifs */ |
79 | st8 [r12] = r26, -8 /* save ar.ifs */ |
78 | 80 | ||
79 | and r30 = ~3, r24 |
81 | and r30 = ~3, r24 |
80 | mov ar.rsc = r30 /* place RSE in enforced lazy mode */ |
82 | mov ar.rsc = r30 /* place RSE in enforced lazy mode */ |
81 | 83 | ||
82 | mov r27 = ar.rnat |
84 | mov r27 = ar.rnat |
83 | mov r28 = ar.bspstore |
85 | mov r28 = ar.bspstore |
84 | 86 | ||
85 | /* assume kernel backing store */ |
87 | /* assume kernel backing store */ |
86 | mov ar.bspstore = r28 |
88 | mov ar.bspstore = r28 |
87 | 89 | ||
88 | mov r29 = ar.bsp |
90 | mov r29 = ar.bsp |
89 | 91 | ||
90 | st8 [r12] = r27, -8 /* save ar.rnat */ |
92 | st8 [r12] = r27, -8 /* save ar.rnat */ |
91 | st8 [r12] = r28, -8 /* save ar.bspstore */ |
93 | st8 [r12] = r28, -8 /* save ar.bspstore */ |
92 | st8 [r12] = r29, -8 /* save ar.bsp */ |
94 | st8 [r12] = r29, -8 /* save ar.bsp */ |
93 | 95 | ||
94 | mov ar.rsc = r24 /* restore RSE's setting */ |
96 | mov ar.rsc = r24 /* restore RSE's setting */ |
95 | .explicit |
97 | .explicit |
96 | 98 | ||
97 | /* the rest of the save-handler can be kept outside IVT */ |
99 | /* the rest of the save-handler can be kept outside IVT */ |
98 | 100 | ||
99 | movl r24 = \handler |
101 | movl r24 = \handler |
100 | mov r25 = b0 |
102 | mov r25 = b0 |
101 | br.call.sptk.many rp = heavyweight_handler_inner |
103 | br.call.sptk.many rp = heavyweight_handler_inner |
102 | 0: mov b0 = r25 |
104 | 0: mov b0 = r25 |
103 | 105 | ||
104 | br heavyweight_handler_finalize |
106 | br heavyweight_handler_finalize |
105 | .endm |
107 | .endm |
106 | 108 | ||
107 | .global heavyweight_handler_inner |
109 | .global heavyweight_handler_inner |
108 | heavyweight_handler_inner: |
110 | heavyweight_handler_inner: |
109 | /* |
111 | /* |
110 | * From this point, the rest of the interrupted context |
112 | * From this point, the rest of the interrupted context |
111 | * will be preserved in stacked registers and backing store. |
113 | * will be preserved in stacked registers and backing store. |
112 | */ |
114 | */ |
113 | alloc loc0 = ar.pfs, 0, 46, 0, 0 ;; |
115 | alloc loc0 = ar.pfs, 0, 46, 0, 0 ;; |
114 | 116 | ||
115 | /* copy handler address (r24 from bank 0 will be invisible soon) */ |
117 | /* copy handler address (r24 from bank 0 will be invisible soon) */ |
116 | mov loc1 = r24 |
118 | mov loc1 = r24 |
117 | 119 | ||
118 | /* 6. switch to bank 1 and reenable PSR.ic */ |
120 | /* 6. switch to bank 1 and reenable PSR.ic */ |
119 | ssm 0x2000 |
121 | ssm 0x2000 |
120 | bsw.1 ;; |
122 | bsw.1 ;; |
121 | srlz.d |
123 | srlz.d |
122 | 124 | ||
123 | /* 7. preserve branch and application registers */ |
125 | /* 7. preserve branch and application registers */ |
124 | mov loc2 = ar.unat |
126 | mov loc2 = ar.unat |
125 | mov loc3 = ar.lc |
127 | mov loc3 = ar.lc |
126 | mov loc4 = ar.ec |
128 | mov loc4 = ar.ec |
127 | mov loc5 = ar.ccv |
129 | mov loc5 = ar.ccv |
128 | mov loc6 = ar.csd |
130 | mov loc6 = ar.csd |
129 | mov loc7 = ar.ssd |
131 | mov loc7 = ar.ssd |
130 | 132 | ||
131 | mov loc8 = b0 |
133 | mov loc8 = b0 |
132 | mov loc9 = b1 |
134 | mov loc9 = b1 |
133 | mov loc10 = b2 |
135 | mov loc10 = b2 |
134 | mov loc11 = b3 |
136 | mov loc11 = b3 |
135 | mov loc12 = b4 |
137 | mov loc12 = b4 |
136 | mov loc13 = b5 |
138 | mov loc13 = b5 |
137 | mov loc14 = b6 |
139 | mov loc14 = b6 |
138 | mov loc15 = b7 |
140 | mov loc15 = b7 |
139 | 141 | ||
140 | /* 8. preserve general and floating-point registers */ |
142 | /* 8. preserve general and floating-point registers */ |
141 | /* TODO: save floating-point context */ |
143 | /* TODO: save floating-point context */ |
142 | mov loc16 = r1 |
144 | mov loc16 = r1 |
143 | mov loc17 = r2 |
145 | mov loc17 = r2 |
144 | mov loc18 = r3 |
146 | mov loc18 = r3 |
145 | mov loc19 = r4 |
147 | mov loc19 = r4 |
146 | mov loc20 = r5 |
148 | mov loc20 = r5 |
147 | mov loc21 = r6 |
149 | mov loc21 = r6 |
148 | mov loc22 = r7 |
150 | mov loc22 = r7 |
149 | mov loc23 = r8 |
151 | mov loc23 = r8 |
150 | mov loc24 = r9 |
152 | mov loc24 = r9 |
151 | mov loc25 = r10 |
153 | mov loc25 = r10 |
152 | mov loc26 = r11 |
154 | mov loc26 = r11 |
153 | /* skip r12 (stack pointer) */ |
155 | /* skip r12 (stack pointer) */ |
154 | mov loc27 = r13 |
156 | mov loc27 = r13 |
155 | mov loc28 = r14 |
157 | mov loc28 = r14 |
156 | mov loc29 = r15 |
158 | mov loc29 = r15 |
157 | mov loc30 = r16 |
159 | mov loc30 = r16 |
158 | mov loc31 = r17 |
160 | mov loc31 = r17 |
159 | mov loc32 = r18 |
161 | mov loc32 = r18 |
160 | mov loc33 = r19 |
162 | mov loc33 = r19 |
161 | mov loc34 = r20 |
163 | mov loc34 = r20 |
162 | mov loc35 = r21 |
164 | mov loc35 = r21 |
163 | mov loc36 = r22 |
165 | mov loc36 = r22 |
164 | mov loc37 = r23 |
166 | mov loc37 = r23 |
165 | mov loc38 = r24 |
167 | mov loc38 = r24 |
166 | mov loc39 = r25 |
168 | mov loc39 = r25 |
167 | mov loc40 = r26 |
169 | mov loc40 = r26 |
168 | mov loc41 = r27 |
170 | mov loc41 = r27 |
169 | mov loc42 = r28 |
171 | mov loc42 = r28 |
170 | mov loc43 = r29 |
172 | mov loc43 = r29 |
171 | mov loc44 = r30 |
173 | mov loc44 = r30 |
172 | mov loc45 = r31 |
174 | mov loc45 = r31 |
173 | 175 | ||
174 | /* 9. skipped (will not enable interrupts) */ |
176 | /* 9. skipped (will not enable interrupts) */ |
175 | 177 | ||
176 | /* 10. call handler */ |
178 | /* 10. call handler */ |
177 | mov b1 = loc1 |
179 | mov b1 = loc1 |
178 | br.call.sptk.many b0 = b1 |
180 | br.call.sptk.many b0 = b1 |
179 | 181 | ||
180 | /* 11. return from handler */ |
182 | /* 11. return from handler */ |
181 | 0: |
183 | 0: |
182 | 184 | ||
183 | /* 12. skipped (will not disable interrupts) */ |
185 | /* 12. skipped (will not disable interrupts) */ |
184 | 186 | ||
185 | /* 13. restore general and floating-point registers */ |
187 | /* 13. restore general and floating-point registers */ |
186 | /* TODO: restore floating-point context */ |
188 | /* TODO: restore floating-point context */ |
187 | mov r1 = loc16 |
189 | mov r1 = loc16 |
188 | mov r2 = loc17 |
190 | mov r2 = loc17 |
189 | mov r3 = loc18 |
191 | mov r3 = loc18 |
190 | mov r4 = loc19 |
192 | mov r4 = loc19 |
191 | mov r5 = loc20 |
193 | mov r5 = loc20 |
192 | mov r6 = loc21 |
194 | mov r6 = loc21 |
193 | mov r7 = loc22 |
195 | mov r7 = loc22 |
194 | mov r8 = loc23 |
196 | mov r8 = loc23 |
195 | mov r9 = loc24 |
197 | mov r9 = loc24 |
196 | mov r10 = loc25 |
198 | mov r10 = loc25 |
197 | mov r11 = loc26 |
199 | mov r11 = loc26 |
198 | /* skip r12 (stack pointer) */ |
200 | /* skip r12 (stack pointer) */ |
199 | mov r13 = loc27 |
201 | mov r13 = loc27 |
200 | mov r14 = loc28 |
202 | mov r14 = loc28 |
201 | mov r15 = loc29 |
203 | mov r15 = loc29 |
202 | mov r16 = loc30 |
204 | mov r16 = loc30 |
203 | mov r17 = loc31 |
205 | mov r17 = loc31 |
204 | mov r18 = loc32 |
206 | mov r18 = loc32 |
205 | mov r19 = loc33 |
207 | mov r19 = loc33 |
206 | mov r20 = loc34 |
208 | mov r20 = loc34 |
207 | mov r21 = loc35 |
209 | mov r21 = loc35 |
208 | mov r22 = loc36 |
210 | mov r22 = loc36 |
209 | mov r23 = loc37 |
211 | mov r23 = loc37 |
210 | mov r24 = loc38 |
212 | mov r24 = loc38 |
211 | mov r25 = loc39 |
213 | mov r25 = loc39 |
212 | mov r26 = loc40 |
214 | mov r26 = loc40 |
213 | mov r27 = loc41 |
215 | mov r27 = loc41 |
214 | mov r28 = loc42 |
216 | mov r28 = loc42 |
215 | mov r29 = loc43 |
217 | mov r29 = loc43 |
216 | mov r30 = loc44 |
218 | mov r30 = loc44 |
217 | mov r31 = loc45 |
219 | mov r31 = loc45 |
218 | 220 | ||
219 | /* 14. restore branch and application registers */ |
221 | /* 14. restore branch and application registers */ |
220 | mov ar.unat = loc2 |
222 | mov ar.unat = loc2 |
221 | mov ar.lc = loc3 |
223 | mov ar.lc = loc3 |
222 | mov ar.ec = loc4 |
224 | mov ar.ec = loc4 |
223 | mov ar.ccv = loc5 |
225 | mov ar.ccv = loc5 |
224 | mov ar.csd = loc6 |
226 | mov ar.csd = loc6 |
225 | mov ar.ssd = loc7 |
227 | mov ar.ssd = loc7 |
226 | 228 | ||
227 | mov b0 = loc8 |
229 | mov b0 = loc8 |
228 | mov b1 = loc9 |
230 | mov b1 = loc9 |
229 | mov b2 = loc10 |
231 | mov b2 = loc10 |
230 | mov b3 = loc11 |
232 | mov b3 = loc11 |
231 | mov b4 = loc12 |
233 | mov b4 = loc12 |
232 | mov b5 = loc13 |
234 | mov b5 = loc13 |
233 | mov b6 = loc14 |
235 | mov b6 = loc14 |
234 | mov b7 = loc15 |
236 | mov b7 = loc15 |
235 | 237 | ||
236 | /* 15. disable PSR.ic and switch to bank 0 */ |
238 | /* 15. disable PSR.ic and switch to bank 0 */ |
237 | rsm 0x2000 |
239 | rsm 0x2000 |
238 | bsw.0 ;; |
240 | bsw.0 ;; |
239 | srlz.d |
241 | srlz.d |
240 | 242 | ||
241 | mov ar.pfs = loc0 |
243 | mov ar.pfs = loc0 |
242 | br.ret.sptk.many rp |
244 | br.ret.sptk.many rp |
243 | 245 | ||
244 | .global heavyweight_handler_finalize |
246 | .global heavyweight_handler_finalize |
245 | heavyweight_handler_finalize: |
247 | heavyweight_handler_finalize: |
246 | /* 16. RSE switch to interrupted context */ |
248 | /* 16. RSE switch to interrupted context */ |
247 | 249 | ||
248 | /* 17. restore interruption state from memory stack */ |
250 | /* 17. restore interruption state from memory stack */ |
249 | 251 | ||
250 | /* 18. restore predicate registers from memory stack */ |
252 | /* 18. restore predicate registers from memory stack */ |
251 | 253 | ||
252 | /* 19. return from interruption */ |
254 | /* 19. return from interruption */ |
253 | rfi |
255 | rfi |
254 | 256 | ||
255 | 257 | ||
256 | 258 | ||
257 | 259 | ||
258 | dump_gregs: |
260 | dump_gregs: |
259 | mov r16 = REG_DUMP;; |
261 | mov r16 = REG_DUMP;; |
260 | st8 [r16] = r0;; |
262 | st8 [r16] = r0;; |
261 | add r16 = 8,r16 ;; |
263 | add r16 = 8,r16 ;; |
262 | st8 [r16] = r1;; |
264 | st8 [r16] = r1;; |
263 | add r16 = 8,r16 ;; |
265 | add r16 = 8,r16 ;; |
264 | st8 [r16] = r2;; |
266 | st8 [r16] = r2;; |
265 | add r16 = 8,r16 ;; |
267 | add r16 = 8,r16 ;; |
266 | st8 [r16] = r3;; |
268 | st8 [r16] = r3;; |
267 | add r16 = 8,r16 ;; |
269 | add r16 = 8,r16 ;; |
268 | st8 [r16] = r4;; |
270 | st8 [r16] = r4;; |
269 | add r16 = 8,r16 ;; |
271 | add r16 = 8,r16 ;; |
270 | st8 [r16] = r5;; |
272 | st8 [r16] = r5;; |
271 | add r16 = 8,r16 ;; |
273 | add r16 = 8,r16 ;; |
272 | st8 [r16] = r6;; |
274 | st8 [r16] = r6;; |
273 | add r16 = 8,r16 ;; |
275 | add r16 = 8,r16 ;; |
274 | st8 [r16] = r7;; |
276 | st8 [r16] = r7;; |
275 | add r16 = 8,r16 ;; |
277 | add r16 = 8,r16 ;; |
276 | st8 [r16] = r8;; |
278 | st8 [r16] = r8;; |
277 | add r16 = 8,r16 ;; |
279 | add r16 = 8,r16 ;; |
278 | st8 [r16] = r9;; |
280 | st8 [r16] = r9;; |
279 | add r16 = 8,r16 ;; |
281 | add r16 = 8,r16 ;; |
280 | st8 [r16] = r10;; |
282 | st8 [r16] = r10;; |
281 | add r16 = 8,r16 ;; |
283 | add r16 = 8,r16 ;; |
282 | st8 [r16] = r11;; |
284 | st8 [r16] = r11;; |
283 | add r16 = 8,r16 ;; |
285 | add r16 = 8,r16 ;; |
284 | st8 [r16] = r12;; |
286 | st8 [r16] = r12;; |
285 | add r16 = 8,r16 ;; |
287 | add r16 = 8,r16 ;; |
286 | st8 [r16] = r13;; |
288 | st8 [r16] = r13;; |
287 | add r16 = 8,r16 ;; |
289 | add r16 = 8,r16 ;; |
288 | st8 [r16] = r14;; |
290 | st8 [r16] = r14;; |
289 | add r16 = 8,r16 ;; |
291 | add r16 = 8,r16 ;; |
290 | st8 [r16] = r15;; |
292 | st8 [r16] = r15;; |
291 | add r16 = 8,r16 ;; |
293 | add r16 = 8,r16 ;; |
292 | 294 | ||
293 | bsw.1;; |
295 | bsw.1;; |
294 | mov r15 = r16;; |
296 | mov r15 = r16;; |
295 | bsw.0;; |
297 | bsw.0;; |
296 | st8 [r16] = r15;; |
298 | st8 [r16] = r15;; |
297 | add r16 = 8,r16 ;; |
299 | add r16 = 8,r16 ;; |
298 | bsw.1;; |
300 | bsw.1;; |
299 | mov r15 = r17;; |
301 | mov r15 = r17;; |
300 | bsw.0;; |
302 | bsw.0;; |
301 | st8 [r16] = r15;; |
303 | st8 [r16] = r15;; |
302 | add r16 = 8,r16 ;; |
304 | add r16 = 8,r16 ;; |
303 | bsw.1;; |
305 | bsw.1;; |
304 | mov r15 = r18;; |
306 | mov r15 = r18;; |
305 | bsw.0;; |
307 | bsw.0;; |
306 | st8 [r16] = r15;; |
308 | st8 [r16] = r15;; |
307 | add r16 = 8,r16 ;; |
309 | add r16 = 8,r16 ;; |
308 | bsw.1;; |
310 | bsw.1;; |
309 | mov r15 = r19;; |
311 | mov r15 = r19;; |
310 | bsw.0;; |
312 | bsw.0;; |
311 | st8 [r16] = r15;; |
313 | st8 [r16] = r15;; |
312 | add r16 = 8,r16 ;; |
314 | add r16 = 8,r16 ;; |
313 | bsw.1;; |
315 | bsw.1;; |
314 | mov r15 = r20;; |
316 | mov r15 = r20;; |
315 | bsw.0;; |
317 | bsw.0;; |
316 | st8 [r16] = r15;; |
318 | st8 [r16] = r15;; |
317 | add r16 = 8,r16 ;; |
319 | add r16 = 8,r16 ;; |
318 | bsw.1;; |
320 | bsw.1;; |
319 | mov r15 = r21;; |
321 | mov r15 = r21;; |
320 | bsw.0;; |
322 | bsw.0;; |
321 | st8 [r16] = r15;; |
323 | st8 [r16] = r15;; |
322 | add r16 = 8,r16 ;; |
324 | add r16 = 8,r16 ;; |
323 | bsw.1;; |
325 | bsw.1;; |
324 | mov r15 = r22;; |
326 | mov r15 = r22;; |
325 | bsw.0;; |
327 | bsw.0;; |
326 | st8 [r16] = r15;; |
328 | st8 [r16] = r15;; |
327 | add r16 = 8,r16 ;; |
329 | add r16 = 8,r16 ;; |
328 | bsw.1;; |
330 | bsw.1;; |
329 | mov r15 = r23;; |
331 | mov r15 = r23;; |
330 | bsw.0;; |
332 | bsw.0;; |
331 | st8 [r16] = r15;; |
333 | st8 [r16] = r15;; |
332 | add r16 = 8,r16 ;; |
334 | add r16 = 8,r16 ;; |
333 | bsw.1;; |
335 | bsw.1;; |
334 | mov r15 = r24;; |
336 | mov r15 = r24;; |
335 | bsw.0;; |
337 | bsw.0;; |
336 | st8 [r16] = r15;; |
338 | st8 [r16] = r15;; |
337 | add r16 = 8,r16 ;; |
339 | add r16 = 8,r16 ;; |
338 | bsw.1;; |
340 | bsw.1;; |
339 | mov r15 = r25;; |
341 | mov r15 = r25;; |
340 | bsw.0;; |
342 | bsw.0;; |
341 | st8 [r16] = r15;; |
343 | st8 [r16] = r15;; |
342 | add r16 = 8,r16 ;; |
344 | add r16 = 8,r16 ;; |
343 | bsw.1;; |
345 | bsw.1;; |
344 | mov r15 = r26;; |
346 | mov r15 = r26;; |
345 | bsw.0;; |
347 | bsw.0;; |
346 | st8 [r16] = r15;; |
348 | st8 [r16] = r15;; |
347 | add r16 = 8,r16 ;; |
349 | add r16 = 8,r16 ;; |
348 | bsw.1;; |
350 | bsw.1;; |
349 | mov r15 = r27;; |
351 | mov r15 = r27;; |
350 | bsw.0;; |
352 | bsw.0;; |
351 | st8 [r16] = r15;; |
353 | st8 [r16] = r15;; |
352 | add r16 = 8,r16 ;; |
354 | add r16 = 8,r16 ;; |
353 | bsw.1;; |
355 | bsw.1;; |
354 | mov r15 = r28;; |
356 | mov r15 = r28;; |
355 | bsw.0;; |
357 | bsw.0;; |
356 | st8 [r16] = r15;; |
358 | st8 [r16] = r15;; |
357 | add r16 = 8,r16 ;; |
359 | add r16 = 8,r16 ;; |
358 | bsw.1;; |
360 | bsw.1;; |
359 | mov r15 = r29;; |
361 | mov r15 = r29;; |
360 | bsw.0;; |
362 | bsw.0;; |
361 | st8 [r16] = r15;; |
363 | st8 [r16] = r15;; |
362 | add r16 = 8,r16 ;; |
364 | add r16 = 8,r16 ;; |
363 | bsw.1;; |
365 | bsw.1;; |
364 | mov r15 = r30;; |
366 | mov r15 = r30;; |
365 | bsw.0;; |
367 | bsw.0;; |
366 | st8 [r16] = r15;; |
368 | st8 [r16] = r15;; |
367 | add r16 = 8,r16 ;; |
369 | add r16 = 8,r16 ;; |
368 | bsw.1;; |
370 | bsw.1;; |
369 | mov r15 = r31;; |
371 | mov r15 = r31;; |
370 | bsw.0;; |
372 | bsw.0;; |
371 | st8 [r16] = r15;; |
373 | st8 [r16] = r15;; |
372 | add r16 = 8,r16 ;; |
374 | add r16 = 8,r16 ;; |
373 | 375 | ||
374 | 376 | ||
375 | st8 [r16] = r32;; |
377 | st8 [r16] = r32;; |
376 | add r16 = 8,r16 ;; |
378 | add r16 = 8,r16 ;; |
377 | st8 [r16] = r33;; |
379 | st8 [r16] = r33;; |
378 | add r16 = 8,r16 ;; |
380 | add r16 = 8,r16 ;; |
379 | st8 [r16] = r34;; |
381 | st8 [r16] = r34;; |
380 | add r16 = 8,r16 ;; |
382 | add r16 = 8,r16 ;; |
381 | st8 [r16] = r35;; |
383 | st8 [r16] = r35;; |
382 | add r16 = 8,r16 ;; |
384 | add r16 = 8,r16 ;; |
383 | st8 [r16] = r36;; |
385 | st8 [r16] = r36;; |
384 | add r16 = 8,r16 ;; |
386 | add r16 = 8,r16 ;; |
385 | st8 [r16] = r37;; |
387 | st8 [r16] = r37;; |
386 | add r16 = 8,r16 ;; |
388 | add r16 = 8,r16 ;; |
387 | st8 [r16] = r38;; |
389 | st8 [r16] = r38;; |
388 | add r16 = 8,r16 ;; |
390 | add r16 = 8,r16 ;; |
389 | st8 [r16] = r39;; |
391 | st8 [r16] = r39;; |
390 | add r16 = 8,r16 ;; |
392 | add r16 = 8,r16 ;; |
391 | st8 [r16] = r40;; |
393 | st8 [r16] = r40;; |
392 | add r16 = 8,r16 ;; |
394 | add r16 = 8,r16 ;; |
393 | st8 [r16] = r41;; |
395 | st8 [r16] = r41;; |
394 | add r16 = 8,r16 ;; |
396 | add r16 = 8,r16 ;; |
395 | st8 [r16] = r42;; |
397 | st8 [r16] = r42;; |
396 | add r16 = 8,r16 ;; |
398 | add r16 = 8,r16 ;; |
397 | st8 [r16] = r43;; |
399 | st8 [r16] = r43;; |
398 | add r16 = 8,r16 ;; |
400 | add r16 = 8,r16 ;; |
399 | st8 [r16] = r44;; |
401 | st8 [r16] = r44;; |
400 | add r16 = 8,r16 ;; |
402 | add r16 = 8,r16 ;; |
401 | st8 [r16] = r45;; |
403 | st8 [r16] = r45;; |
402 | add r16 = 8,r16 ;; |
404 | add r16 = 8,r16 ;; |
403 | st8 [r16] = r46;; |
405 | st8 [r16] = r46;; |
404 | add r16 = 8,r16 ;; |
406 | add r16 = 8,r16 ;; |
405 | st8 [r16] = r47;; |
407 | st8 [r16] = r47;; |
406 | add r16 = 8,r16 ;; |
408 | add r16 = 8,r16 ;; |
407 | st8 [r16] = r48;; |
409 | st8 [r16] = r48;; |
408 | add r16 = 8,r16 ;; |
410 | add r16 = 8,r16 ;; |
409 | st8 [r16] = r49;; |
411 | st8 [r16] = r49;; |
410 | add r16 = 8,r16 ;; |
412 | add r16 = 8,r16 ;; |
411 | st8 [r16] = r50;; |
413 | st8 [r16] = r50;; |
412 | add r16 = 8,r16 ;; |
414 | add r16 = 8,r16 ;; |
413 | st8 [r16] = r51;; |
415 | st8 [r16] = r51;; |
414 | add r16 = 8,r16 ;; |
416 | add r16 = 8,r16 ;; |
415 | st8 [r16] = r52;; |
417 | st8 [r16] = r52;; |
416 | add r16 = 8,r16 ;; |
418 | add r16 = 8,r16 ;; |
417 | st8 [r16] = r53;; |
419 | st8 [r16] = r53;; |
418 | add r16 = 8,r16 ;; |
420 | add r16 = 8,r16 ;; |
419 | st8 [r16] = r54;; |
421 | st8 [r16] = r54;; |
420 | add r16 = 8,r16 ;; |
422 | add r16 = 8,r16 ;; |
421 | st8 [r16] = r55;; |
423 | st8 [r16] = r55;; |
422 | add r16 = 8,r16 ;; |
424 | add r16 = 8,r16 ;; |
423 | st8 [r16] = r56;; |
425 | st8 [r16] = r56;; |
424 | add r16 = 8,r16 ;; |
426 | add r16 = 8,r16 ;; |
425 | st8 [r16] = r57;; |
427 | st8 [r16] = r57;; |
426 | add r16 = 8,r16 ;; |
428 | add r16 = 8,r16 ;; |
427 | st8 [r16] = r58;; |
429 | st8 [r16] = r58;; |
428 | add r16 = 8,r16 ;; |
430 | add r16 = 8,r16 ;; |
429 | st8 [r16] = r59;; |
431 | st8 [r16] = r59;; |
430 | add r16 = 8,r16 ;; |
432 | add r16 = 8,r16 ;; |
431 | st8 [r16] = r60;; |
433 | st8 [r16] = r60;; |
432 | add r16 = 8,r16 ;; |
434 | add r16 = 8,r16 ;; |
433 | st8 [r16] = r61;; |
435 | st8 [r16] = r61;; |
434 | add r16 = 8,r16 ;; |
436 | add r16 = 8,r16 ;; |
435 | st8 [r16] = r62;; |
437 | st8 [r16] = r62;; |
436 | add r16 = 8,r16 ;; |
438 | add r16 = 8,r16 ;; |
437 | st8 [r16] = r63;; |
439 | st8 [r16] = r63;; |
438 | add r16 = 8,r16 ;; |
440 | add r16 = 8,r16 ;; |
439 | 441 | ||
440 | 442 | ||
441 | 443 | ||
442 | st8 [r16] = r64;; |
444 | st8 [r16] = r64;; |
443 | add r16 = 8,r16 ;; |
445 | add r16 = 8,r16 ;; |
444 | st8 [r16] = r65;; |
446 | st8 [r16] = r65;; |
445 | add r16 = 8,r16 ;; |
447 | add r16 = 8,r16 ;; |
446 | st8 [r16] = r66;; |
448 | st8 [r16] = r66;; |
447 | add r16 = 8,r16 ;; |
449 | add r16 = 8,r16 ;; |
448 | st8 [r16] = r67;; |
450 | st8 [r16] = r67;; |
449 | add r16 = 8,r16 ;; |
451 | add r16 = 8,r16 ;; |
450 | st8 [r16] = r68;; |
452 | st8 [r16] = r68;; |
451 | add r16 = 8,r16 ;; |
453 | add r16 = 8,r16 ;; |
452 | st8 [r16] = r69;; |
454 | st8 [r16] = r69;; |
453 | add r16 = 8,r16 ;; |
455 | add r16 = 8,r16 ;; |
454 | st8 [r16] = r70;; |
456 | st8 [r16] = r70;; |
455 | add r16 = 8,r16 ;; |
457 | add r16 = 8,r16 ;; |
456 | st8 [r16] = r71;; |
458 | st8 [r16] = r71;; |
457 | add r16 = 8,r16 ;; |
459 | add r16 = 8,r16 ;; |
458 | st8 [r16] = r72;; |
460 | st8 [r16] = r72;; |
459 | add r16 = 8,r16 ;; |
461 | add r16 = 8,r16 ;; |
460 | st8 [r16] = r73;; |
462 | st8 [r16] = r73;; |
461 | add r16 = 8,r16 ;; |
463 | add r16 = 8,r16 ;; |
462 | st8 [r16] = r74;; |
464 | st8 [r16] = r74;; |
463 | add r16 = 8,r16 ;; |
465 | add r16 = 8,r16 ;; |
464 | st8 [r16] = r75;; |
466 | st8 [r16] = r75;; |
465 | add r16 = 8,r16 ;; |
467 | add r16 = 8,r16 ;; |
466 | st8 [r16] = r76;; |
468 | st8 [r16] = r76;; |
467 | add r16 = 8,r16 ;; |
469 | add r16 = 8,r16 ;; |
468 | st8 [r16] = r77;; |
470 | st8 [r16] = r77;; |
469 | add r16 = 8,r16 ;; |
471 | add r16 = 8,r16 ;; |
470 | st8 [r16] = r78;; |
472 | st8 [r16] = r78;; |
471 | add r16 = 8,r16 ;; |
473 | add r16 = 8,r16 ;; |
472 | st8 [r16] = r79;; |
474 | st8 [r16] = r79;; |
473 | add r16 = 8,r16 ;; |
475 | add r16 = 8,r16 ;; |
474 | st8 [r16] = r80;; |
476 | st8 [r16] = r80;; |
475 | add r16 = 8,r16 ;; |
477 | add r16 = 8,r16 ;; |
476 | st8 [r16] = r81;; |
478 | st8 [r16] = r81;; |
477 | add r16 = 8,r16 ;; |
479 | add r16 = 8,r16 ;; |
478 | st8 [r16] = r82;; |
480 | st8 [r16] = r82;; |
479 | add r16 = 8,r16 ;; |
481 | add r16 = 8,r16 ;; |
480 | st8 [r16] = r83;; |
482 | st8 [r16] = r83;; |
481 | add r16 = 8,r16 ;; |
483 | add r16 = 8,r16 ;; |
482 | st8 [r16] = r84;; |
484 | st8 [r16] = r84;; |
483 | add r16 = 8,r16 ;; |
485 | add r16 = 8,r16 ;; |
484 | st8 [r16] = r85;; |
486 | st8 [r16] = r85;; |
485 | add r16 = 8,r16 ;; |
487 | add r16 = 8,r16 ;; |
486 | st8 [r16] = r86;; |
488 | st8 [r16] = r86;; |
487 | add r16 = 8,r16 ;; |
489 | add r16 = 8,r16 ;; |
488 | st8 [r16] = r87;; |
490 | st8 [r16] = r87;; |
489 | add r16 = 8,r16 ;; |
491 | add r16 = 8,r16 ;; |
490 | st8 [r16] = r88;; |
492 | st8 [r16] = r88;; |
491 | add r16 = 8,r16 ;; |
493 | add r16 = 8,r16 ;; |
492 | st8 [r16] = r89;; |
494 | st8 [r16] = r89;; |
493 | add r16 = 8,r16 ;; |
495 | add r16 = 8,r16 ;; |
494 | st8 [r16] = r90;; |
496 | st8 [r16] = r90;; |
495 | add r16 = 8,r16 ;; |
497 | add r16 = 8,r16 ;; |
496 | st8 [r16] = r91;; |
498 | st8 [r16] = r91;; |
497 | add r16 = 8,r16 ;; |
499 | add r16 = 8,r16 ;; |
498 | st8 [r16] = r92;; |
500 | st8 [r16] = r92;; |
499 | add r16 = 8,r16 ;; |
501 | add r16 = 8,r16 ;; |
500 | st8 [r16] = r93;; |
502 | st8 [r16] = r93;; |
501 | add r16 = 8,r16 ;; |
503 | add r16 = 8,r16 ;; |
502 | st8 [r16] = r94;; |
504 | st8 [r16] = r94;; |
503 | add r16 = 8,r16 ;; |
505 | add r16 = 8,r16 ;; |
504 | st8 [r16] = r95;; |
506 | st8 [r16] = r95;; |
505 | add r16 = 8,r16 ;; |
507 | add r16 = 8,r16 ;; |
506 | 508 | ||
507 | 509 | ||
508 | 510 | ||
509 | st8 [r16] = r96;; |
511 | st8 [r16] = r96;; |
510 | add r16 = 8,r16 ;; |
512 | add r16 = 8,r16 ;; |
511 | st8 [r16] = r97;; |
513 | st8 [r16] = r97;; |
512 | add r16 = 8,r16 ;; |
514 | add r16 = 8,r16 ;; |
513 | st8 [r16] = r98;; |
515 | st8 [r16] = r98;; |
514 | add r16 = 8,r16 ;; |
516 | add r16 = 8,r16 ;; |
515 | st8 [r16] = r99;; |
517 | st8 [r16] = r99;; |
516 | add r16 = 8,r16 ;; |
518 | add r16 = 8,r16 ;; |
517 | st8 [r16] = r100;; |
519 | st8 [r16] = r100;; |
518 | add r16 = 8,r16 ;; |
520 | add r16 = 8,r16 ;; |
519 | st8 [r16] = r101;; |
521 | st8 [r16] = r101;; |
520 | add r16 = 8,r16 ;; |
522 | add r16 = 8,r16 ;; |
521 | st8 [r16] = r102;; |
523 | st8 [r16] = r102;; |
522 | add r16 = 8,r16 ;; |
524 | add r16 = 8,r16 ;; |
523 | st8 [r16] = r103;; |
525 | st8 [r16] = r103;; |
524 | add r16 = 8,r16 ;; |
526 | add r16 = 8,r16 ;; |
525 | st8 [r16] = r104;; |
527 | st8 [r16] = r104;; |
526 | add r16 = 8,r16 ;; |
528 | add r16 = 8,r16 ;; |
527 | st8 [r16] = r105;; |
529 | st8 [r16] = r105;; |
528 | add r16 = 8,r16 ;; |
530 | add r16 = 8,r16 ;; |
529 | st8 [r16] = r106;; |
531 | st8 [r16] = r106;; |
530 | add r16 = 8,r16 ;; |
532 | add r16 = 8,r16 ;; |
531 | st8 [r16] = r107;; |
533 | st8 [r16] = r107;; |
532 | add r16 = 8,r16 ;; |
534 | add r16 = 8,r16 ;; |
533 | st8 [r16] = r108;; |
535 | st8 [r16] = r108;; |
534 | add r16 = 8,r16 ;; |
536 | add r16 = 8,r16 ;; |
535 | st8 [r16] = r109;; |
537 | st8 [r16] = r109;; |
536 | add r16 = 8,r16 ;; |
538 | add r16 = 8,r16 ;; |
537 | st8 [r16] = r110;; |
539 | st8 [r16] = r110;; |
538 | add r16 = 8,r16 ;; |
540 | add r16 = 8,r16 ;; |
539 | st8 [r16] = r111;; |
541 | st8 [r16] = r111;; |
540 | add r16 = 8,r16 ;; |
542 | add r16 = 8,r16 ;; |
541 | st8 [r16] = r112;; |
543 | st8 [r16] = r112;; |
542 | add r16 = 8,r16 ;; |
544 | add r16 = 8,r16 ;; |
543 | st8 [r16] = r113;; |
545 | st8 [r16] = r113;; |
544 | add r16 = 8,r16 ;; |
546 | add r16 = 8,r16 ;; |
545 | st8 [r16] = r114;; |
547 | st8 [r16] = r114;; |
546 | add r16 = 8,r16 ;; |
548 | add r16 = 8,r16 ;; |
547 | st8 [r16] = r115;; |
549 | st8 [r16] = r115;; |
548 | add r16 = 8,r16 ;; |
550 | add r16 = 8,r16 ;; |
549 | st8 [r16] = r116;; |
551 | st8 [r16] = r116;; |
550 | add r16 = 8,r16 ;; |
552 | add r16 = 8,r16 ;; |
551 | st8 [r16] = r117;; |
553 | st8 [r16] = r117;; |
552 | add r16 = 8,r16 ;; |
554 | add r16 = 8,r16 ;; |
553 | st8 [r16] = r118;; |
555 | st8 [r16] = r118;; |
554 | add r16 = 8,r16 ;; |
556 | add r16 = 8,r16 ;; |
555 | st8 [r16] = r119;; |
557 | st8 [r16] = r119;; |
556 | add r16 = 8,r16 ;; |
558 | add r16 = 8,r16 ;; |
557 | st8 [r16] = r120;; |
559 | st8 [r16] = r120;; |
558 | add r16 = 8,r16 ;; |
560 | add r16 = 8,r16 ;; |
559 | st8 [r16] = r121;; |
561 | st8 [r16] = r121;; |
560 | add r16 = 8,r16 ;; |
562 | add r16 = 8,r16 ;; |
561 | st8 [r16] = r122;; |
563 | st8 [r16] = r122;; |
562 | add r16 = 8,r16 ;; |
564 | add r16 = 8,r16 ;; |
563 | st8 [r16] = r123;; |
565 | st8 [r16] = r123;; |
564 | add r16 = 8,r16 ;; |
566 | add r16 = 8,r16 ;; |
565 | st8 [r16] = r124;; |
567 | st8 [r16] = r124;; |
566 | add r16 = 8,r16 ;; |
568 | add r16 = 8,r16 ;; |
567 | st8 [r16] = r125;; |
569 | st8 [r16] = r125;; |
568 | add r16 = 8,r16 ;; |
570 | add r16 = 8,r16 ;; |
569 | st8 [r16] = r126;; |
571 | st8 [r16] = r126;; |
570 | add r16 = 8,r16 ;; |
572 | add r16 = 8,r16 ;; |
571 | st8 [r16] = r127;; |
573 | st8 [r16] = r127;; |
572 | add r16 = 8,r16 ;; |
574 | add r16 = 8,r16 ;; |
573 | 575 | ||
574 | 576 | ||
575 | 577 | ||
576 | br.ret.sptk.many b0;; |
578 | br.ret.sptk.many b0;; |
577 | 579 | ||
578 | 580 | ||
579 | 581 | ||
580 | 582 | ||
581 | 583 | ||
582 | .macro Handler o h |
584 | .macro Handler o h |
583 | .org IVT + \o |
585 | .org IVT + \o |
584 | br \h;; |
586 | br \h;; |
585 | .endm |
587 | .endm |
586 | 588 | ||
587 | .macro Handler2 o |
589 | .macro Handler2 o |
588 | .org IVT + \o |
590 | .org IVT + \o |
589 | br.call.sptk.many b0 = dump_gregs;; |
591 | br.call.sptk.many b0 = dump_gregs;; |
590 | mov r16 = \o ;; |
592 | mov r16 = \o ;; |
591 | bsw.1;; |
593 | bsw.1;; |
592 | br universal_handler;; |
594 | br universal_handler;; |
593 | .endm |
595 | .endm |
594 | 596 | ||
595 | 597 | ||
596 | 598 | ||
597 | .global IVT |
599 | .global IVT |
598 | .align 32768 |
600 | .align 32768 |
599 | IVT: |
601 | IVT: |
600 | 602 | ||
601 | 603 | ||
602 | Handler2 0x0000 |
604 | Handler2 0x0000 |
603 | Handler2 0x0400 |
605 | Handler2 0x0400 |
604 | Handler2 0x0800 |
606 | Handler2 0x0800 |
605 | Handler2 0x0c00 |
607 | Handler2 0x0c00 |
606 | Handler2 0x1000 |
608 | Handler2 0x1000 |
607 | Handler2 0x1400 |
609 | Handler2 0x1400 |
608 | Handler2 0x1800 |
610 | Handler2 0x1800 |
609 | Handler2 0x1c00 |
611 | Handler2 0x1c00 |
610 | Handler2 0x2000 |
612 | Handler2 0x2000 |
611 | Handler2 0x2400 |
613 | Handler2 0x2400 |
612 | Handler2 0x2800 |
614 | Handler2 0x2800 |
613 | Handler 0x2c00 break_instruction |
615 | Handler 0x2c00 break_instruction |
614 | HEAVYWEIGHT_HANDLER 0x3000 external_interrupt /* For external interrupt, heavyweight handler is used. */ |
616 | HEAVYWEIGHT_HANDLER 0x3000 external_interrupt /* For external interrupt, heavyweight handler is used. */ |
615 | Handler2 0x3400 |
617 | Handler2 0x3400 |
616 | Handler2 0x3800 |
618 | Handler2 0x3800 |
617 | Handler2 0x3c00 |
619 | Handler2 0x3c00 |
618 | Handler2 0x4000 |
620 | Handler2 0x4000 |
619 | Handler2 0x4400 |
621 | Handler2 0x4400 |
620 | Handler2 0x4800 |
622 | Handler2 0x4800 |
621 | Handler2 0x4c00 |
623 | Handler2 0x4c00 |
622 | 624 | ||
623 | Handler2 0x5000 |
625 | Handler2 0x5000 |
624 | Handler2 0x5100 |
626 | Handler2 0x5100 |
625 | Handler2 0x5200 |
627 | Handler2 0x5200 |
626 | Handler2 0x5300 |
628 | Handler2 0x5300 |
627 | #Handler 0x5400 general_exception |
629 | #Handler 0x5400 general_exception |
628 | Handler2 0x5400 |
630 | Handler2 0x5400 |
629 | Handler2 0x5500 |
631 | Handler2 0x5500 |
630 | Handler2 0x5600 |
632 | Handler2 0x5600 |
631 | Handler2 0x5700 |
633 | Handler2 0x5700 |
632 | Handler2 0x5800 |
634 | Handler2 0x5800 |
633 | Handler2 0x5900 |
635 | Handler2 0x5900 |
634 | Handler2 0x5a00 |
636 | Handler2 0x5a00 |
635 | Handler2 0x5b00 |
637 | Handler2 0x5b00 |
636 | Handler2 0x5c00 |
638 | Handler2 0x5c00 |
637 | Handler2 0x5d00 |
639 | Handler2 0x5d00 |
638 | Handler2 0x5e00 |
640 | Handler2 0x5e00 |
639 | Handler2 0x5f00 |
641 | Handler2 0x5f00 |
640 | 642 | ||
641 | Handler2 0x6000 |
643 | Handler2 0x6000 |
642 | Handler2 0x6100 |
644 | Handler2 0x6100 |
643 | Handler2 0x6200 |
645 | Handler2 0x6200 |
644 | Handler2 0x6300 |
646 | Handler2 0x6300 |
645 | Handler2 0x6400 |
647 | Handler2 0x6400 |
646 | Handler2 0x6500 |
648 | Handler2 0x6500 |
647 | Handler2 0x6600 |
649 | Handler2 0x6600 |
648 | Handler2 0x6700 |
650 | Handler2 0x6700 |
649 | Handler2 0x6800 |
651 | Handler2 0x6800 |
650 | Handler2 0x6900 |
652 | Handler2 0x6900 |
651 | Handler2 0x6a00 |
653 | Handler2 0x6a00 |
652 | Handler2 0x6b00 |
654 | Handler2 0x6b00 |
653 | Handler2 0x6c00 |
655 | Handler2 0x6c00 |
654 | Handler2 0x6d00 |
656 | Handler2 0x6d00 |
655 | Handler2 0x6e00 |
657 | Handler2 0x6e00 |
656 | Handler2 0x6f00 |
658 | Handler2 0x6f00 |
657 | 659 | ||
658 | Handler2 0x7000 |
660 | Handler2 0x7000 |
659 | Handler2 0x7100 |
661 | Handler2 0x7100 |
660 | Handler2 0x7200 |
662 | Handler2 0x7200 |
661 | Handler2 0x7300 |
663 | Handler2 0x7300 |
662 | Handler2 0x7400 |
664 | Handler2 0x7400 |
663 | Handler2 0x7500 |
665 | Handler2 0x7500 |
664 | Handler2 0x7600 |
666 | Handler2 0x7600 |
665 | Handler2 0x7700 |
667 | Handler2 0x7700 |
666 | Handler2 0x7800 |
668 | Handler2 0x7800 |
667 | Handler2 0x7900 |
669 | Handler2 0x7900 |
668 | Handler2 0x7a00 |
670 | Handler2 0x7a00 |
669 | Handler2 0x7b00 |
671 | Handler2 0x7b00 |
670 | Handler2 0x7c00 |
672 | Handler2 0x7c00 |
671 | Handler2 0x7d00 |
673 | Handler2 0x7d00 |
672 | Handler2 0x7e00 |
674 | Handler2 0x7e00 |
673 | Handler2 0x7f00 |
675 | Handler2 0x7f00 |
674 | 676 | ||
675 | 677 | ||
676 | 678 | ||
677 | 679 | ||
678 | 680 | ||
679 | 681 | ||
680 | 682 | ||
681 | 683 | ||
682 | .align 32768 |
684 | .align 32768 |
683 | .global REG_DUMP |
685 | .global REG_DUMP |
684 | 686 | ||
685 | REG_DUMP: |
687 | REG_DUMP: |
686 | .space 128*8 |
688 | .space 128*8 |
687 | 689 | ||
688 | 690 |