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1 | /* |
1 | /* |
2 | * Copyright (C) 2005 Jakub Jermar |
2 | * Copyright (C) 2005 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | #ifndef __ia64_REGISTER_H__ |
29 | #ifndef __ia64_REGISTER_H__ |
30 | #define __ia64_REGISTER_H__ |
30 | #define __ia64_REGISTER_H__ |
31 | 31 | ||
32 | #ifndef __ASM__ |
32 | #ifndef __ASM__ |
33 | #include <arch/types.h> |
33 | #include <arch/types.h> |
34 | #endif |
34 | #endif |
35 | 35 | ||
36 | #define CR_IVR_MASK 0xf |
36 | #define CR_IVR_MASK 0xf |
37 | #define PSR_I_MASK 0x4000 |
- | |
38 | #define PSR_IC_MASK 0x2000 |
37 | #define PSR_IC_MASK 0x2000 |
- | 38 | #define PSR_I_MASK 0x4000 |
|
- | 39 | #define PSR_PK_MASK 0x8000 |
|
39 | 40 | ||
40 | /** Application registers. */ |
41 | /** Application registers. */ |
41 | #define AR_KR0 0 |
42 | #define AR_KR0 0 |
42 | #define AR_KR1 1 |
43 | #define AR_KR1 1 |
43 | #define AR_KR2 2 |
44 | #define AR_KR2 2 |
44 | #define AR_KR3 3 |
45 | #define AR_KR3 3 |
45 | #define AR_KR4 4 |
46 | #define AR_KR4 4 |
46 | #define AR_KR5 5 |
47 | #define AR_KR5 5 |
47 | #define AR_KR6 6 |
48 | #define AR_KR6 6 |
48 | #define AR_KR7 7 |
49 | #define AR_KR7 7 |
49 | /* AR 8-15 reserved */ |
50 | /* AR 8-15 reserved */ |
50 | #define AR_RSC 16 |
51 | #define AR_RSC 16 |
51 | #define AR_BSP 17 |
52 | #define AR_BSP 17 |
52 | #define AR_BSPSTORE 18 |
53 | #define AR_BSPSTORE 18 |
53 | #define AR_RNAT 19 |
54 | #define AR_RNAT 19 |
54 | /* AR 20 reserved */ |
55 | /* AR 20 reserved */ |
55 | #define AR_FCR 21 |
56 | #define AR_FCR 21 |
56 | /* AR 22-23 reserved */ |
57 | /* AR 22-23 reserved */ |
57 | #define AR_EFLAG 24 |
58 | #define AR_EFLAG 24 |
58 | #define AR_CSD 25 |
59 | #define AR_CSD 25 |
59 | #define AR_SSD 26 |
60 | #define AR_SSD 26 |
60 | #define AR_CFLG 27 |
61 | #define AR_CFLG 27 |
61 | #define AR_FSR 28 |
62 | #define AR_FSR 28 |
62 | #define AR_FIR 29 |
63 | #define AR_FIR 29 |
63 | #define AR_FDR 30 |
64 | #define AR_FDR 30 |
64 | /* AR 31 reserved */ |
65 | /* AR 31 reserved */ |
65 | #define AR_CCV 32 |
66 | #define AR_CCV 32 |
66 | /* AR 33-35 reserved */ |
67 | /* AR 33-35 reserved */ |
67 | #define AR_UNAT 36 |
68 | #define AR_UNAT 36 |
68 | /* AR 37-39 reserved */ |
69 | /* AR 37-39 reserved */ |
69 | #define AR_FPSR 40 |
70 | #define AR_FPSR 40 |
70 | /* AR 41-43 reserved */ |
71 | /* AR 41-43 reserved */ |
71 | #define AR_ITC 44 |
72 | #define AR_ITC 44 |
72 | /* AR 45-47 reserved */ |
73 | /* AR 45-47 reserved */ |
73 | /* AR 48-63 ignored */ |
74 | /* AR 48-63 ignored */ |
74 | #define AR_PFS 64 |
75 | #define AR_PFS 64 |
75 | #define AR_LC 65 |
76 | #define AR_LC 65 |
76 | #define AR_EC 66 |
77 | #define AR_EC 66 |
77 | /* AR 67-111 reserved */ |
78 | /* AR 67-111 reserved */ |
78 | /* AR 112-127 ignored */ |
79 | /* AR 112-127 ignored */ |
79 | 80 | ||
80 | /** Control registers. */ |
81 | /** Control registers. */ |
81 | #define CR_DCR 0 |
82 | #define CR_DCR 0 |
82 | #define CR_ITM 1 |
83 | #define CR_ITM 1 |
83 | #define CR_IVA 2 |
84 | #define CR_IVA 2 |
84 | /* CR3-CR7 reserved */ |
85 | /* CR3-CR7 reserved */ |
85 | #define CR_PTA 8 |
86 | #define CR_PTA 8 |
86 | /* CR9-CR15 reserved */ |
87 | /* CR9-CR15 reserved */ |
87 | #define CR_IPSR 16 |
88 | #define CR_IPSR 16 |
88 | #define CR_ISR 17 |
89 | #define CR_ISR 17 |
89 | /* CR18 reserved */ |
90 | /* CR18 reserved */ |
90 | #define CR_IIP 19 |
91 | #define CR_IIP 19 |
91 | #define CR_IFA 20 |
92 | #define CR_IFA 20 |
92 | #define CR_ITIR 21 |
93 | #define CR_ITIR 21 |
93 | #define CR_IIPA 22 |
94 | #define CR_IIPA 22 |
94 | #define CR_IFS 23 |
95 | #define CR_IFS 23 |
95 | #define CR_IIM 24 |
96 | #define CR_IIM 24 |
96 | #define CR_IHA 25 |
97 | #define CR_IHA 25 |
97 | /* CR26-CR63 reserved */ |
98 | /* CR26-CR63 reserved */ |
98 | #define CR_LID 64 |
99 | #define CR_LID 64 |
99 | #define CR_IVR 65 |
100 | #define CR_IVR 65 |
100 | #define CR_TPR 66 |
101 | #define CR_TPR 66 |
101 | #define CR_EOI 67 |
102 | #define CR_EOI 67 |
102 | #define CR_IRR0 68 |
103 | #define CR_IRR0 68 |
103 | #define CR_IRR1 69 |
104 | #define CR_IRR1 69 |
104 | #define CR_IRR2 70 |
105 | #define CR_IRR2 70 |
105 | #define CR_IRR3 71 |
106 | #define CR_IRR3 71 |
106 | #define CR_ITV 72 |
107 | #define CR_ITV 72 |
107 | #define CR_PMV 73 |
108 | #define CR_PMV 73 |
108 | #define CR_CMCV 74 |
109 | #define CR_CMCV 74 |
109 | /* CR75-CR79 reserved */ |
110 | /* CR75-CR79 reserved */ |
110 | #define CR_LRR0 80 |
111 | #define CR_LRR0 80 |
111 | #define CR_LRR1 81 |
112 | #define CR_LRR1 81 |
112 | /* CR82-CR127 reserved */ |
113 | /* CR82-CR127 reserved */ |
113 | 114 | ||
114 | #ifndef __ASM__ |
115 | #ifndef __ASM__ |
115 | /** External Interrupt Vector Register */ |
116 | /** External Interrupt Vector Register */ |
116 | union cr_ivr { |
117 | union cr_ivr { |
117 | __u8 vector; |
118 | __u8 vector; |
118 | __u64 value; |
119 | __u64 value; |
119 | }; |
120 | }; |
120 | 121 | ||
121 | typedef union cr_ivr cr_ivr_t; |
122 | typedef union cr_ivr cr_ivr_t; |
122 | 123 | ||
123 | /** Task Priority Register */ |
124 | /** Task Priority Register */ |
124 | union cr_tpr { |
125 | union cr_tpr { |
125 | struct { |
126 | struct { |
126 | unsigned : 4; |
127 | unsigned : 4; |
127 | unsigned mic: 4; /**< Mask Interrupt Class. */ |
128 | unsigned mic: 4; /**< Mask Interrupt Class. */ |
128 | unsigned : 8; |
129 | unsigned : 8; |
129 | unsigned mmi: 1; /**< Mask Maskable Interrupts. */ |
130 | unsigned mmi: 1; /**< Mask Maskable Interrupts. */ |
130 | } __attribute__ ((packed)); |
131 | } __attribute__ ((packed)); |
131 | __u64 value; |
132 | __u64 value; |
132 | }; |
133 | }; |
133 | 134 | ||
134 | typedef union cr_tpr cr_tpr_t; |
135 | typedef union cr_tpr cr_tpr_t; |
135 | 136 | ||
136 | /** Interval Timer Vector */ |
137 | /** Interval Timer Vector */ |
137 | union cr_itv { |
138 | union cr_itv { |
138 | struct { |
139 | struct { |
139 | unsigned vector : 8; |
140 | unsigned vector : 8; |
140 | unsigned : 4; |
141 | unsigned : 4; |
141 | unsigned : 1; |
142 | unsigned : 1; |
142 | unsigned : 3; |
143 | unsigned : 3; |
143 | unsigned m : 1; /**< Mask. */ |
144 | unsigned m : 1; /**< Mask. */ |
144 | } __attribute__ ((packed)); |
145 | } __attribute__ ((packed)); |
145 | __u64 value; |
146 | __u64 value; |
146 | }; |
147 | }; |
147 | 148 | ||
148 | typedef union cr_itv cr_itv_t; |
149 | typedef union cr_itv cr_itv_t; |
149 | 150 | ||
150 | /** Interruption Status Register */ |
151 | /** Interruption Status Register */ |
151 | union cr_isr { |
152 | union cr_isr { |
152 | struct { |
153 | struct { |
153 | union { |
154 | union { |
154 | /** General Exception code field structuring. */ |
155 | /** General Exception code field structuring. */ |
155 | struct { |
156 | struct { |
156 | unsigned ge_na : 4; |
157 | unsigned ge_na : 4; |
157 | unsigned ge_code : 4; |
158 | unsigned ge_code : 4; |
158 | } __attribute__ ((packed)); |
159 | } __attribute__ ((packed)); |
159 | __u16 code; |
160 | __u16 code; |
160 | }; |
161 | }; |
161 | __u8 vector; |
162 | __u8 vector; |
162 | unsigned : 8; |
163 | unsigned : 8; |
163 | unsigned x : 1; /**< Execute exception. */ |
164 | unsigned x : 1; /**< Execute exception. */ |
164 | unsigned w : 1; /**< Write exception. */ |
165 | unsigned w : 1; /**< Write exception. */ |
165 | unsigned r : 1; /**< Read exception. */ |
166 | unsigned r : 1; /**< Read exception. */ |
166 | unsigned na : 1; /**< Non-access exception. */ |
167 | unsigned na : 1; /**< Non-access exception. */ |
167 | unsigned sp : 1; /**< Speculative load exception. */ |
168 | unsigned sp : 1; /**< Speculative load exception. */ |
168 | unsigned rs : 1; /**< Register stack. */ |
169 | unsigned rs : 1; /**< Register stack. */ |
169 | unsigned ir : 1; /**< Incomplete Register frame. */ |
170 | unsigned ir : 1; /**< Incomplete Register frame. */ |
170 | unsigned ni : 1; /**< Nested Interruption. */ |
171 | unsigned ni : 1; /**< Nested Interruption. */ |
171 | unsigned so : 1; /**< IA-32 Supervisor Override. */ |
172 | unsigned so : 1; /**< IA-32 Supervisor Override. */ |
172 | unsigned ei : 2; /**< Excepting Instruction. */ |
173 | unsigned ei : 2; /**< Excepting Instruction. */ |
173 | unsigned ed : 1; /**< Exception Deferral. */ |
174 | unsigned ed : 1; /**< Exception Deferral. */ |
174 | unsigned : 20; |
175 | unsigned : 20; |
175 | } __attribute__ ((packed)); |
176 | } __attribute__ ((packed)); |
176 | __u64 value; |
177 | __u64 value; |
177 | }; |
178 | }; |
178 | 179 | ||
179 | typedef union cr_isr cr_isr_t; |
180 | typedef union cr_isr cr_isr_t; |
180 | 181 | ||
181 | /** CPUID Register 3 */ |
182 | /** CPUID Register 3 */ |
182 | union cpuid3 { |
183 | union cpuid3 { |
183 | struct { |
184 | struct { |
184 | __u8 number; |
185 | __u8 number; |
185 | __u8 revision; |
186 | __u8 revision; |
186 | __u8 model; |
187 | __u8 model; |
187 | __u8 family; |
188 | __u8 family; |
188 | __u8 archrev; |
189 | __u8 archrev; |
189 | } __attribute__ ((packed)); |
190 | } __attribute__ ((packed)); |
190 | __u64 value; |
191 | __u64 value; |
191 | }; |
192 | }; |
192 | 193 | ||
193 | typedef union cpuid3 cpuid3_t; |
194 | typedef union cpuid3 cpuid3_t; |
194 | 195 | ||
195 | #endif /* !__ASM__ */ |
196 | #endif /* !__ASM__ */ |
196 | 197 | ||
197 | #endif |
198 | #endif |
198 | 199 |