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1 | /* |
1 | /* |
2 | * Copyright (c) 2005 - 2006 Jakub Jermar |
2 | * Copyright (c) 2005 - 2006 Jakub Jermar |
3 | * Copyright (c) 2006 Jakub Vana |
3 | * Copyright (c) 2006 Jakub Vana |
4 | * All rights reserved. |
4 | * All rights reserved. |
5 | * |
5 | * |
6 | * Redistribution and use in source and binary forms, with or without |
6 | * Redistribution and use in source and binary forms, with or without |
7 | * modification, are permitted provided that the following conditions |
7 | * modification, are permitted provided that the following conditions |
8 | * are met: |
8 | * are met: |
9 | * |
9 | * |
10 | * - Redistributions of source code must retain the above copyright |
10 | * - Redistributions of source code must retain the above copyright |
11 | * notice, this list of conditions and the following disclaimer. |
11 | * notice, this list of conditions and the following disclaimer. |
12 | * - Redistributions in binary form must reproduce the above copyright |
12 | * - Redistributions in binary form must reproduce the above copyright |
13 | * notice, this list of conditions and the following disclaimer in the |
13 | * notice, this list of conditions and the following disclaimer in the |
14 | * documentation and/or other materials provided with the distribution. |
14 | * documentation and/or other materials provided with the distribution. |
15 | * - The name of the author may not be used to endorse or promote products |
15 | * - The name of the author may not be used to endorse or promote products |
16 | * derived from this software without specific prior written permission. |
16 | * derived from this software without specific prior written permission. |
17 | * |
17 | * |
18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
21 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
23 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
27 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
28 | */ |
28 | */ |
29 | 29 | ||
30 | /** @addtogroup ia64mm |
30 | /** @addtogroup ia64mm |
31 | * @{ |
31 | * @{ |
32 | */ |
32 | */ |
33 | /** @file |
33 | /** @file |
34 | */ |
34 | */ |
35 | 35 | ||
36 | #ifndef KERN_ia64_PAGE_H_ |
36 | #ifndef KERN_ia64_PAGE_H_ |
37 | #define KERN_ia64_PAGE_H_ |
37 | #define KERN_ia64_PAGE_H_ |
38 | 38 | ||
39 | #include <arch/mm/frame.h> |
39 | #include <arch/mm/frame.h> |
40 | 40 | ||
41 | #define PAGE_SIZE FRAME_SIZE |
41 | #define PAGE_SIZE FRAME_SIZE |
42 | #define PAGE_WIDTH FRAME_WIDTH |
42 | #define PAGE_WIDTH FRAME_WIDTH |
43 | 43 | ||
44 | #ifdef KERNEL |
44 | #ifdef KERNEL |
45 | 45 | ||
46 | /** Bit width of the TLB-locked portion of kernel address space. */ |
46 | /** Bit width of the TLB-locked portion of kernel address space. */ |
47 | #define KERNEL_PAGE_WIDTH 28 /* 256M */ |
47 | #define KERNEL_PAGE_WIDTH 28 /* 256M */ |
48 | #define IO_PAGE_WIDTH 26 /* 64M */ |
48 | #define IO_PAGE_WIDTH 26 /* 64M */ |
49 | #define FW_PAGE_WIDTH 28 /* 256M */ |
49 | #define FW_PAGE_WIDTH 28 /* 256M */ |
50 | 50 | ||
51 | #define USPACE_IO_PAGE_WIDTH 12 /* 4K */ |
51 | #define USPACE_IO_PAGE_WIDTH 12 /* 4K */ |
52 | 52 | ||
53 | 53 | ||
54 | /* |
54 | /* |
55 | * Statically mapped IO spaces - offsets to 0xe...00 of virtual addresses |
55 | * Statically mapped IO spaces - offsets to 0xe...00 of virtual addresses |
56 | * because of "minimal virtual bits implemented is 51" it is possible to |
56 | * because of "minimal virtual bits implemented is 51" it is possible to |
57 | * have values up to 0x0007000000000000 |
57 | * have values up to 0x0007000000000000 |
58 | */ |
58 | */ |
59 | 59 | ||
60 | /* Firmware area (bellow 4GB in phys mem) */ |
60 | /* Firmware area (bellow 4GB in phys mem) */ |
61 | #define FW_OFFSET 0x00000000F0000000 |
61 | #define FW_OFFSET 0x00000000F0000000 |
62 | /* Legacy IO space */ |
62 | /* Legacy IO space */ |
63 | #define IO_OFFSET 0x0001000000000000 |
63 | #define IO_OFFSET 0x0001000000000000 |
64 | /* Videoram - now mapped to 0 as VGA text mode vram on 0xb8000 */ |
64 | /* Videoram - now mapped to 0 as VGA text mode vram on 0xb8000 */ |
65 | #define VIO_OFFSET 0x0002000000000000 |
65 | #define VIO_OFFSET 0x0002000000000000 |
66 | 66 | ||
67 | 67 | ||
68 | #define PPN_SHIFT 12 |
68 | #define PPN_SHIFT 12 |
69 | 69 | ||
70 | #define VRN_SHIFT 61 |
70 | #define VRN_SHIFT 61 |
71 | #define VRN_MASK (7LL << VRN_SHIFT) |
71 | #define VRN_MASK (7LL << VRN_SHIFT) |
72 | #define VA2VRN(va) ((va)>>VRN_SHIFT) |
72 | #define VA2VRN(va) ((va)>>VRN_SHIFT) |
73 | 73 | ||
74 | #ifdef __ASM__ |
74 | #ifdef __ASM__ |
75 | #define VRN_KERNEL 7 |
75 | #define VRN_KERNEL 7 |
76 | #else |
76 | #else |
77 | #define VRN_KERNEL 7LL |
77 | #define VRN_KERNEL 7LL |
78 | #endif |
78 | #endif |
79 | 79 | ||
80 | #define REGION_REGISTERS 8 |
80 | #define REGION_REGISTERS 8 |
81 | 81 | ||
82 | #define KA2PA(x) ((uintptr_t) (x - (VRN_KERNEL << VRN_SHIFT))) |
82 | #define KA2PA(x) ((uintptr_t) (x - (VRN_KERNEL << VRN_SHIFT))) |
83 | #define PA2KA(x) ((uintptr_t) (x + (VRN_KERNEL << VRN_SHIFT))) |
83 | #define PA2KA(x) ((uintptr_t) (x + (VRN_KERNEL << VRN_SHIFT))) |
84 | 84 | ||
85 | #define VHPT_WIDTH 20 /* 1M */ |
85 | #define VHPT_WIDTH 20 /* 1M */ |
86 | #define VHPT_SIZE (1 << VHPT_WIDTH) |
86 | #define VHPT_SIZE (1 << VHPT_WIDTH) |
87 | 87 | ||
88 | #define PTA_BASE_SHIFT 15 |
88 | #define PTA_BASE_SHIFT 15 |
89 | 89 | ||
90 | /** Memory Attributes. */ |
90 | /** Memory Attributes. */ |
91 | #define MA_WRITEBACK 0x0 |
91 | #define MA_WRITEBACK 0x0 |
92 | #define MA_UNCACHEABLE 0x4 |
92 | #define MA_UNCACHEABLE 0x4 |
93 | 93 | ||
94 | /** Privilege Levels. Only the most and the least privileged ones are ever used. */ |
94 | /** Privilege Levels. Only the most and the least privileged ones are ever used. */ |
95 | #define PL_KERNEL 0x0 |
95 | #define PL_KERNEL 0x0 |
96 | #define PL_USER 0x3 |
96 | #define PL_USER 0x3 |
97 | 97 | ||
98 | /* Access Rigths. Only certain combinations are used by the kernel. */ |
98 | /* Access Rigths. Only certain combinations are used by the kernel. */ |
99 | #define AR_READ 0x0 |
99 | #define AR_READ 0x0 |
100 | #define AR_EXECUTE 0x1 |
100 | #define AR_EXECUTE 0x1 |
101 | #define AR_WRITE 0x2 |
101 | #define AR_WRITE 0x2 |
102 | 102 | ||
103 | #ifndef __ASM__ |
103 | #ifndef __ASM__ |
104 | 104 | ||
105 | #include <arch/mm/as.h> |
105 | #include <arch/mm/as.h> |
106 | #include <arch/mm/frame.h> |
106 | #include <arch/mm/frame.h> |
107 | #include <arch/interrupt.h> |
107 | #include <arch/interrupt.h> |
108 | #include <arch/barrier.h> |
108 | #include <arch/barrier.h> |
109 | #include <arch/mm/asid.h> |
109 | #include <arch/mm/asid.h> |
110 | #include <arch/types.h> |
110 | #include <arch/types.h> |
111 | #include <debug.h> |
111 | #include <debug.h> |
112 | 112 | ||
113 | struct vhpt_tag_info { |
113 | struct vhpt_tag_info { |
114 | unsigned long long tag : 63; |
114 | unsigned long long tag : 63; |
115 | unsigned ti : 1; |
115 | unsigned ti : 1; |
116 | } __attribute__ ((packed)); |
116 | } __attribute__ ((packed)); |
117 | 117 | ||
118 | union vhpt_tag { |
118 | union vhpt_tag { |
119 | struct vhpt_tag_info tag_info; |
119 | struct vhpt_tag_info tag_info; |
120 | unsigned tag_word; |
120 | unsigned tag_word; |
121 | }; |
121 | }; |
122 | 122 | ||
123 | struct vhpt_entry_present { |
123 | struct vhpt_entry_present { |
124 | /* Word 0 */ |
124 | /* Word 0 */ |
125 | unsigned p : 1; |
125 | unsigned p : 1; |
126 | unsigned : 1; |
126 | unsigned : 1; |
127 | unsigned ma : 3; |
127 | unsigned ma : 3; |
128 | unsigned a : 1; |
128 | unsigned a : 1; |
129 | unsigned d : 1; |
129 | unsigned d : 1; |
130 | unsigned pl : 2; |
130 | unsigned pl : 2; |
131 | unsigned ar : 3; |
131 | unsigned ar : 3; |
132 | unsigned long long ppn : 38; |
132 | unsigned long long ppn : 38; |
133 | unsigned : 2; |
133 | unsigned : 2; |
134 | unsigned ed : 1; |
134 | unsigned ed : 1; |
135 | unsigned ig1 : 11; |
135 | unsigned ig1 : 11; |
136 | 136 | ||
137 | /* Word 1 */ |
137 | /* Word 1 */ |
138 | unsigned : 2; |
138 | unsigned : 2; |
139 | unsigned ps : 6; |
139 | unsigned ps : 6; |
140 | unsigned key : 24; |
140 | unsigned key : 24; |
141 | unsigned : 32; |
141 | unsigned : 32; |
142 | 142 | ||
143 | /* Word 2 */ |
143 | /* Word 2 */ |
144 | union vhpt_tag tag; |
144 | union vhpt_tag tag; |
145 | 145 | ||
146 | /* Word 3 */ |
146 | /* Word 3 */ |
147 | uint64_t ig3 : 64; |
147 | uint64_t ig3 : 64; |
148 | } __attribute__ ((packed)); |
148 | } __attribute__ ((packed)); |
149 | 149 | ||
150 | struct vhpt_entry_not_present { |
150 | struct vhpt_entry_not_present { |
151 | /* Word 0 */ |
151 | /* Word 0 */ |
152 | unsigned p : 1; |
152 | unsigned p : 1; |
153 | unsigned long long ig0 : 52; |
153 | unsigned long long ig0 : 52; |
154 | unsigned ig1 : 11; |
154 | unsigned ig1 : 11; |
155 | 155 | ||
156 | /* Word 1 */ |
156 | /* Word 1 */ |
157 | unsigned : 2; |
157 | unsigned : 2; |
158 | unsigned ps : 6; |
158 | unsigned ps : 6; |
159 | unsigned long long ig2 : 56; |
159 | unsigned long long ig2 : 56; |
160 | 160 | ||
161 | /* Word 2 */ |
161 | /* Word 2 */ |
162 | union vhpt_tag tag; |
162 | union vhpt_tag tag; |
163 | 163 | ||
164 | /* Word 3 */ |
164 | /* Word 3 */ |
165 | uint64_t ig3 : 64; |
165 | uint64_t ig3 : 64; |
166 | } __attribute__ ((packed)); |
166 | } __attribute__ ((packed)); |
167 | 167 | ||
168 | typedef union vhpt_entry { |
168 | typedef union vhpt_entry { |
169 | struct vhpt_entry_present present; |
169 | struct vhpt_entry_present present; |
170 | struct vhpt_entry_not_present not_present; |
170 | struct vhpt_entry_not_present not_present; |
171 | uint64_t word[4]; |
171 | uint64_t word[4]; |
172 | } vhpt_entry_t; |
172 | } vhpt_entry_t; |
173 | 173 | ||
174 | struct region_register_map { |
174 | struct region_register_map { |
175 | unsigned ve : 1; |
175 | unsigned ve : 1; |
176 | unsigned : 1; |
176 | unsigned : 1; |
177 | unsigned ps : 6; |
177 | unsigned ps : 6; |
178 | unsigned rid : 24; |
178 | unsigned rid : 24; |
179 | unsigned : 32; |
179 | unsigned : 32; |
180 | } __attribute__ ((packed)); |
180 | } __attribute__ ((packed)); |
181 | 181 | ||
182 | typedef union region_register { |
182 | typedef union region_register { |
183 | struct region_register_map map; |
183 | struct region_register_map map; |
184 | unsigned long long word; |
184 | unsigned long long word; |
185 | } region_register; |
185 | } region_register; |
186 | 186 | ||
187 | struct pta_register_map { |
187 | struct pta_register_map { |
188 | unsigned ve : 1; |
188 | unsigned ve : 1; |
189 | unsigned : 1; |
189 | unsigned : 1; |
190 | unsigned size : 6; |
190 | unsigned size : 6; |
191 | unsigned vf : 1; |
191 | unsigned vf : 1; |
192 | unsigned : 6; |
192 | unsigned : 6; |
193 | unsigned long long base : 49; |
193 | unsigned long long base : 49; |
194 | } __attribute__ ((packed)); |
194 | } __attribute__ ((packed)); |
195 | 195 | ||
196 | typedef union pta_register { |
196 | typedef union pta_register { |
197 | struct pta_register_map map; |
197 | struct pta_register_map map; |
198 | uint64_t word; |
198 | uint64_t word; |
199 | } pta_register; |
199 | } pta_register; |
200 | 200 | ||
201 | /** Return Translation Hashed Entry Address. |
201 | /** Return Translation Hashed Entry Address. |
202 | * |
202 | * |
203 | * VRN bits are used to read RID (ASID) from one |
203 | * VRN bits are used to read RID (ASID) from one |
204 | * of the eight region registers registers. |
204 | * of the eight region registers registers. |
205 | * |
205 | * |
206 | * @param va Virtual address including VRN bits. |
206 | * @param va Virtual address including VRN bits. |
207 | * |
207 | * |
208 | * @return Address of the head of VHPT collision chain. |
208 | * @return Address of the head of VHPT collision chain. |
209 | */ |
209 | */ |
210 | static inline uint64_t thash(uint64_t va) |
210 | static inline uint64_t thash(uint64_t va) |
211 | { |
211 | { |
212 | uint64_t ret; |
212 | uint64_t ret; |
213 | 213 | ||
214 | asm volatile ("thash %0 = %1\n" : "=r" (ret) : "r" (va)); |
214 | asm volatile ("thash %0 = %1\n" : "=r" (ret) : "r" (va)); |
215 | 215 | ||
216 | return ret; |
216 | return ret; |
217 | } |
217 | } |
218 | 218 | ||
219 | /** Return Translation Hashed Entry Tag. |
219 | /** Return Translation Hashed Entry Tag. |
220 | * |
220 | * |
221 | * VRN bits are used to read RID (ASID) from one |
221 | * VRN bits are used to read RID (ASID) from one |
222 | * of the eight region registers. |
222 | * of the eight region registers. |
223 | * |
223 | * |
224 | * @param va Virtual address including VRN bits. |
224 | * @param va Virtual address including VRN bits. |
225 | * |
225 | * |
226 | * @return The unique tag for VPN and RID in the collision chain returned by thash(). |
226 | * @return The unique tag for VPN and RID in the collision chain returned by thash(). |
227 | */ |
227 | */ |
228 | static inline uint64_t ttag(uint64_t va) |
228 | static inline uint64_t ttag(uint64_t va) |
229 | { |
229 | { |
230 | uint64_t ret; |
230 | uint64_t ret; |
231 | 231 | ||
232 | asm volatile ("ttag %0 = %1\n" : "=r" (ret) : "r" (va)); |
232 | asm volatile ("ttag %0 = %1\n" : "=r" (ret) : "r" (va)); |
233 | 233 | ||
234 | return ret; |
234 | return ret; |
235 | } |
235 | } |
236 | 236 | ||
237 | /** Read Region Register. |
237 | /** Read Region Register. |
238 | * |
238 | * |
239 | * @param i Region register index. |
239 | * @param i Region register index. |
240 | * |
240 | * |
241 | * @return Current contents of rr[i]. |
241 | * @return Current contents of rr[i]. |
242 | */ |
242 | */ |
243 | static inline uint64_t rr_read(index_t i) |
243 | static inline uint64_t rr_read(size_t i) |
244 | { |
244 | { |
245 | uint64_t ret; |
245 | uint64_t ret; |
246 | ASSERT(i < REGION_REGISTERS); |
246 | ASSERT(i < REGION_REGISTERS); |
247 | asm volatile ("mov %0 = rr[%1]\n" : "=r" (ret) : "r" (i << VRN_SHIFT)); |
247 | asm volatile ("mov %0 = rr[%1]\n" : "=r" (ret) : "r" (i << VRN_SHIFT)); |
248 | return ret; |
248 | return ret; |
249 | } |
249 | } |
250 | 250 | ||
251 | /** Write Region Register. |
251 | /** Write Region Register. |
252 | * |
252 | * |
253 | * @param i Region register index. |
253 | * @param i Region register index. |
254 | * @param v Value to be written to rr[i]. |
254 | * @param v Value to be written to rr[i]. |
255 | */ |
255 | */ |
256 | static inline void rr_write(index_t i, uint64_t v) |
256 | static inline void rr_write(size_t i, uint64_t v) |
257 | { |
257 | { |
258 | ASSERT(i < REGION_REGISTERS); |
258 | ASSERT(i < REGION_REGISTERS); |
259 | asm volatile ( |
259 | asm volatile ( |
260 | "mov rr[%0] = %1\n" |
260 | "mov rr[%0] = %1\n" |
261 | : |
261 | : |
262 | : "r" (i << VRN_SHIFT), "r" (v) |
262 | : "r" (i << VRN_SHIFT), "r" (v) |
263 | ); |
263 | ); |
264 | } |
264 | } |
265 | 265 | ||
266 | /** Read Page Table Register. |
266 | /** Read Page Table Register. |
267 | * |
267 | * |
268 | * @return Current value stored in PTA. |
268 | * @return Current value stored in PTA. |
269 | */ |
269 | */ |
270 | static inline uint64_t pta_read(void) |
270 | static inline uint64_t pta_read(void) |
271 | { |
271 | { |
272 | uint64_t ret; |
272 | uint64_t ret; |
273 | 273 | ||
274 | asm volatile ("mov %0 = cr.pta\n" : "=r" (ret)); |
274 | asm volatile ("mov %0 = cr.pta\n" : "=r" (ret)); |
275 | 275 | ||
276 | return ret; |
276 | return ret; |
277 | } |
277 | } |
278 | 278 | ||
279 | /** Write Page Table Register. |
279 | /** Write Page Table Register. |
280 | * |
280 | * |
281 | * @param v New value to be stored in PTA. |
281 | * @param v New value to be stored in PTA. |
282 | */ |
282 | */ |
283 | static inline void pta_write(uint64_t v) |
283 | static inline void pta_write(uint64_t v) |
284 | { |
284 | { |
285 | asm volatile ("mov cr.pta = %0\n" : : "r" (v)); |
285 | asm volatile ("mov cr.pta = %0\n" : : "r" (v)); |
286 | } |
286 | } |
287 | 287 | ||
288 | extern void page_arch_init(void); |
288 | extern void page_arch_init(void); |
289 | 289 | ||
290 | extern vhpt_entry_t *vhpt_hash(uintptr_t page, asid_t asid); |
290 | extern vhpt_entry_t *vhpt_hash(uintptr_t page, asid_t asid); |
291 | extern bool vhpt_compare(uintptr_t page, asid_t asid, vhpt_entry_t *v); |
291 | extern bool vhpt_compare(uintptr_t page, asid_t asid, vhpt_entry_t *v); |
292 | extern void vhpt_set_record(vhpt_entry_t *v, uintptr_t page, asid_t asid, uintptr_t frame, int flags); |
292 | extern void vhpt_set_record(vhpt_entry_t *v, uintptr_t page, asid_t asid, uintptr_t frame, int flags); |
293 | 293 | ||
294 | #endif /* __ASM__ */ |
294 | #endif /* __ASM__ */ |
295 | 295 | ||
296 | #endif /* KERNEL */ |
296 | #endif /* KERNEL */ |
297 | 297 | ||
298 | #endif |
298 | #endif |
299 | 299 | ||
300 | /** @} |
300 | /** @} |
301 | */ |
301 | */ |
302 | 302 |