Rev 1888 | Rev 2071 | Go to most recent revision | Only display areas with differences | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
Rev 1888 | Rev 1970 | ||
---|---|---|---|
1 | /* |
1 | /* |
2 | * Copyright (C) 2001-2004 Jakub Jermar |
2 | * Copyright (C) 2001-2004 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup ia32 |
29 | /** @addtogroup ia32 |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | */ |
33 | */ |
34 | 34 | ||
35 | #include <arch/types.h> |
35 | #include <arch/types.h> |
36 | #include <arch/smp/apic.h> |
36 | #include <arch/smp/apic.h> |
37 | #include <arch/smp/ap.h> |
37 | #include <arch/smp/ap.h> |
38 | #include <arch/smp/mps.h> |
38 | #include <arch/smp/mps.h> |
39 | #include <arch/boot/boot.h> |
39 | #include <arch/boot/boot.h> |
40 | #include <mm/page.h> |
40 | #include <mm/page.h> |
41 | #include <time/delay.h> |
41 | #include <time/delay.h> |
42 | #include <interrupt.h> |
42 | #include <interrupt.h> |
43 | #include <arch/interrupt.h> |
43 | #include <arch/interrupt.h> |
44 | #include <print.h> |
44 | #include <print.h> |
45 | #include <arch/asm.h> |
45 | #include <arch/asm.h> |
46 | #include <arch.h> |
46 | #include <arch.h> |
- | 47 | #include <ddi/irq.h> |
|
- | 48 | #include <ddi/device.h> |
|
47 | 49 | ||
48 | #ifdef CONFIG_SMP |
50 | #ifdef CONFIG_SMP |
49 | 51 | ||
50 | /* |
52 | /* |
51 | * Advanced Programmable Interrupt Controller for SMP systems. |
53 | * Advanced Programmable Interrupt Controller for SMP systems. |
52 | * Tested on: |
54 | * Tested on: |
53 | * Bochs 2.0.2 - Bochs 2.2.6 with 2-8 CPUs |
55 | * Bochs 2.0.2 - Bochs 2.2.6 with 2-8 CPUs |
54 | * Simics 2.0.28 - Simics 2.2.19 2-15 CPUs |
56 | * Simics 2.0.28 - Simics 2.2.19 2-15 CPUs |
55 | * VMware Workstation 5.5 with 2 CPUs |
57 | * VMware Workstation 5.5 with 2 CPUs |
56 | * QEMU 0.8.0 with 2-15 CPUs |
58 | * QEMU 0.8.0 with 2-15 CPUs |
57 | * ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs |
59 | * ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs |
58 | * ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs |
60 | * ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs |
59 | * MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs |
61 | * MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs |
60 | */ |
62 | */ |
61 | 63 | ||
62 | /* |
64 | /* |
63 | * These variables either stay configured as initilalized, or are changed by |
65 | * These variables either stay configured as initilalized, or are changed by |
64 | * the MP configuration code. |
66 | * the MP configuration code. |
65 | * |
67 | * |
66 | * Pay special attention to the volatile keyword. Without it, gcc -O2 would |
68 | * Pay special attention to the volatile keyword. Without it, gcc -O2 would |
67 | * optimize the code too much and accesses to l_apic and io_apic, that must |
69 | * optimize the code too much and accesses to l_apic and io_apic, that must |
68 | * always be 32-bit, would use byte oriented instructions. |
70 | * always be 32-bit, would use byte oriented instructions. |
69 | */ |
71 | */ |
70 | volatile uint32_t *l_apic = (uint32_t *) 0xfee00000; |
72 | volatile uint32_t *l_apic = (uint32_t *) 0xfee00000; |
71 | volatile uint32_t *io_apic = (uint32_t *) 0xfec00000; |
73 | volatile uint32_t *io_apic = (uint32_t *) 0xfec00000; |
72 | 74 | ||
73 | uint32_t apic_id_mask = 0; |
75 | uint32_t apic_id_mask = 0; |
- | 76 | static irq_t l_apic_timer_irq; |
|
74 | 77 | ||
75 | static int apic_poll_errors(void); |
78 | static int apic_poll_errors(void); |
76 | 79 | ||
77 | #ifdef LAPIC_VERBOSE |
80 | #ifdef LAPIC_VERBOSE |
78 | static char *delmod_str[] = { |
81 | static char *delmod_str[] = { |
79 | "Fixed", |
82 | "Fixed", |
80 | "Lowest Priority", |
83 | "Lowest Priority", |
81 | "SMI", |
84 | "SMI", |
82 | "Reserved", |
85 | "Reserved", |
83 | "NMI", |
86 | "NMI", |
84 | "INIT", |
87 | "INIT", |
85 | "STARTUP", |
88 | "STARTUP", |
86 | "ExtInt" |
89 | "ExtInt" |
87 | }; |
90 | }; |
88 | 91 | ||
89 | static char *destmod_str[] = { |
92 | static char *destmod_str[] = { |
90 | "Physical", |
93 | "Physical", |
91 | "Logical" |
94 | "Logical" |
92 | }; |
95 | }; |
93 | 96 | ||
94 | static char *trigmod_str[] = { |
97 | static char *trigmod_str[] = { |
95 | "Edge", |
98 | "Edge", |
96 | "Level" |
99 | "Level" |
97 | }; |
100 | }; |
98 | 101 | ||
99 | static char *mask_str[] = { |
102 | static char *mask_str[] = { |
100 | "Unmasked", |
103 | "Unmasked", |
101 | "Masked" |
104 | "Masked" |
102 | }; |
105 | }; |
103 | 106 | ||
104 | static char *delivs_str[] = { |
107 | static char *delivs_str[] = { |
105 | "Idle", |
108 | "Idle", |
106 | "Send Pending" |
109 | "Send Pending" |
107 | }; |
110 | }; |
108 | 111 | ||
109 | static char *tm_mode_str[] = { |
112 | static char *tm_mode_str[] = { |
110 | "One-shot", |
113 | "One-shot", |
111 | "Periodic" |
114 | "Periodic" |
112 | }; |
115 | }; |
113 | 116 | ||
114 | static char *intpol_str[] = { |
117 | static char *intpol_str[] = { |
115 | "Polarity High", |
118 | "Polarity High", |
116 | "Polarity Low" |
119 | "Polarity Low" |
117 | }; |
120 | }; |
118 | #endif /* LAPIC_VERBOSE */ |
121 | #endif /* LAPIC_VERBOSE */ |
119 | 122 | ||
- | 123 | /** APIC spurious interrupt handler. |
|
- | 124 | * |
|
- | 125 | * @param n Interrupt vector. |
|
- | 126 | * @param istate Interrupted state. |
|
- | 127 | */ |
|
- | 128 | static void apic_spurious(int n, istate_t *istate) |
|
- | 129 | { |
|
- | 130 | #ifdef CONFIG_DEBUG |
|
- | 131 | printf("cpu%d: APIC spurious interrupt\n", CPU->id); |
|
- | 132 | #endif |
|
- | 133 | } |
|
120 | 134 | ||
121 | static void apic_spurious(int n, istate_t *istate); |
135 | static irq_ownership_t l_apic_timer_claim(void) |
- | 136 | { |
|
- | 137 | return IRQ_ACCEPT; |
|
- | 138 | } |
|
- | 139 | ||
122 | static void l_apic_timer_interrupt(int n, istate_t *istate); |
140 | static void l_apic_timer_irq_handler(irq_t *irq, void *arg, ...) |
- | 141 | { |
|
- | 142 | clock(); |
|
- | 143 | } |
|
123 | 144 | ||
124 | /** Initialize APIC on BSP. */ |
145 | /** Initialize APIC on BSP. */ |
125 | void apic_init(void) |
146 | void apic_init(void) |
126 | { |
147 | { |
127 | io_apic_id_t idreg; |
148 | io_apic_id_t idreg; |
128 | int i; |
149 | int i; |
129 | 150 | ||
130 | exc_register(VECTOR_APIC_SPUR, "apic_spurious", (iroutine) apic_spurious); |
151 | exc_register(VECTOR_APIC_SPUR, "apic_spurious", (iroutine) apic_spurious); |
131 | 152 | ||
132 | enable_irqs_function = io_apic_enable_irqs; |
153 | enable_irqs_function = io_apic_enable_irqs; |
133 | disable_irqs_function = io_apic_disable_irqs; |
154 | disable_irqs_function = io_apic_disable_irqs; |
134 | eoi_function = l_apic_eoi; |
155 | eoi_function = l_apic_eoi; |
135 | 156 | ||
136 | /* |
157 | /* |
137 | * Configure interrupt routing. |
158 | * Configure interrupt routing. |
138 | * IRQ 0 remains masked as the time signal is generated by l_apic's themselves. |
159 | * IRQ 0 remains masked as the time signal is generated by l_apic's themselves. |
139 | * Other interrupts will be forwarded to the lowest priority CPU. |
160 | * Other interrupts will be forwarded to the lowest priority CPU. |
140 | */ |
161 | */ |
141 | io_apic_disable_irqs(0xffff); |
162 | io_apic_disable_irqs(0xffff); |
- | 163 | ||
- | 164 | irq_initialize(&l_apic_timer_irq); |
|
- | 165 | l_apic_timer_irq.devno = device_assign_devno(); |
|
- | 166 | l_apic_timer_irq.inr = IRQ_CLK; |
|
- | 167 | l_apic_timer_irq.claim = l_apic_timer_claim; |
|
142 | exc_register(VECTOR_CLK, "l_apic_timer", (iroutine) l_apic_timer_interrupt); |
168 | l_apic_timer_irq.handler = l_apic_timer_irq_handler; |
- | 169 | irq_register(&l_apic_timer_irq); |
|
- | 170 | ||
143 | for (i = 0; i < IRQ_COUNT; i++) { |
171 | for (i = 0; i < IRQ_COUNT; i++) { |
144 | int pin; |
172 | int pin; |
145 | 173 | ||
146 | if ((pin = smp_irq_to_pin(i)) != -1) { |
174 | if ((pin = smp_irq_to_pin(i)) != -1) |
147 | io_apic_change_ioredtbl(pin, DEST_ALL, IVT_IRQBASE+i, LOPRI); |
175 | io_apic_change_ioredtbl(pin, DEST_ALL, IVT_IRQBASE+i, LOPRI); |
148 | } |
176 | } |
149 | } |
- | |
150 | 177 | ||
151 | /* |
178 | /* |
152 | * Ensure that io_apic has unique ID. |
179 | * Ensure that io_apic has unique ID. |
153 | */ |
180 | */ |
154 | idreg.value = io_apic_read(IOAPICID); |
181 | idreg.value = io_apic_read(IOAPICID); |
155 | if ((1<<idreg.apic_id) & apic_id_mask) { /* see if IO APIC ID is used already */ |
182 | if ((1 << idreg.apic_id) & apic_id_mask) { /* see if IO APIC ID is used already */ |
156 | for (i = 0; i < APIC_ID_COUNT; i++) { |
183 | for (i = 0; i < APIC_ID_COUNT; i++) { |
157 | if (!((1<<i) & apic_id_mask)) { |
184 | if (!((1 << i) & apic_id_mask)) { |
158 | idreg.apic_id = i; |
185 | idreg.apic_id = i; |
159 | io_apic_write(IOAPICID, idreg.value); |
186 | io_apic_write(IOAPICID, idreg.value); |
160 | break; |
187 | break; |
161 | } |
188 | } |
162 | } |
189 | } |
163 | } |
190 | } |
164 | 191 | ||
165 | /* |
192 | /* |
166 | * Configure the BSP's lapic. |
193 | * Configure the BSP's lapic. |
167 | */ |
194 | */ |
168 | l_apic_init(); |
195 | l_apic_init(); |
169 | 196 | ||
170 | l_apic_debug(); |
197 | l_apic_debug(); |
171 | } |
198 | } |
172 | 199 | ||
173 | /** APIC spurious interrupt handler. |
- | |
174 | * |
- | |
175 | * @param n Interrupt vector. |
- | |
176 | * @param istate Interrupted state. |
- | |
177 | */ |
- | |
178 | void apic_spurious(int n, istate_t *istate) |
- | |
179 | { |
- | |
180 | #ifdef CONFIG_DEBUG |
- | |
181 | printf("cpu%d: APIC spurious interrupt\n", CPU->id); |
- | |
182 | #endif |
- | |
183 | } |
- | |
184 | - | ||
185 | /** Poll for APIC errors. |
200 | /** Poll for APIC errors. |
186 | * |
201 | * |
187 | * Examine Error Status Register and report all errors found. |
202 | * Examine Error Status Register and report all errors found. |
188 | * |
203 | * |
189 | * @return 0 on error, 1 on success. |
204 | * @return 0 on error, 1 on success. |
190 | */ |
205 | */ |
191 | int apic_poll_errors(void) |
206 | int apic_poll_errors(void) |
192 | { |
207 | { |
193 | esr_t esr; |
208 | esr_t esr; |
194 | 209 | ||
195 | esr.value = l_apic[ESR]; |
210 | esr.value = l_apic[ESR]; |
196 | 211 | ||
197 | if (esr.send_checksum_error) |
212 | if (esr.send_checksum_error) |
198 | printf("Send Checksum Error\n"); |
213 | printf("Send Checksum Error\n"); |
199 | if (esr.receive_checksum_error) |
214 | if (esr.receive_checksum_error) |
200 | printf("Receive Checksum Error\n"); |
215 | printf("Receive Checksum Error\n"); |
201 | if (esr.send_accept_error) |
216 | if (esr.send_accept_error) |
202 | printf("Send Accept Error\n"); |
217 | printf("Send Accept Error\n"); |
203 | if (esr.receive_accept_error) |
218 | if (esr.receive_accept_error) |
204 | printf("Receive Accept Error\n"); |
219 | printf("Receive Accept Error\n"); |
205 | if (esr.send_illegal_vector) |
220 | if (esr.send_illegal_vector) |
206 | printf("Send Illegal Vector\n"); |
221 | printf("Send Illegal Vector\n"); |
207 | if (esr.received_illegal_vector) |
222 | if (esr.received_illegal_vector) |
208 | printf("Received Illegal Vector\n"); |
223 | printf("Received Illegal Vector\n"); |
209 | if (esr.illegal_register_address) |
224 | if (esr.illegal_register_address) |
210 | printf("Illegal Register Address\n"); |
225 | printf("Illegal Register Address\n"); |
211 | 226 | ||
212 | return !esr.err_bitmap; |
227 | return !esr.err_bitmap; |
213 | } |
228 | } |
214 | 229 | ||
215 | /** Send all CPUs excluding CPU IPI vector. |
230 | /** Send all CPUs excluding CPU IPI vector. |
216 | * |
231 | * |
217 | * @param vector Interrupt vector to be sent. |
232 | * @param vector Interrupt vector to be sent. |
218 | * |
233 | * |
219 | * @return 0 on failure, 1 on success. |
234 | * @return 0 on failure, 1 on success. |
220 | */ |
235 | */ |
221 | int l_apic_broadcast_custom_ipi(uint8_t vector) |
236 | int l_apic_broadcast_custom_ipi(uint8_t vector) |
222 | { |
237 | { |
223 | icr_t icr; |
238 | icr_t icr; |
224 | 239 | ||
225 | icr.lo = l_apic[ICRlo]; |
240 | icr.lo = l_apic[ICRlo]; |
226 | icr.delmod = DELMOD_FIXED; |
241 | icr.delmod = DELMOD_FIXED; |
227 | icr.destmod = DESTMOD_LOGIC; |
242 | icr.destmod = DESTMOD_LOGIC; |
228 | icr.level = LEVEL_ASSERT; |
243 | icr.level = LEVEL_ASSERT; |
229 | icr.shorthand = SHORTHAND_ALL_EXCL; |
244 | icr.shorthand = SHORTHAND_ALL_EXCL; |
230 | icr.trigger_mode = TRIGMOD_LEVEL; |
245 | icr.trigger_mode = TRIGMOD_LEVEL; |
231 | icr.vector = vector; |
246 | icr.vector = vector; |
232 | 247 | ||
233 | l_apic[ICRlo] = icr.lo; |
248 | l_apic[ICRlo] = icr.lo; |
234 | 249 | ||
235 | icr.lo = l_apic[ICRlo]; |
250 | icr.lo = l_apic[ICRlo]; |
236 | if (icr.delivs == DELIVS_PENDING) { |
251 | if (icr.delivs == DELIVS_PENDING) { |
237 | #ifdef CONFIG_DEBUG |
252 | #ifdef CONFIG_DEBUG |
238 | printf("IPI is pending.\n"); |
253 | printf("IPI is pending.\n"); |
239 | #endif |
254 | #endif |
240 | } |
255 | } |
241 | 256 | ||
242 | return apic_poll_errors(); |
257 | return apic_poll_errors(); |
243 | } |
258 | } |
244 | 259 | ||
245 | /** Universal Start-up Algorithm for bringing up the AP processors. |
260 | /** Universal Start-up Algorithm for bringing up the AP processors. |
246 | * |
261 | * |
247 | * @param apicid APIC ID of the processor to be brought up. |
262 | * @param apicid APIC ID of the processor to be brought up. |
248 | * |
263 | * |
249 | * @return 0 on failure, 1 on success. |
264 | * @return 0 on failure, 1 on success. |
250 | */ |
265 | */ |
251 | int l_apic_send_init_ipi(uint8_t apicid) |
266 | int l_apic_send_init_ipi(uint8_t apicid) |
252 | { |
267 | { |
253 | icr_t icr; |
268 | icr_t icr; |
254 | int i; |
269 | int i; |
255 | 270 | ||
256 | /* |
271 | /* |
257 | * Read the ICR register in and zero all non-reserved fields. |
272 | * Read the ICR register in and zero all non-reserved fields. |
258 | */ |
273 | */ |
259 | icr.lo = l_apic[ICRlo]; |
274 | icr.lo = l_apic[ICRlo]; |
260 | icr.hi = l_apic[ICRhi]; |
275 | icr.hi = l_apic[ICRhi]; |
261 | 276 | ||
262 | icr.delmod = DELMOD_INIT; |
277 | icr.delmod = DELMOD_INIT; |
263 | icr.destmod = DESTMOD_PHYS; |
278 | icr.destmod = DESTMOD_PHYS; |
264 | icr.level = LEVEL_ASSERT; |
279 | icr.level = LEVEL_ASSERT; |
265 | icr.trigger_mode = TRIGMOD_LEVEL; |
280 | icr.trigger_mode = TRIGMOD_LEVEL; |
266 | icr.shorthand = SHORTHAND_NONE; |
281 | icr.shorthand = SHORTHAND_NONE; |
267 | icr.vector = 0; |
282 | icr.vector = 0; |
268 | icr.dest = apicid; |
283 | icr.dest = apicid; |
269 | 284 | ||
270 | l_apic[ICRhi] = icr.hi; |
285 | l_apic[ICRhi] = icr.hi; |
271 | l_apic[ICRlo] = icr.lo; |
286 | l_apic[ICRlo] = icr.lo; |
272 | 287 | ||
273 | /* |
288 | /* |
274 | * According to MP Specification, 20us should be enough to |
289 | * According to MP Specification, 20us should be enough to |
275 | * deliver the IPI. |
290 | * deliver the IPI. |
276 | */ |
291 | */ |
277 | delay(20); |
292 | delay(20); |
278 | 293 | ||
279 | if (!apic_poll_errors()) |
294 | if (!apic_poll_errors()) |
280 | return 0; |
295 | return 0; |
281 | 296 | ||
282 | icr.lo = l_apic[ICRlo]; |
297 | icr.lo = l_apic[ICRlo]; |
283 | if (icr.delivs == DELIVS_PENDING) { |
298 | if (icr.delivs == DELIVS_PENDING) { |
284 | #ifdef CONFIG_DEBUG |
299 | #ifdef CONFIG_DEBUG |
285 | printf("IPI is pending.\n"); |
300 | printf("IPI is pending.\n"); |
286 | #endif |
301 | #endif |
287 | } |
302 | } |
288 | 303 | ||
289 | icr.delmod = DELMOD_INIT; |
304 | icr.delmod = DELMOD_INIT; |
290 | icr.destmod = DESTMOD_PHYS; |
305 | icr.destmod = DESTMOD_PHYS; |
291 | icr.level = LEVEL_DEASSERT; |
306 | icr.level = LEVEL_DEASSERT; |
292 | icr.shorthand = SHORTHAND_NONE; |
307 | icr.shorthand = SHORTHAND_NONE; |
293 | icr.trigger_mode = TRIGMOD_LEVEL; |
308 | icr.trigger_mode = TRIGMOD_LEVEL; |
294 | icr.vector = 0; |
309 | icr.vector = 0; |
295 | l_apic[ICRlo] = icr.lo; |
310 | l_apic[ICRlo] = icr.lo; |
296 | 311 | ||
297 | /* |
312 | /* |
298 | * Wait 10ms as MP Specification specifies. |
313 | * Wait 10ms as MP Specification specifies. |
299 | */ |
314 | */ |
300 | delay(10000); |
315 | delay(10000); |
301 | 316 | ||
302 | if (!is_82489DX_apic(l_apic[LAVR])) { |
317 | if (!is_82489DX_apic(l_apic[LAVR])) { |
303 | /* |
318 | /* |
304 | * If this is not 82489DX-based l_apic we must send two STARTUP IPI's. |
319 | * If this is not 82489DX-based l_apic we must send two STARTUP IPI's. |
305 | */ |
320 | */ |
306 | for (i = 0; i<2; i++) { |
321 | for (i = 0; i<2; i++) { |
307 | icr.lo = l_apic[ICRlo]; |
322 | icr.lo = l_apic[ICRlo]; |
308 | icr.vector = ((uintptr_t) ap_boot) / 4096; /* calculate the reset vector */ |
323 | icr.vector = ((uintptr_t) ap_boot) / 4096; /* calculate the reset vector */ |
309 | icr.delmod = DELMOD_STARTUP; |
324 | icr.delmod = DELMOD_STARTUP; |
310 | icr.destmod = DESTMOD_PHYS; |
325 | icr.destmod = DESTMOD_PHYS; |
311 | icr.level = LEVEL_ASSERT; |
326 | icr.level = LEVEL_ASSERT; |
312 | icr.shorthand = SHORTHAND_NONE; |
327 | icr.shorthand = SHORTHAND_NONE; |
313 | icr.trigger_mode = TRIGMOD_LEVEL; |
328 | icr.trigger_mode = TRIGMOD_LEVEL; |
314 | l_apic[ICRlo] = icr.lo; |
329 | l_apic[ICRlo] = icr.lo; |
315 | delay(200); |
330 | delay(200); |
316 | } |
331 | } |
317 | } |
332 | } |
318 | 333 | ||
319 | return apic_poll_errors(); |
334 | return apic_poll_errors(); |
320 | } |
335 | } |
321 | 336 | ||
322 | /** Initialize Local APIC. */ |
337 | /** Initialize Local APIC. */ |
323 | void l_apic_init(void) |
338 | void l_apic_init(void) |
324 | { |
339 | { |
325 | lvt_error_t error; |
340 | lvt_error_t error; |
326 | lvt_lint_t lint; |
341 | lvt_lint_t lint; |
327 | tpr_t tpr; |
342 | tpr_t tpr; |
328 | svr_t svr; |
343 | svr_t svr; |
329 | icr_t icr; |
344 | icr_t icr; |
330 | tdcr_t tdcr; |
345 | tdcr_t tdcr; |
331 | lvt_tm_t tm; |
346 | lvt_tm_t tm; |
332 | ldr_t ldr; |
347 | ldr_t ldr; |
333 | dfr_t dfr; |
348 | dfr_t dfr; |
334 | uint32_t t1, t2; |
349 | uint32_t t1, t2; |
335 | 350 | ||
336 | /* Initialize LVT Error register. */ |
351 | /* Initialize LVT Error register. */ |
337 | error.value = l_apic[LVT_Err]; |
352 | error.value = l_apic[LVT_Err]; |
338 | error.masked = true; |
353 | error.masked = true; |
339 | l_apic[LVT_Err] = error.value; |
354 | l_apic[LVT_Err] = error.value; |
340 | 355 | ||
341 | /* Initialize LVT LINT0 register. */ |
356 | /* Initialize LVT LINT0 register. */ |
342 | lint.value = l_apic[LVT_LINT0]; |
357 | lint.value = l_apic[LVT_LINT0]; |
343 | lint.masked = true; |
358 | lint.masked = true; |
344 | l_apic[LVT_LINT0] = lint.value; |
359 | l_apic[LVT_LINT0] = lint.value; |
345 | 360 | ||
346 | /* Initialize LVT LINT1 register. */ |
361 | /* Initialize LVT LINT1 register. */ |
347 | lint.value = l_apic[LVT_LINT1]; |
362 | lint.value = l_apic[LVT_LINT1]; |
348 | lint.masked = true; |
363 | lint.masked = true; |
349 | l_apic[LVT_LINT1] = lint.value; |
364 | l_apic[LVT_LINT1] = lint.value; |
350 | 365 | ||
351 | /* Task Priority Register initialization. */ |
366 | /* Task Priority Register initialization. */ |
352 | tpr.value = l_apic[TPR]; |
367 | tpr.value = l_apic[TPR]; |
353 | tpr.pri_sc = 0; |
368 | tpr.pri_sc = 0; |
354 | tpr.pri = 0; |
369 | tpr.pri = 0; |
355 | l_apic[TPR] = tpr.value; |
370 | l_apic[TPR] = tpr.value; |
356 | 371 | ||
357 | /* Spurious-Interrupt Vector Register initialization. */ |
372 | /* Spurious-Interrupt Vector Register initialization. */ |
358 | svr.value = l_apic[SVR]; |
373 | svr.value = l_apic[SVR]; |
359 | svr.vector = VECTOR_APIC_SPUR; |
374 | svr.vector = VECTOR_APIC_SPUR; |
360 | svr.lapic_enabled = true; |
375 | svr.lapic_enabled = true; |
361 | svr.focus_checking = true; |
376 | svr.focus_checking = true; |
362 | l_apic[SVR] = svr.value; |
377 | l_apic[SVR] = svr.value; |
363 | 378 | ||
364 | if (CPU->arch.family >= 6) |
379 | if (CPU->arch.family >= 6) |
365 | enable_l_apic_in_msr(); |
380 | enable_l_apic_in_msr(); |
366 | 381 | ||
367 | /* Interrupt Command Register initialization. */ |
382 | /* Interrupt Command Register initialization. */ |
368 | icr.lo = l_apic[ICRlo]; |
383 | icr.lo = l_apic[ICRlo]; |
369 | icr.delmod = DELMOD_INIT; |
384 | icr.delmod = DELMOD_INIT; |
370 | icr.destmod = DESTMOD_PHYS; |
385 | icr.destmod = DESTMOD_PHYS; |
371 | icr.level = LEVEL_DEASSERT; |
386 | icr.level = LEVEL_DEASSERT; |
372 | icr.shorthand = SHORTHAND_ALL_INCL; |
387 | icr.shorthand = SHORTHAND_ALL_INCL; |
373 | icr.trigger_mode = TRIGMOD_LEVEL; |
388 | icr.trigger_mode = TRIGMOD_LEVEL; |
374 | l_apic[ICRlo] = icr.lo; |
389 | l_apic[ICRlo] = icr.lo; |
375 | 390 | ||
376 | /* Timer Divide Configuration Register initialization. */ |
391 | /* Timer Divide Configuration Register initialization. */ |
377 | tdcr.value = l_apic[TDCR]; |
392 | tdcr.value = l_apic[TDCR]; |
378 | tdcr.div_value = DIVIDE_1; |
393 | tdcr.div_value = DIVIDE_1; |
379 | l_apic[TDCR] = tdcr.value; |
394 | l_apic[TDCR] = tdcr.value; |
380 | 395 | ||
381 | /* Program local timer. */ |
396 | /* Program local timer. */ |
382 | tm.value = l_apic[LVT_Tm]; |
397 | tm.value = l_apic[LVT_Tm]; |
383 | tm.vector = VECTOR_CLK; |
398 | tm.vector = VECTOR_CLK; |
384 | tm.mode = TIMER_PERIODIC; |
399 | tm.mode = TIMER_PERIODIC; |
385 | tm.masked = false; |
400 | tm.masked = false; |
386 | l_apic[LVT_Tm] = tm.value; |
401 | l_apic[LVT_Tm] = tm.value; |
387 | 402 | ||
388 | /* |
403 | /* |
389 | * Measure and configure the timer to generate timer |
404 | * Measure and configure the timer to generate timer |
390 | * interrupt with period 1s/HZ seconds. |
405 | * interrupt with period 1s/HZ seconds. |
391 | */ |
406 | */ |
392 | t1 = l_apic[CCRT]; |
407 | t1 = l_apic[CCRT]; |
393 | l_apic[ICRT] = 0xffffffff; |
408 | l_apic[ICRT] = 0xffffffff; |
394 | 409 | ||
395 | while (l_apic[CCRT] == t1) |
410 | while (l_apic[CCRT] == t1) |
396 | ; |
411 | ; |
397 | 412 | ||
398 | t1 = l_apic[CCRT]; |
413 | t1 = l_apic[CCRT]; |
399 | delay(1000000/HZ); |
414 | delay(1000000/HZ); |
400 | t2 = l_apic[CCRT]; |
415 | t2 = l_apic[CCRT]; |
401 | 416 | ||
402 | l_apic[ICRT] = t1-t2; |
417 | l_apic[ICRT] = t1-t2; |
403 | 418 | ||
404 | /* Program Logical Destination Register. */ |
419 | /* Program Logical Destination Register. */ |
405 | ldr.value = l_apic[LDR]; |
420 | ldr.value = l_apic[LDR]; |
406 | if (CPU->id < sizeof(CPU->id)*8) /* size in bits */ |
421 | if (CPU->id < sizeof(CPU->id)*8) /* size in bits */ |
407 | ldr.id = (1<<CPU->id); |
422 | ldr.id = (1<<CPU->id); |
408 | l_apic[LDR] = ldr.value; |
423 | l_apic[LDR] = ldr.value; |
409 | 424 | ||
410 | /* Program Destination Format Register for Flat mode. */ |
425 | /* Program Destination Format Register for Flat mode. */ |
411 | dfr.value = l_apic[DFR]; |
426 | dfr.value = l_apic[DFR]; |
412 | dfr.model = MODEL_FLAT; |
427 | dfr.model = MODEL_FLAT; |
413 | l_apic[DFR] = dfr.value; |
428 | l_apic[DFR] = dfr.value; |
414 | } |
429 | } |
415 | 430 | ||
416 | /** Local APIC End of Interrupt. */ |
431 | /** Local APIC End of Interrupt. */ |
417 | void l_apic_eoi(void) |
432 | void l_apic_eoi(void) |
418 | { |
433 | { |
419 | l_apic[EOI] = 0; |
434 | l_apic[EOI] = 0; |
420 | } |
435 | } |
421 | 436 | ||
422 | /** Dump content of Local APIC registers. */ |
437 | /** Dump content of Local APIC registers. */ |
423 | void l_apic_debug(void) |
438 | void l_apic_debug(void) |
424 | { |
439 | { |
425 | #ifdef LAPIC_VERBOSE |
440 | #ifdef LAPIC_VERBOSE |
426 | lvt_tm_t tm; |
441 | lvt_tm_t tm; |
427 | lvt_lint_t lint; |
442 | lvt_lint_t lint; |
428 | lvt_error_t error; |
443 | lvt_error_t error; |
429 | 444 | ||
430 | printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id()); |
445 | printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id()); |
431 | 446 | ||
432 | tm.value = l_apic[LVT_Tm]; |
447 | tm.value = l_apic[LVT_Tm]; |
433 | printf("LVT Tm: vector=%hhd, %s, %s, %s\n", tm.vector, delivs_str[tm.delivs], mask_str[tm.masked], tm_mode_str[tm.mode]); |
448 | printf("LVT Tm: vector=%hhd, %s, %s, %s\n", tm.vector, delivs_str[tm.delivs], mask_str[tm.masked], tm_mode_str[tm.mode]); |
434 | lint.value = l_apic[LVT_LINT0]; |
449 | lint.value = l_apic[LVT_LINT0]; |
435 | printf("LVT LINT0: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]); |
450 | printf("LVT LINT0: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]); |
436 | lint.value = l_apic[LVT_LINT1]; |
451 | lint.value = l_apic[LVT_LINT1]; |
437 | printf("LVT LINT1: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]); |
452 | printf("LVT LINT1: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]); |
438 | error.value = l_apic[LVT_Err]; |
453 | error.value = l_apic[LVT_Err]; |
439 | printf("LVT Err: vector=%hhd, %s, %s\n", error.vector, delivs_str[error.delivs], mask_str[error.masked]); |
454 | printf("LVT Err: vector=%hhd, %s, %s\n", error.vector, delivs_str[error.delivs], mask_str[error.masked]); |
440 | #endif |
455 | #endif |
441 | } |
456 | } |
442 | - | ||
443 | /** Local APIC Timer Interrupt. |
- | |
444 | * |
- | |
445 | * @param n Interrupt vector number. |
- | |
446 | * @param istate Interrupted state. |
- | |
447 | */ |
- | |
448 | void l_apic_timer_interrupt(int n, istate_t *istate) |
- | |
449 | { |
- | |
450 | l_apic_eoi(); |
- | |
451 | clock(); |
- | |
452 | } |
- | |
453 | 457 | ||
454 | /** Get Local APIC ID. |
458 | /** Get Local APIC ID. |
455 | * |
459 | * |
456 | * @return Local APIC ID. |
460 | * @return Local APIC ID. |
457 | */ |
461 | */ |
458 | uint8_t l_apic_id(void) |
462 | uint8_t l_apic_id(void) |
459 | { |
463 | { |
460 | l_apic_id_t idreg; |
464 | l_apic_id_t idreg; |
461 | 465 | ||
462 | idreg.value = l_apic[L_APIC_ID]; |
466 | idreg.value = l_apic[L_APIC_ID]; |
463 | return idreg.apic_id; |
467 | return idreg.apic_id; |
464 | } |
468 | } |
465 | 469 | ||
466 | /** Read from IO APIC register. |
470 | /** Read from IO APIC register. |
467 | * |
471 | * |
468 | * @param address IO APIC register address. |
472 | * @param address IO APIC register address. |
469 | * |
473 | * |
470 | * @return Content of the addressed IO APIC register. |
474 | * @return Content of the addressed IO APIC register. |
471 | */ |
475 | */ |
472 | uint32_t io_apic_read(uint8_t address) |
476 | uint32_t io_apic_read(uint8_t address) |
473 | { |
477 | { |
474 | io_regsel_t regsel; |
478 | io_regsel_t regsel; |
475 | 479 | ||
476 | regsel.value = io_apic[IOREGSEL]; |
480 | regsel.value = io_apic[IOREGSEL]; |
477 | regsel.reg_addr = address; |
481 | regsel.reg_addr = address; |
478 | io_apic[IOREGSEL] = regsel.value; |
482 | io_apic[IOREGSEL] = regsel.value; |
479 | return io_apic[IOWIN]; |
483 | return io_apic[IOWIN]; |
480 | } |
484 | } |
481 | 485 | ||
482 | /** Write to IO APIC register. |
486 | /** Write to IO APIC register. |
483 | * |
487 | * |
484 | * @param address IO APIC register address. |
488 | * @param address IO APIC register address. |
485 | * @param x Content to be written to the addressed IO APIC register. |
489 | * @param x Content to be written to the addressed IO APIC register. |
486 | */ |
490 | */ |
487 | void io_apic_write(uint8_t address, uint32_t x) |
491 | void io_apic_write(uint8_t address, uint32_t x) |
488 | { |
492 | { |
489 | io_regsel_t regsel; |
493 | io_regsel_t regsel; |
490 | 494 | ||
491 | regsel.value = io_apic[IOREGSEL]; |
495 | regsel.value = io_apic[IOREGSEL]; |
492 | regsel.reg_addr = address; |
496 | regsel.reg_addr = address; |
493 | io_apic[IOREGSEL] = regsel.value; |
497 | io_apic[IOREGSEL] = regsel.value; |
494 | io_apic[IOWIN] = x; |
498 | io_apic[IOWIN] = x; |
495 | } |
499 | } |
496 | 500 | ||
497 | /** Change some attributes of one item in I/O Redirection Table. |
501 | /** Change some attributes of one item in I/O Redirection Table. |
498 | * |
502 | * |
499 | * @param pin IO APIC pin number. |
503 | * @param pin IO APIC pin number. |
500 | * @param dest Interrupt destination address. |
504 | * @param dest Interrupt destination address. |
501 | * @param v Interrupt vector to trigger. |
505 | * @param v Interrupt vector to trigger. |
502 | * @param flags Flags. |
506 | * @param flags Flags. |
503 | */ |
507 | */ |
504 | void io_apic_change_ioredtbl(int pin, int dest, uint8_t v, int flags) |
508 | void io_apic_change_ioredtbl(int pin, int dest, uint8_t v, int flags) |
505 | { |
509 | { |
506 | io_redirection_reg_t reg; |
510 | io_redirection_reg_t reg; |
507 | int dlvr = DELMOD_FIXED; |
511 | int dlvr = DELMOD_FIXED; |
508 | 512 | ||
509 | if (flags & LOPRI) |
513 | if (flags & LOPRI) |
510 | dlvr = DELMOD_LOWPRI; |
514 | dlvr = DELMOD_LOWPRI; |
511 | 515 | ||
512 | reg.lo = io_apic_read(IOREDTBL + pin*2); |
516 | reg.lo = io_apic_read(IOREDTBL + pin*2); |
513 | reg.hi = io_apic_read(IOREDTBL + pin*2 + 1); |
517 | reg.hi = io_apic_read(IOREDTBL + pin*2 + 1); |
514 | 518 | ||
515 | reg.dest = dest; |
519 | reg.dest = dest; |
516 | reg.destmod = DESTMOD_LOGIC; |
520 | reg.destmod = DESTMOD_LOGIC; |
517 | reg.trigger_mode = TRIGMOD_EDGE; |
521 | reg.trigger_mode = TRIGMOD_EDGE; |
518 | reg.intpol = POLARITY_HIGH; |
522 | reg.intpol = POLARITY_HIGH; |
519 | reg.delmod = dlvr; |
523 | reg.delmod = dlvr; |
520 | reg.intvec = v; |
524 | reg.intvec = v; |
521 | 525 | ||
522 | io_apic_write(IOREDTBL + pin*2, reg.lo); |
526 | io_apic_write(IOREDTBL + pin*2, reg.lo); |
523 | io_apic_write(IOREDTBL + pin*2 + 1, reg.hi); |
527 | io_apic_write(IOREDTBL + pin*2 + 1, reg.hi); |
524 | } |
528 | } |
525 | 529 | ||
526 | /** Mask IRQs in IO APIC. |
530 | /** Mask IRQs in IO APIC. |
527 | * |
531 | * |
528 | * @param irqmask Bitmask of IRQs to be masked (0 = do not mask, 1 = mask). |
532 | * @param irqmask Bitmask of IRQs to be masked (0 = do not mask, 1 = mask). |
529 | */ |
533 | */ |
530 | void io_apic_disable_irqs(uint16_t irqmask) |
534 | void io_apic_disable_irqs(uint16_t irqmask) |
531 | { |
535 | { |
532 | io_redirection_reg_t reg; |
536 | io_redirection_reg_t reg; |
533 | int i, pin; |
537 | int i, pin; |
534 | 538 | ||
535 | for (i=0;i<16;i++) { |
539 | for (i=0;i<16;i++) { |
536 | if (irqmask & (1<<i)) { |
540 | if (irqmask & (1<<i)) { |
537 | /* |
541 | /* |
538 | * Mask the signal input in IO APIC if there is a |
542 | * Mask the signal input in IO APIC if there is a |
539 | * mapping for the respective IRQ number. |
543 | * mapping for the respective IRQ number. |
540 | */ |
544 | */ |
541 | pin = smp_irq_to_pin(i); |
545 | pin = smp_irq_to_pin(i); |
542 | if (pin != -1) { |
546 | if (pin != -1) { |
543 | reg.lo = io_apic_read(IOREDTBL + pin*2); |
547 | reg.lo = io_apic_read(IOREDTBL + pin*2); |
544 | reg.masked = true; |
548 | reg.masked = true; |
545 | io_apic_write(IOREDTBL + pin*2, reg.lo); |
549 | io_apic_write(IOREDTBL + pin*2, reg.lo); |
546 | } |
550 | } |
547 | 551 | ||
548 | } |
552 | } |
549 | } |
553 | } |
550 | } |
554 | } |
551 | 555 | ||
552 | /** Unmask IRQs in IO APIC. |
556 | /** Unmask IRQs in IO APIC. |
553 | * |
557 | * |
554 | * @param irqmask Bitmask of IRQs to be unmasked (0 = do not unmask, 1 = unmask). |
558 | * @param irqmask Bitmask of IRQs to be unmasked (0 = do not unmask, 1 = unmask). |
555 | */ |
559 | */ |
556 | void io_apic_enable_irqs(uint16_t irqmask) |
560 | void io_apic_enable_irqs(uint16_t irqmask) |
557 | { |
561 | { |
558 | int i, pin; |
562 | int i, pin; |
559 | io_redirection_reg_t reg; |
563 | io_redirection_reg_t reg; |
560 | 564 | ||
561 | for (i=0;i<16;i++) { |
565 | for (i=0;i<16;i++) { |
562 | if (irqmask & (1<<i)) { |
566 | if (irqmask & (1<<i)) { |
563 | /* |
567 | /* |
564 | * Unmask the signal input in IO APIC if there is a |
568 | * Unmask the signal input in IO APIC if there is a |
565 | * mapping for the respective IRQ number. |
569 | * mapping for the respective IRQ number. |
566 | */ |
570 | */ |
567 | pin = smp_irq_to_pin(i); |
571 | pin = smp_irq_to_pin(i); |
568 | if (pin != -1) { |
572 | if (pin != -1) { |
569 | reg.lo = io_apic_read(IOREDTBL + pin*2); |
573 | reg.lo = io_apic_read(IOREDTBL + pin*2); |
570 | reg.masked = false; |
574 | reg.masked = false; |
571 | io_apic_write(IOREDTBL + pin*2, reg.lo); |
575 | io_apic_write(IOREDTBL + pin*2, reg.lo); |
572 | } |
576 | } |
573 | 577 | ||
574 | } |
578 | } |
575 | } |
579 | } |
576 | } |
580 | } |
577 | 581 | ||
578 | #endif /* CONFIG_SMP */ |
582 | #endif /* CONFIG_SMP */ |
579 | 583 | ||
580 | /** @} |
584 | /** @} |
581 | */ |
585 | */ |
582 | 586 |