WebSVN – HelenOS – Diff – /trunk/kernel/arch/ia32/src/smp/apic.c


/*
 * Copyright (C) 2001-2004 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#include <arch/types.h>
#include <arch/smp/apic.h>
#include <arch/smp/ap.h>
#include <arch/smp/mps.h>
#include <arch/boot/boot.h>
#include <mm/page.h>
#include <time/delay.h>
#include <interrupt.h>
#include <arch/interrupt.h>
#include <print.h>
#include <arch/asm.h>
#include <arch.h>
 
#ifdef CONFIG_SMP
 
/*
 * Advanced Programmable Interrupt Controller for SMP systems.
 * Tested on:
 *  Bochs 2.0.2 - Bochs 2.2.6 with 2-8 CPUs
 *  Simics 2.0.28 - Simics 2.2.19 2-15 CPUs
 *  VMware Workstation 5.5 with 2 CPUs
 *  ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs
 *  ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs
 *  MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs
 */
 
/*
 * These variables either stay configured as initilalized, or are changed by
 * the MP configuration code.
 *
 * Pay special attention to the volatile keyword. Without it, gcc -O2 would
 * optimize the code too much and accesses to l_apic and io_apic, that must
 * always be 32-bit, would use byte oriented instructions.
 */
volatile __u32 *l_apic = (__u32 *) 0xfee00000;
volatile __u32 *io_apic = (__u32 *) 0xfec00000;
 
__u32 apic_id_mask = 0;
 
static int apic_poll_errors(void);
 
#ifdef LAPIC_VERBOSE
static char *delmod_str[] = {
    "Fixed",
    "Lowest Priority",
    "SMI",
    "Reserved",
    "NMI",
    "INIT",
    "STARTUP",
    "ExtInt"
};
 
static char *destmod_str[] = {
    "Physical",
    "Logical"
};
 
static char *trigmod_str[] = {
    "Edge",
    "Level"
};
 
static char *mask_str[] = {
    "Unmasked",
    "Masked"
};
 
static char *delivs_str[] = {
    "Idle",
    "Send Pending"
};
 
static char *tm_mode_str[] = {
    "One-shot",
    "Periodic"
};
 
static char *intpol_str[] = {
    "Polarity High",
    "Polarity Low"
};
#endif /* LAPIC_VERBOSE */
 
 
static void apic_spurious(int n, void *stack);
static void l_apic_timer_interrupt(int n, void *stack);
 
/** Initialize APIC on BSP. */
void apic_init(void)
{
    io_apic_id_t idreg;
    int i;
 
    exc_register(VECTOR_APIC_SPUR, "apic_spurious", apic_spurious);
 
    enable_irqs_function = io_apic_enable_irqs;
    disable_irqs_function = io_apic_disable_irqs;
    eoi_function = l_apic_eoi;
   
    /*
     * Configure interrupt routing.
     * IRQ 0 remains masked as the time signal is generated by l_apic's themselves.
     * Other interrupts will be forwarded to the lowest priority CPU.
     */
    io_apic_disable_irqs(0xffff);
    exc_register(VECTOR_CLK, "l_apic_timer", l_apic_timer_interrupt);
    for (i = 0; i < IRQ_COUNT; i++) {
        int pin;
   
        if ((pin = smp_irq_to_pin(i)) != -1) {
            io_apic_change_ioredtbl(pin, DEST_ALL, IVT_IRQBASE+i, LOPRI);
        }
    }
   
    /*
     * Ensure that io_apic has unique ID.
     */
    idreg.value = io_apic_read(IOAPICID);
    if ((1<<idreg.apic_id) & apic_id_mask) {    /* see if IO APIC ID is used already */
        for (i = 0; i < APIC_ID_COUNT; i++) {
            if (!((1<<i) & apic_id_mask)) {
                idreg.apic_id = i;
                io_apic_write(IOAPICID, idreg.value);
                break;
            }
        }
    }
 
    /*
     * Configure the BSP's lapic.
     */
    l_apic_init();
 
    l_apic_debug();
}
 
/** APIC spurious interrupt handler.
 *
 * @param n Interrupt vector.
 * @param stack Interrupted stack.
 */
void apic_spurious(int n, void *stack)
{
    printf("cpu%d: APIC spurious interrupt\n", CPU->id);
}
 
/** Poll for APIC errors.
 *
 * Examine Error Status Register and report all errors found.
 *
 * @return 0 on error, 1 on success.
 */
int apic_poll_errors(void)
{
    esr_t esr;
   
    esr.value = l_apic[ESR];
   
    if (esr.send_checksum_error)
        printf("Send Checksum Error\n");
    if (esr.receive_checksum_error)
        printf("Receive Checksum Error\n");
    if (esr.send_accept_error)
        printf("Send Accept Error\n");
    if (esr.receive_accept_error)
        printf("Receive Accept Error\n");
    if (esr.send_illegal_vector)
        printf("Send Illegal Vector\n");
    if (esr.received_illegal_vector)
        printf("Received Illegal Vector\n");
    if (esr.illegal_register_address)
        printf("Illegal Register Address\n");
 
    return !esr.err_bitmap;
}
 
/** Send all CPUs excluding CPU IPI vector.
 *
 * @param vector Interrupt vector to be sent.
 *
 * @return 0 on failure, 1 on success.
 */
int l_apic_broadcast_custom_ipi(__u8 vector)
{
    icr_t icr;
 
    icr.lo = l_apic[ICRlo];
    icr.delmod = DELMOD_FIXED;
    icr.destmod = DESTMOD_LOGIC;
    icr.level = LEVEL_ASSERT;
    icr.shorthand = SHORTHAND_ALL_EXCL;
    icr.trigger_mode = TRIGMOD_LEVEL;
    icr.vector = vector;
 
    l_apic[ICRlo] = icr.lo;
 
    icr.lo = l_apic[ICRlo];
    if (icr.delivs == DELIVS_PENDING)
        printf("IPI is pending.\n");
 
    return apic_poll_errors();
}
 
/** Universal Start-up Algorithm for bringing up the AP processors.
 *
 * @param apicid APIC ID of the processor to be brought up.
 *
 * @return 0 on failure, 1 on success.
 */
int l_apic_send_init_ipi(__u8 apicid)
{
    icr_t icr;
    int i;
 
    /*
     * Read the ICR register in and zero all non-reserved fields.
     */
    icr.lo = l_apic[ICRlo];
    icr.hi = l_apic[ICRhi];
   
    icr.delmod = DELMOD_INIT;
    icr.destmod = DESTMOD_PHYS;
    icr.level = LEVEL_ASSERT;
    icr.trigger_mode = TRIGMOD_LEVEL;
    icr.shorthand = SHORTHAND_NONE;
    icr.vector = 0;
    icr.dest = apicid;
   
    l_apic[ICRhi] = icr.hi;
    l_apic[ICRlo] = icr.lo;
 
    /*
     * According to MP Specification, 20us should be enough to
     * deliver the IPI.
     */
    delay(20);
 
    if (!apic_poll_errors()) return 0;
 
    icr.lo = l_apic[ICRlo];
    if (icr.delivs == DELIVS_PENDING)
        printf("IPI is pending.\n");
 
    icr.delmod = DELMOD_INIT;
    icr.destmod = DESTMOD_PHYS;
    icr.level = LEVEL_DEASSERT;
    icr.shorthand = SHORTHAND_NONE;
    icr.trigger_mode = TRIGMOD_LEVEL;
    icr.vector = 0;
    l_apic[ICRlo] = icr.lo;
 
    /*
     * Wait 10ms as MP Specification specifies.
     */
    delay(10000);
 
    if (!is_82489DX_apic(l_apic[LAVR])) {
        /*
         * If this is not 82489DX-based l_apic we must send two STARTUP IPI's.
         */
        for (i = 0; i<2; i++) {
            icr.lo = l_apic[ICRlo];
            icr.vector = ((__address) ap_boot) / 4096; /* calculate the reset vector */
            icr.delmod = DELMOD_STARTUP;
            icr.destmod = DESTMOD_PHYS;
            icr.level = LEVEL_ASSERT;
            icr.shorthand = SHORTHAND_NONE;
            icr.trigger_mode = TRIGMOD_LEVEL;
            l_apic[ICRlo] = icr.lo;
            delay(200);
        }
    }
   
    return apic_poll_errors();
}
 
/** Initialize Local APIC. */
void l_apic_init(void)
{
    lvt_error_t error;
    lvt_lint_t lint;
    tpr_t tpr;
    svr_t svr;
    icr_t icr;
    tdcr_t tdcr;
    lvt_tm_t tm;
    ldr_t ldr;
    dfr_t dfr;
    __u32 t1, t2;
 
    /* Initialize LVT Error register. */
    error.value = l_apic[LVT_Err];
    error.masked = true;
    l_apic[LVT_Err] = error.value;
 
    /* Initialize LVT LINT0 register. */
    lint.value = l_apic[LVT_LINT0];
    lint.masked = true;
    l_apic[LVT_LINT0] = lint.value;
 
    /* Initialize LVT LINT1 register. */
    lint.value = l_apic[LVT_LINT1];
    lint.masked = true;
    l_apic[LVT_LINT1] = lint.value;
 
    /* Task Priority Register initialization. */
    tpr.value = l_apic[TPR];
    tpr.pri_sc = 0;
    tpr.pri = 0;
    l_apic[TPR] = tpr.value;
   
    /* Spurious-Interrupt Vector Register initialization. */
    svr.value = l_apic[SVR];
    svr.vector = VECTOR_APIC_SPUR;
    svr.lapic_enabled = true;
    svr.focus_checking = true;
    l_apic[SVR] = svr.value;
 
 
 
    if (CPU->arch.family >= 6)
        enable_l_apic_in_msr();
   
    /* Interrupt Command Register initialization. */
    icr.lo = l_apic[ICRlo];
    icr.delmod = DELMOD_INIT;
    icr.destmod = DESTMOD_PHYS;
    icr.level = LEVEL_DEASSERT;
    icr.shorthand = SHORTHAND_ALL_INCL;
    icr.trigger_mode = TRIGMOD_LEVEL;
    l_apic[ICRlo] = icr.lo;
   
    /* Timer Divide Configuration Register initialization. */
    tdcr.value = l_apic[TDCR];
    tdcr.div_value = DIVIDE_1;
    l_apic[TDCR] = tdcr.value;
 
    /* Program local timer. */
    tm.value = l_apic[LVT_Tm];
    tm.vector = VECTOR_CLK;
    tm.mode = TIMER_PERIODIC;
    tm.masked = false;
    l_apic[LVT_Tm] = tm.value;
 
    /* Measure and configure the timer to generate timer interrupt each ms. */
    t1 = l_apic[CCRT];
    l_apic[ICRT] = 0xffffffff;
 
    while (l_apic[CCRT] == t1)
        ;
       
    t1 = l_apic[CCRT];
    delay(1000);
    t2 = l_apic[CCRT];
   
    l_apic[ICRT] = t1-t2;
   
    /* Program Logical Destination Register. */
    ldr.value = l_apic[LDR];
    if (CPU->id < sizeof(CPU->id)*8)    /* size in bits */
        ldr.id = (1<<CPU->id);
    l_apic[LDR] = ldr.value;
   
    /* Program Destination Format Register for Flat mode. */
    dfr.value = l_apic[DFR];
    dfr.model = MODEL_FLAT;
    l_apic[DFR] = dfr.value;
}
 
/** Local APIC End of Interrupt. */
void l_apic_eoi(void)
{
    l_apic[EOI] = 0;
}
 
/** Dump content of Local APIC registers. */
void l_apic_debug(void)
{
#ifdef LAPIC_VERBOSE
    lvt_tm_t tm;
    lvt_lint_t lint;
    lvt_error_t error; 
   
    printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id());
 
    tm.value = l_apic[LVT_Tm];
    printf("LVT Tm: vector=%B, %s, %s, %s\n", tm.vector, delivs_str[tm.delivs], mask_str[tm.masked], tm_mode_str[tm.mode]);
    lint.value = l_apic[LVT_LINT0];
    printf("LVT LINT0: vector=%B, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]);
    lint.value = l_apic[LVT_LINT1];
    printf("LVT LINT1: vector=%B, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]);   
    error.value = l_apic[LVT_Err];
    printf("LVT Err: vector=%B, %s, %s\n", error.vector, delivs_str[error.delivs], mask_str[error.masked]);
#endif
}
 
/** Local APIC Timer Interrupt.
 *
 * @param n Interrupt vector number.
 * @param stack Interrupted stack.
 */
void l_apic_timer_interrupt(int n, void *stack)
{
    l_apic_eoi();
    clock();
}
 
/** Get Local APIC ID.
 *
 * @return Local APIC ID.
 */
__u8 l_apic_id(void)
{
    l_apic_id_t idreg;
   
    idreg.value = l_apic[L_APIC_ID];
    return idreg.apic_id;
}
 
/** Read from IO APIC register.
 *
 * @param address IO APIC register address.
 *
 * @return Content of the addressed IO APIC register.
 */
__u32 io_apic_read(__u8 address)
{
    io_regsel_t regsel;
   
    regsel.value = io_apic[IOREGSEL];
    regsel.reg_addr = address;
    io_apic[IOREGSEL] = regsel.value;
    return io_apic[IOWIN];
}
 
/** Write to IO APIC register.
 *
 * @param address IO APIC register address.
 * @param Content to be written to the addressed IO APIC register.
 */
void io_apic_write(__u8 address, __u32 x)
{
    io_regsel_t regsel;
   
    regsel.value = io_apic[IOREGSEL];
    regsel.reg_addr = address;
    io_apic[IOREGSEL] = regsel.value;
    io_apic[IOWIN] = x;
}
 
/** Change some attributes of one item in I/O Redirection Table.
 *
 * @param pin IO APIC pin number.
 * @param dest Interrupt destination address.
 * @param v Interrupt vector to trigger.
 * @param flags Flags.
 */
void io_apic_change_ioredtbl(int pin, int dest, __u8 v, int flags)
{
    io_redirection_reg_t reg;
    int dlvr = DELMOD_FIXED;
   
    if (flags & LOPRI)
        dlvr = DELMOD_LOWPRI;
 
    reg.lo = io_apic_read(IOREDTBL + pin*2);
    reg.hi = io_apic_read(IOREDTBL + pin*2 + 1);
   
    reg.dest = dest;
    reg.destmod = DESTMOD_LOGIC;
    reg.trigger_mode = TRIGMOD_EDGE;
    reg.intpol = POLARITY_HIGH;
    reg.delmod = dlvr;
    reg.intvec = v;
 
    io_apic_write(IOREDTBL + pin*2, reg.lo);
    io_apic_write(IOREDTBL + pin*2 + 1, reg.hi);
}
 
/** Mask IRQs in IO APIC.
 *
 * @param irqmask Bitmask of IRQs to be masked (0 = do not mask, 1 = mask).
 */
void io_apic_disable_irqs(__u16 irqmask)
{
    io_redirection_reg_t reg;
    int i, pin;
   
    for (i=0;i<16;i++) {
        if (irqmask & (1<<i)) {
            /*
             * Mask the signal input in IO APIC if there is a
             * mapping for the respective IRQ number.
             */
            pin = smp_irq_to_pin(i);
            if (pin != -1) {
                reg.lo = io_apic_read(IOREDTBL + pin*2);
                reg.masked = true;
                io_apic_write(IOREDTBL + pin*2, reg.lo);
            }
           
        }
    }
}
 
/** Unmask IRQs in IO APIC.
 *
 * @param irqmask Bitmask of IRQs to be unmasked (0 = do not unmask, 1 = unmask).
 */
void io_apic_enable_irqs(__u16 irqmask)
{
    int i, pin;
    io_redirection_reg_t reg;  
   
    for (i=0;i<16;i++) {
        if (irqmask & (1<<i)) {
            /*
             * Unmask the signal input in IO APIC if there is a
             * mapping for the respective IRQ number.
             */
            pin = smp_irq_to_pin(i);
            if (pin != -1) {
                reg.lo = io_apic_read(IOREDTBL + pin*2);
                reg.masked = false;
                io_apic_write(IOREDTBL + pin*2, reg.lo);
            }
           
        }
    }
}
 
#endif /* CONFIG_SMP */
 

Rev 693	Rev 750
1	/*	1	/*
2	* Copyright (C) 2001-2004 Jakub Jermar	2	* Copyright (C) 2001-2004 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	#include <arch/types.h>	29	#include <arch/types.h>
30	#include <arch/smp/apic.h>	30	#include <arch/smp/apic.h>
31	#include <arch/smp/ap.h>	31	#include <arch/smp/ap.h>
32	#include <arch/smp/mps.h>	32	#include <arch/smp/mps.h>
33	#include <arch/boot/boot.h>	33	#include <arch/boot/boot.h>
34	#include <mm/page.h>	34	#include <mm/page.h>
35	#include <time/delay.h>	35	#include <time/delay.h>
36	#include <interrupt.h>	36	#include <interrupt.h>
37	#include <arch/interrupt.h>	37	#include <arch/interrupt.h>
38	#include <print.h>	38	#include <print.h>
39	#include <arch/asm.h>	39	#include <arch/asm.h>
40	#include <arch.h>	40	#include <arch.h>
41		41
42	#ifdef CONFIG_SMP	42	#ifdef CONFIG_SMP
43		43
44	/*	44	/*
45	* Advanced Programmable Interrupt Controller for SMP systems.	45	* Advanced Programmable Interrupt Controller for SMP systems.
46	* Tested on:	46	* Tested on:
47	* Bochs 2.0.2 - Bochs 2.2.5 with 2-8 CPUs	47	* Bochs 2.0.2 - Bochs 2.2.6 with 2-8 CPUs
48	* Simics 2.0.28 - Simics 2.2.19 2-15 CPUs	48	* Simics 2.0.28 - Simics 2.2.19 2-15 CPUs
49	* VMware Workstation 5.5 with 2 CPUs	49	* VMware Workstation 5.5 with 2 CPUs
50	* ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs	50	* ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs
51	* ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs	51	* ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs
52	* MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs	52	* MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs
53	*/	53	*/
54		54
55	/*	55	/*
56	* These variables either stay configured as initilalized, or are changed by	56	* These variables either stay configured as initilalized, or are changed by
57	* the MP configuration code.	57	* the MP configuration code.
58	*	58	*
59	* Pay special attention to the volatile keyword. Without it, gcc -O2 would	59	* Pay special attention to the volatile keyword. Without it, gcc -O2 would
60	* optimize the code too much and accesses to l_apic and io_apic, that must	60	* optimize the code too much and accesses to l_apic and io_apic, that must
61	* always be 32-bit, would use byte oriented instructions.	61	* always be 32-bit, would use byte oriented instructions.
62	*/	62	*/
63	volatile __u32 l_apic = (__u32 ) 0xfee00000;	63	volatile __u32 l_apic = (__u32 ) 0xfee00000;
64	volatile __u32 io_apic = (__u32 ) 0xfec00000;	64	volatile __u32 io_apic = (__u32 ) 0xfec00000;
65		65
66	__u32 apic_id_mask = 0;	66	__u32 apic_id_mask = 0;
67		67
68	static int apic_poll_errors(void);	68	static int apic_poll_errors(void);
69		69
70	#ifdef LAPIC_VERBOSE	70	#ifdef LAPIC_VERBOSE
71	static char *delmod_str[] = {	71	static char *delmod_str[] = {
72	"Fixed",	72	"Fixed",
73	"Lowest Priority",	73	"Lowest Priority",
74	"SMI",	74	"SMI",
75	"Reserved",	75	"Reserved",
76	"NMI",	76	"NMI",
77	"INIT",	77	"INIT",
78	"STARTUP",	78	"STARTUP",
79	"ExtInt"	79	"ExtInt"
80	};	80	};
81		81
82	static char *destmod_str[] = {	82	static char *destmod_str[] = {
83	"Physical",	83	"Physical",
84	"Logical"	84	"Logical"
85	};	85	};
86		86
87	static char *trigmod_str[] = {	87	static char *trigmod_str[] = {
88	"Edge",	88	"Edge",
89	"Level"	89	"Level"
90	};	90	};
91		91
92	static char *mask_str[] = {	92	static char *mask_str[] = {
93	"Unmasked",	93	"Unmasked",
94	"Masked"	94	"Masked"
95	};	95	};
96		96
97	static char *delivs_str[] = {	97	static char *delivs_str[] = {
98	"Idle",	98	"Idle",
99	"Send Pending"	99	"Send Pending"
100	};	100	};
101		101
102	static char *tm_mode_str[] = {	102	static char *tm_mode_str[] = {
103	"One-shot",	103	"One-shot",
104	"Periodic"	104	"Periodic"
105	};	105	};
106		106
107	static char *intpol_str[] = {	107	static char *intpol_str[] = {
108	"Polarity High",	108	"Polarity High",
109	"Polarity Low"	109	"Polarity Low"
110	};	110	};
111	#endif /* LAPIC_VERBOSE */	111	#endif /* LAPIC_VERBOSE */
112		112
113		113
114	static void apic_spurious(int n, void *stack);	114	static void apic_spurious(int n, void *stack);
115	static void l_apic_timer_interrupt(int n, void *stack);	115	static void l_apic_timer_interrupt(int n, void *stack);
116		116
117	/** Initialize APIC on BSP. */	117	/** Initialize APIC on BSP. */
118	void apic_init(void)	118	void apic_init(void)
119	{	119	{
120	io_apic_id_t idreg;	120	io_apic_id_t idreg;
121	int i;	121	int i;
122		122
123	exc_register(VECTOR_APIC_SPUR, "apic_spurious", apic_spurious);	123	exc_register(VECTOR_APIC_SPUR, "apic_spurious", apic_spurious);
124		124
125	enable_irqs_function = io_apic_enable_irqs;	125	enable_irqs_function = io_apic_enable_irqs;
126	disable_irqs_function = io_apic_disable_irqs;	126	disable_irqs_function = io_apic_disable_irqs;
127	eoi_function = l_apic_eoi;	127	eoi_function = l_apic_eoi;
128		128
129	/*	129	/*
130	* Configure interrupt routing.	130	* Configure interrupt routing.
131	* IRQ 0 remains masked as the time signal is generated by l_apic's themselves.	131	* IRQ 0 remains masked as the time signal is generated by l_apic's themselves.
132	* Other interrupts will be forwarded to the lowest priority CPU.	132	* Other interrupts will be forwarded to the lowest priority CPU.
133	*/	133	*/
134	io_apic_disable_irqs(0xffff);	134	io_apic_disable_irqs(0xffff);
135	exc_register(VECTOR_CLK, "l_apic_timer", l_apic_timer_interrupt);	135	exc_register(VECTOR_CLK, "l_apic_timer", l_apic_timer_interrupt);
136	for (i = 0; i < IRQ_COUNT; i++) {	136	for (i = 0; i < IRQ_COUNT; i++) {
137	int pin;	137	int pin;
138		138
139	if ((pin = smp_irq_to_pin(i)) != -1) {	139	if ((pin = smp_irq_to_pin(i)) != -1) {
140	io_apic_change_ioredtbl(pin, DEST_ALL, IVT_IRQBASE+i, LOPRI);	140	io_apic_change_ioredtbl(pin, DEST_ALL, IVT_IRQBASE+i, LOPRI);
141	}	141	}
142	}	142	}
143		143
144	/*	144	/*
145	* Ensure that io_apic has unique ID.	145	* Ensure that io_apic has unique ID.
146	*/	146	*/
147	idreg.value = io_apic_read(IOAPICID);	147	idreg.value = io_apic_read(IOAPICID);
148	if ((1<<idreg.apic_id) & apic_id_mask) { /* see if IO APIC ID is used already */	148	if ((1<<idreg.apic_id) & apic_id_mask) { /* see if IO APIC ID is used already */
149	for (i = 0; i < APIC_ID_COUNT; i++) {	149	for (i = 0; i < APIC_ID_COUNT; i++) {
150	if (!((1<<i) & apic_id_mask)) {	150	if (!((1<<i) & apic_id_mask)) {
151	idreg.apic_id = i;	151	idreg.apic_id = i;
152	io_apic_write(IOAPICID, idreg.value);	152	io_apic_write(IOAPICID, idreg.value);
153	break;	153	break;
154	}	154	}
155	}	155	}
156	}	156	}
157		157
158	/*	158	/*
159	* Configure the BSP's lapic.	159	* Configure the BSP's lapic.
160	*/	160	*/
161	l_apic_init();	161	l_apic_init();
162		162
163	l_apic_debug();	163	l_apic_debug();
164	}	164	}
165		165
166	/** APIC spurious interrupt handler.	166	/** APIC spurious interrupt handler.
167	*	167	*
168	* @param n Interrupt vector.	168	* @param n Interrupt vector.
169	* @param stack Interrupted stack.	169	* @param stack Interrupted stack.
170	*/	170	*/
171	void apic_spurious(int n, void *stack)	171	void apic_spurious(int n, void *stack)
172	{	172	{
173	printf("cpu%d: APIC spurious interrupt\n", CPU->id);	173	printf("cpu%d: APIC spurious interrupt\n", CPU->id);
174	}	174	}
175		175
176	/** Poll for APIC errors.	176	/** Poll for APIC errors.
177	*	177	*
178	* Examine Error Status Register and report all errors found.	178	* Examine Error Status Register and report all errors found.
179	*	179	*
180	* @return 0 on error, 1 on success.	180	* @return 0 on error, 1 on success.
181	*/	181	*/
182	int apic_poll_errors(void)	182	int apic_poll_errors(void)
183	{	183	{
184	esr_t esr;	184	esr_t esr;
185		185
186	esr.value = l_apic[ESR];	186	esr.value = l_apic[ESR];
187		187
188	if (esr.send_checksum_error)	188	if (esr.send_checksum_error)
189	printf("Send Checksum Error\n");	189	printf("Send Checksum Error\n");
190	if (esr.receive_checksum_error)	190	if (esr.receive_checksum_error)
191	printf("Receive Checksum Error\n");	191	printf("Receive Checksum Error\n");
192	if (esr.send_accept_error)	192	if (esr.send_accept_error)
193	printf("Send Accept Error\n");	193	printf("Send Accept Error\n");
194	if (esr.receive_accept_error)	194	if (esr.receive_accept_error)
195	printf("Receive Accept Error\n");	195	printf("Receive Accept Error\n");
196	if (esr.send_illegal_vector)	196	if (esr.send_illegal_vector)
197	printf("Send Illegal Vector\n");	197	printf("Send Illegal Vector\n");
198	if (esr.received_illegal_vector)	198	if (esr.received_illegal_vector)
199	printf("Received Illegal Vector\n");	199	printf("Received Illegal Vector\n");
200	if (esr.illegal_register_address)	200	if (esr.illegal_register_address)
201	printf("Illegal Register Address\n");	201	printf("Illegal Register Address\n");
202		202
203	return !esr.err_bitmap;	203	return !esr.err_bitmap;
204	}	204	}
205		205
206	/** Send all CPUs excluding CPU IPI vector.	206	/** Send all CPUs excluding CPU IPI vector.
207	*	207	*
208	* @param vector Interrupt vector to be sent.	208	* @param vector Interrupt vector to be sent.
209	*	209	*
210	* @return 0 on failure, 1 on success.	210	* @return 0 on failure, 1 on success.
211	*/	211	*/
212	int l_apic_broadcast_custom_ipi(__u8 vector)	212	int l_apic_broadcast_custom_ipi(__u8 vector)
213	{	213	{
214	icr_t icr;	214	icr_t icr;
215		215
216	icr.lo = l_apic[ICRlo];	216	icr.lo = l_apic[ICRlo];
217	icr.delmod = DELMOD_FIXED;	217	icr.delmod = DELMOD_FIXED;
218	icr.destmod = DESTMOD_LOGIC;	218	icr.destmod = DESTMOD_LOGIC;
219	icr.level = LEVEL_ASSERT;	219	icr.level = LEVEL_ASSERT;
220	icr.shorthand = SHORTHAND_ALL_EXCL;	220	icr.shorthand = SHORTHAND_ALL_EXCL;
221	icr.trigger_mode = TRIGMOD_LEVEL;	221	icr.trigger_mode = TRIGMOD_LEVEL;
222	icr.vector = vector;	222	icr.vector = vector;
223		223
224	l_apic[ICRlo] = icr.lo;	224	l_apic[ICRlo] = icr.lo;
225		225
226	icr.lo = l_apic[ICRlo];	226	icr.lo = l_apic[ICRlo];
227	if (icr.delivs == DELIVS_PENDING)	227	if (icr.delivs == DELIVS_PENDING)
228	printf("IPI is pending.\n");	228	printf("IPI is pending.\n");
229		229
230	return apic_poll_errors();	230	return apic_poll_errors();
231	}	231	}
232		232
233	/** Universal Start-up Algorithm for bringing up the AP processors.	233	/** Universal Start-up Algorithm for bringing up the AP processors.
234	*	234	*
235	* @param apicid APIC ID of the processor to be brought up.	235	* @param apicid APIC ID of the processor to be brought up.
236	*	236	*
237	* @return 0 on failure, 1 on success.	237	* @return 0 on failure, 1 on success.
238	*/	238	*/
239	int l_apic_send_init_ipi(__u8 apicid)	239	int l_apic_send_init_ipi(__u8 apicid)
240	{	240	{
241	icr_t icr;	241	icr_t icr;
242	int i;	242	int i;
243		243
244	/*	244	/*
245	* Read the ICR register in and zero all non-reserved fields.	245	* Read the ICR register in and zero all non-reserved fields.
246	*/	246	*/
247	icr.lo = l_apic[ICRlo];	247	icr.lo = l_apic[ICRlo];
248	icr.hi = l_apic[ICRhi];	248	icr.hi = l_apic[ICRhi];
249		249
250	icr.delmod = DELMOD_INIT;	250	icr.delmod = DELMOD_INIT;
251	icr.destmod = DESTMOD_PHYS;	251	icr.destmod = DESTMOD_PHYS;
252	icr.level = LEVEL_ASSERT;	252	icr.level = LEVEL_ASSERT;
253	icr.trigger_mode = TRIGMOD_LEVEL;	253	icr.trigger_mode = TRIGMOD_LEVEL;
254	icr.shorthand = SHORTHAND_NONE;	254	icr.shorthand = SHORTHAND_NONE;
255	icr.vector = 0;	255	icr.vector = 0;
256	icr.dest = apicid;	256	icr.dest = apicid;
257		257
258	l_apic[ICRhi] = icr.hi;	258	l_apic[ICRhi] = icr.hi;
259	l_apic[ICRlo] = icr.lo;	259	l_apic[ICRlo] = icr.lo;
260		260
261	/*	261	/*
262	* According to MP Specification, 20us should be enough to	262	* According to MP Specification, 20us should be enough to
263	* deliver the IPI.	263	* deliver the IPI.
264	*/	264	*/
265	delay(20);	265	delay(20);
266		266
267	if (!apic_poll_errors()) return 0;	267	if (!apic_poll_errors()) return 0;
268		268
269	icr.lo = l_apic[ICRlo];	269	icr.lo = l_apic[ICRlo];
270	if (icr.delivs == DELIVS_PENDING)	270	if (icr.delivs == DELIVS_PENDING)
271	printf("IPI is pending.\n");	271	printf("IPI is pending.\n");
272		272
273	icr.delmod = DELMOD_INIT;	273	icr.delmod = DELMOD_INIT;
274	icr.destmod = DESTMOD_PHYS;	274	icr.destmod = DESTMOD_PHYS;
275	icr.level = LEVEL_DEASSERT;	275	icr.level = LEVEL_DEASSERT;
276	icr.shorthand = SHORTHAND_NONE;	276	icr.shorthand = SHORTHAND_NONE;
277	icr.trigger_mode = TRIGMOD_LEVEL;	277	icr.trigger_mode = TRIGMOD_LEVEL;
278	icr.vector = 0;	278	icr.vector = 0;
279	l_apic[ICRlo] = icr.lo;	279	l_apic[ICRlo] = icr.lo;
280		280
281	/*	281	/*
282	* Wait 10ms as MP Specification specifies.	282	* Wait 10ms as MP Specification specifies.
283	*/	283	*/
284	delay(10000);	284	delay(10000);
285		285
286	if (!is_82489DX_apic(l_apic[LAVR])) {	286	if (!is_82489DX_apic(l_apic[LAVR])) {
287	/*	287	/*
288	* If this is not 82489DX-based l_apic we must send two STARTUP IPI's.	288	* If this is not 82489DX-based l_apic we must send two STARTUP IPI's.
289	*/	289	*/
290	for (i = 0; i<2; i++) {	290	for (i = 0; i<2; i++) {
291	icr.lo = l_apic[ICRlo];	291	icr.lo = l_apic[ICRlo];
292	icr.vector = ((__address) ap_boot) / 4096; /* calculate the reset vector */	292	icr.vector = ((__address) ap_boot) / 4096; /* calculate the reset vector */
293	icr.delmod = DELMOD_STARTUP;	293	icr.delmod = DELMOD_STARTUP;
294	icr.destmod = DESTMOD_PHYS;	294	icr.destmod = DESTMOD_PHYS;
295	icr.level = LEVEL_ASSERT;	295	icr.level = LEVEL_ASSERT;
296	icr.shorthand = SHORTHAND_NONE;	296	icr.shorthand = SHORTHAND_NONE;
297	icr.trigger_mode = TRIGMOD_LEVEL;	297	icr.trigger_mode = TRIGMOD_LEVEL;
298	l_apic[ICRlo] = icr.lo;	298	l_apic[ICRlo] = icr.lo;
299	delay(200);	299	delay(200);
300	}	300	}
301	}	301	}
302		302
303	return apic_poll_errors();	303	return apic_poll_errors();
304	}	304	}
305		305
306	/** Initialize Local APIC. */	306	/** Initialize Local APIC. */
307	void l_apic_init(void)	307	void l_apic_init(void)
308	{	308	{
309	lvt_error_t error;	309	lvt_error_t error;
310	lvt_lint_t lint;	310	lvt_lint_t lint;
-		311	tpr_t tpr;
311	svr_t svr;	312	svr_t svr;
312	icr_t icr;	313	icr_t icr;
313	tdcr_t tdcr;	314	tdcr_t tdcr;
314	lvt_tm_t tm;	315	lvt_tm_t tm;
315	ldr_t ldr;	316	ldr_t ldr;
316	dfr_t dfr;	317	dfr_t dfr;
317	__u32 t1, t2;	318	__u32 t1, t2;
318		319
319	/* Initialize LVT Error register. */	320	/* Initialize LVT Error register. */
320	error.value = l_apic[LVT_Err];	321	error.value = l_apic[LVT_Err];
321	error.masked = true;	322	error.masked = true;
322	l_apic[LVT_Err] = error.value;	323	l_apic[LVT_Err] = error.value;
323		324
324	/* Initialize LVT LINT0 register. */	325	/* Initialize LVT LINT0 register. */
325	lint.value = l_apic[LVT_LINT0];	326	lint.value = l_apic[LVT_LINT0];
326	lint.masked = true;	327	lint.masked = true;
327	l_apic[LVT_LINT0] = lint.value;	328	l_apic[LVT_LINT0] = lint.value;
328		329
329	/* Initialize LVT LINT1 register. */	330	/* Initialize LVT LINT1 register. */
330	lint.value = l_apic[LVT_LINT1];	331	lint.value = l_apic[LVT_LINT1];
331	lint.masked = true;	332	lint.masked = true;
332	l_apic[LVT_LINT1] = lint.value;	333	l_apic[LVT_LINT1] = lint.value;
333		334
-		335	/* Task Priority Register initialization. */
-		336	tpr.value = l_apic[TPR];
-		337	tpr.pri_sc = 0;
-		338	tpr.pri = 0;
-		339	l_apic[TPR] = tpr.value;
-		340
334	/* Spurious-Interrupt Vector Register initialization. */	341	/* Spurious-Interrupt Vector Register initialization. */
335	svr.value = l_apic[SVR];	342	svr.value = l_apic[SVR];
336	svr.vector = VECTOR_APIC_SPUR;	343	svr.vector = VECTOR_APIC_SPUR;
337	svr.lapic_enabled = true;	344	svr.lapic_enabled = true;
-		345	svr.focus_checking = true;
338	l_apic[SVR] = svr.value;	346	l_apic[SVR] = svr.value;
339		347
340	l_apic[TPR] &= TPRClear;	-
341		-
342	if (CPU->arch.family >= 6)	348	if (CPU->arch.family >= 6)
343	enable_l_apic_in_msr();	349	enable_l_apic_in_msr();
344		350
345	/* Interrupt Command Register initialization. */	351	/* Interrupt Command Register initialization. */
346	icr.lo = l_apic[ICRlo];	352	icr.lo = l_apic[ICRlo];
347	icr.delmod = DELMOD_INIT;	353	icr.delmod = DELMOD_INIT;
348	icr.destmod = DESTMOD_PHYS;	354	icr.destmod = DESTMOD_PHYS;
349	icr.level = LEVEL_DEASSERT;	355	icr.level = LEVEL_DEASSERT;
350	icr.shorthand = SHORTHAND_ALL_INCL;	356	icr.shorthand = SHORTHAND_ALL_INCL;
351	icr.trigger_mode = TRIGMOD_LEVEL;	357	icr.trigger_mode = TRIGMOD_LEVEL;
352	l_apic[ICRlo] = icr.lo;	358	l_apic[ICRlo] = icr.lo;
353		359
354	/* Timer Divide Configuration Register initialization. */	360	/* Timer Divide Configuration Register initialization. */
355	tdcr.value = l_apic[TDCR];	361	tdcr.value = l_apic[TDCR];
356	tdcr.div_value = DIVIDE_1;	362	tdcr.div_value = DIVIDE_1;
357	l_apic[TDCR] = tdcr.value;	363	l_apic[TDCR] = tdcr.value;
358		364
359	/* Program local timer. */	365	/* Program local timer. */
360	tm.value = l_apic[LVT_Tm];	366	tm.value = l_apic[LVT_Tm];
361	tm.vector = VECTOR_CLK;	367	tm.vector = VECTOR_CLK;
362	tm.mode = TIMER_PERIODIC;	368	tm.mode = TIMER_PERIODIC;
363	tm.masked = false;	369	tm.masked = false;
364	l_apic[LVT_Tm] = tm.value;	370	l_apic[LVT_Tm] = tm.value;
365		371
366	/* Measure and configure the timer to generate timer interrupt each ms. */	372	/* Measure and configure the timer to generate timer interrupt each ms. */
367	t1 = l_apic[CCRT];	373	t1 = l_apic[CCRT];
368	l_apic[ICRT] = 0xffffffff;	374	l_apic[ICRT] = 0xffffffff;
369		375
370	while (l_apic[CCRT] == t1)	376	while (l_apic[CCRT] == t1)
371	;	377	;
372		378
373	t1 = l_apic[CCRT];	379	t1 = l_apic[CCRT];
374	delay(1000);	380	delay(1000);
375	t2 = l_apic[CCRT];	381	t2 = l_apic[CCRT];
376		382
377	l_apic[ICRT] = t1-t2;	383	l_apic[ICRT] = t1-t2;
378		384
379	/* Program Logical Destination Register. */	385	/* Program Logical Destination Register. */
380	ldr.value = l_apic[LDR];	386	ldr.value = l_apic[LDR];
381	if (CPU->id < sizeof(CPU->id)8) / size in bits */	387	if (CPU->id < sizeof(CPU->id)8) / size in bits */
382	ldr.id = (1<<CPU->id);	388	ldr.id = (1<<CPU->id);
383	l_apic[LDR] = ldr.value;	389	l_apic[LDR] = ldr.value;
384		390
385	/* Program Destination Format Register for Flat mode. */	391	/* Program Destination Format Register for Flat mode. */
386	dfr.value = l_apic[DFR];	392	dfr.value = l_apic[DFR];
387	dfr.model = MODEL_FLAT;	393	dfr.model = MODEL_FLAT;
388	l_apic[DFR] = dfr.value;	394	l_apic[DFR] = dfr.value;
389	}	395	}
390		396
391	/** Local APIC End of Interrupt. */	397	/** Local APIC End of Interrupt. */
392	void l_apic_eoi(void)	398	void l_apic_eoi(void)
393	{	399	{
394	l_apic[EOI] = 0;	400	l_apic[EOI] = 0;
395	}	401	}
396		402
397	/** Dump content of Local APIC registers. */	403	/** Dump content of Local APIC registers. */
398	void l_apic_debug(void)	404	void l_apic_debug(void)
399	{	405	{
400	#ifdef LAPIC_VERBOSE	406	#ifdef LAPIC_VERBOSE
401	lvt_tm_t tm;	407	lvt_tm_t tm;
402	lvt_lint_t lint;	408	lvt_lint_t lint;
403	lvt_error_t error;	409	lvt_error_t error;
404		410
405	printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id());	411	printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id());
406		412
407	tm.value = l_apic[LVT_Tm];	413	tm.value = l_apic[LVT_Tm];
408	printf("LVT Tm: vector=%B, %s, %s, %s\n", tm.vector, delivs_str[tm.delivs], mask_str[tm.masked], tm_mode_str[tm.mode]);	414	printf("LVT Tm: vector=%B, %s, %s, %s\n", tm.vector, delivs_str[tm.delivs], mask_str[tm.masked], tm_mode_str[tm.mode]);
409	lint.value = l_apic[LVT_LINT0];	415	lint.value = l_apic[LVT_LINT0];
410	printf("LVT LINT0: vector=%B, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]);	416	printf("LVT LINT0: vector=%B, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]);
411	lint.value = l_apic[LVT_LINT1];	417	lint.value = l_apic[LVT_LINT1];
412	printf("LVT LINT1: vector=%B, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]);	418	printf("LVT LINT1: vector=%B, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]);
413	error.value = l_apic[LVT_Err];	419	error.value = l_apic[LVT_Err];
414	printf("LVT Err: vector=%B, %s, %s\n", error.vector, delivs_str[error.delivs], mask_str[error.masked]);	420	printf("LVT Err: vector=%B, %s, %s\n", error.vector, delivs_str[error.delivs], mask_str[error.masked]);
415	#endif	421	#endif
416	}	422	}
417		423
418	/** Local APIC Timer Interrupt.	424	/** Local APIC Timer Interrupt.
419	*	425	*
420	* @param n Interrupt vector number.	426	* @param n Interrupt vector number.
421	* @param stack Interrupted stack.	427	* @param stack Interrupted stack.
422	*/	428	*/
423	void l_apic_timer_interrupt(int n, void *stack)	429	void l_apic_timer_interrupt(int n, void *stack)
424	{	430	{
425	l_apic_eoi();	431	l_apic_eoi();
426	clock();	432	clock();
427	}	433	}
428		434
429	/** Get Local APIC ID.	435	/** Get Local APIC ID.
430	*	436	*
431	* @return Local APIC ID.	437	* @return Local APIC ID.
432	*/	438	*/
433	__u8 l_apic_id(void)	439	__u8 l_apic_id(void)
434	{	440	{
435	l_apic_id_t idreg;	441	l_apic_id_t idreg;
436		442
437	idreg.value = l_apic[L_APIC_ID];	443	idreg.value = l_apic[L_APIC_ID];
438	return idreg.apic_id;	444	return idreg.apic_id;
439	}	445	}
440		446
441	/** Read from IO APIC register.	447	/** Read from IO APIC register.
442	*	448	*
443	* @param address IO APIC register address.	449	* @param address IO APIC register address.
444	*	450	*
445	* @return Content of the addressed IO APIC register.	451	* @return Content of the addressed IO APIC register.
446	*/	452	*/
447	__u32 io_apic_read(__u8 address)	453	__u32 io_apic_read(__u8 address)
448	{	454	{
449	io_regsel_t regsel;	455	io_regsel_t regsel;
450		456
451	regsel.value = io_apic[IOREGSEL];	457	regsel.value = io_apic[IOREGSEL];
452	regsel.reg_addr = address;	458	regsel.reg_addr = address;
453	io_apic[IOREGSEL] = regsel.value;	459	io_apic[IOREGSEL] = regsel.value;
454	return io_apic[IOWIN];	460	return io_apic[IOWIN];
455	}	461	}
456		462
457	/** Write to IO APIC register.	463	/** Write to IO APIC register.
458	*	464	*
459	* @param address IO APIC register address.	465	* @param address IO APIC register address.
460	* @param Content to be written to the addressed IO APIC register.	466	* @param Content to be written to the addressed IO APIC register.
461	*/	467	*/
462	void io_apic_write(__u8 address, __u32 x)	468	void io_apic_write(__u8 address, __u32 x)
463	{	469	{
464	io_regsel_t regsel;	470	io_regsel_t regsel;
465		471
466	regsel.value = io_apic[IOREGSEL];	472	regsel.value = io_apic[IOREGSEL];
467	regsel.reg_addr = address;	473	regsel.reg_addr = address;
468	io_apic[IOREGSEL] = regsel.value;	474	io_apic[IOREGSEL] = regsel.value;
469	io_apic[IOWIN] = x;	475	io_apic[IOWIN] = x;
470	}	476	}
471		477
472	/** Change some attributes of one item in I/O Redirection Table.	478	/** Change some attributes of one item in I/O Redirection Table.
473	*	479	*
474	* @param pin IO APIC pin number.	480	* @param pin IO APIC pin number.
475	* @param dest Interrupt destination address.	481	* @param dest Interrupt destination address.
476	* @param v Interrupt vector to trigger.	482	* @param v Interrupt vector to trigger.
477	* @param flags Flags.	483	* @param flags Flags.
478	*/	484	*/
479	void io_apic_change_ioredtbl(int pin, int dest, __u8 v, int flags)	485	void io_apic_change_ioredtbl(int pin, int dest, __u8 v, int flags)
480	{	486	{
481	io_redirection_reg_t reg;	487	io_redirection_reg_t reg;
482	int dlvr = DELMOD_FIXED;	488	int dlvr = DELMOD_FIXED;
483		489
484	if (flags & LOPRI)	490	if (flags & LOPRI)
485	dlvr = DELMOD_LOWPRI;	491	dlvr = DELMOD_LOWPRI;
486		492
487	reg.lo = io_apic_read(IOREDTBL + pin*2);	493	reg.lo = io_apic_read(IOREDTBL + pin*2);
488	reg.hi = io_apic_read(IOREDTBL + pin*2 + 1);	494	reg.hi = io_apic_read(IOREDTBL + pin*2 + 1);
489		495
490	reg.dest = dest;	496	reg.dest = dest;
491	reg.destmod = DESTMOD_LOGIC;	497	reg.destmod = DESTMOD_LOGIC;
492	reg.trigger_mode = TRIGMOD_EDGE;	498	reg.trigger_mode = TRIGMOD_EDGE;

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(root)/trunk/kernel/arch/ia32/src/smp/apic.c @ 3880 – Rev 693 → 750