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1 | /* |
1 | /* |
2 | * Copyright (C) 2001-2004 Jakub Jermar |
2 | * Copyright (C) 2001-2004 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | #include <arch/types.h> |
29 | #include <arch/types.h> |
30 | #include <arch/smp/apic.h> |
30 | #include <arch/smp/apic.h> |
31 | #include <arch/smp/ap.h> |
31 | #include <arch/smp/ap.h> |
32 | #include <arch/smp/mps.h> |
32 | #include <arch/smp/mps.h> |
- | 33 | #include <arch/boot/boot.h> |
|
33 | #include <mm/page.h> |
34 | #include <mm/page.h> |
34 | #include <time/delay.h> |
35 | #include <time/delay.h> |
35 | #include <interrupt.h> |
36 | #include <interrupt.h> |
36 | #include <arch/interrupt.h> |
37 | #include <arch/interrupt.h> |
37 | #include <print.h> |
38 | #include <print.h> |
38 | #include <arch/asm.h> |
39 | #include <arch/asm.h> |
39 | #include <arch.h> |
40 | #include <arch.h> |
40 | 41 | ||
41 | #ifdef CONFIG_SMP |
42 | #ifdef CONFIG_SMP |
42 | 43 | ||
43 | /* |
44 | /* |
44 | * Advanced Programmable Interrupt Controller for SMP systems. |
45 | * Advanced Programmable Interrupt Controller for SMP systems. |
45 | * Tested on: |
46 | * Tested on: |
46 | * Bochs 2.0.2 - Bochs 2.2.5 with 2-8 CPUs |
47 | * Bochs 2.0.2 - Bochs 2.2.5 with 2-8 CPUs |
47 | * Simics 2.0.28 - Simics 2.2.19 2-15 CPUs |
48 | * Simics 2.0.28 - Simics 2.2.19 2-15 CPUs |
48 | * VMware Workstation 5.5 with 2 CPUs |
49 | * VMware Workstation 5.5 with 2 CPUs |
49 | * ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs |
50 | * ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs |
50 | * ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs |
51 | * ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs |
51 | * MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs |
52 | * MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs |
52 | */ |
53 | */ |
53 | 54 | ||
54 | /* |
55 | /* |
55 | * These variables either stay configured as initilalized, or are changed by |
56 | * These variables either stay configured as initilalized, or are changed by |
56 | * the MP configuration code. |
57 | * the MP configuration code. |
57 | * |
58 | * |
58 | * Pay special attention to the volatile keyword. Without it, gcc -O2 would |
59 | * Pay special attention to the volatile keyword. Without it, gcc -O2 would |
59 | * optimize the code too much and accesses to l_apic and io_apic, that must |
60 | * optimize the code too much and accesses to l_apic and io_apic, that must |
60 | * always be 32-bit, would use byte oriented instructions. |
61 | * always be 32-bit, would use byte oriented instructions. |
61 | */ |
62 | */ |
62 | volatile __u32 *l_apic = (__u32 *) 0xfee00000; |
63 | volatile __u32 *l_apic = (__u32 *) 0xfee00000; |
63 | volatile __u32 *io_apic = (__u32 *) 0xfec00000; |
64 | volatile __u32 *io_apic = (__u32 *) 0xfec00000; |
64 | 65 | ||
65 | __u32 apic_id_mask = 0; |
66 | __u32 apic_id_mask = 0; |
66 | 67 | ||
67 | static int apic_poll_errors(void); |
68 | static int apic_poll_errors(void); |
68 | 69 | ||
69 | #ifdef LAPIC_VERBOSE |
70 | #ifdef LAPIC_VERBOSE |
70 | static char *delmod_str[] = { |
71 | static char *delmod_str[] = { |
71 | "Fixed", |
72 | "Fixed", |
72 | "Lowest Priority", |
73 | "Lowest Priority", |
73 | "SMI", |
74 | "SMI", |
74 | "Reserved", |
75 | "Reserved", |
75 | "NMI", |
76 | "NMI", |
76 | "INIT", |
77 | "INIT", |
77 | "STARTUP", |
78 | "STARTUP", |
78 | "ExtInt" |
79 | "ExtInt" |
79 | }; |
80 | }; |
80 | 81 | ||
81 | static char *destmod_str[] = { |
82 | static char *destmod_str[] = { |
82 | "Physical", |
83 | "Physical", |
83 | "Logical" |
84 | "Logical" |
84 | }; |
85 | }; |
85 | 86 | ||
86 | static char *trigmod_str[] = { |
87 | static char *trigmod_str[] = { |
87 | "Edge", |
88 | "Edge", |
88 | "Level" |
89 | "Level" |
89 | }; |
90 | }; |
90 | 91 | ||
91 | static char *mask_str[] = { |
92 | static char *mask_str[] = { |
92 | "Unmasked", |
93 | "Unmasked", |
93 | "Masked" |
94 | "Masked" |
94 | }; |
95 | }; |
95 | 96 | ||
96 | static char *delivs_str[] = { |
97 | static char *delivs_str[] = { |
97 | "Idle", |
98 | "Idle", |
98 | "Send Pending" |
99 | "Send Pending" |
99 | }; |
100 | }; |
100 | 101 | ||
101 | static char *tm_mode_str[] = { |
102 | static char *tm_mode_str[] = { |
102 | "One-shot", |
103 | "One-shot", |
103 | "Periodic" |
104 | "Periodic" |
104 | }; |
105 | }; |
105 | 106 | ||
106 | static char *intpol_str[] = { |
107 | static char *intpol_str[] = { |
107 | "Polarity High", |
108 | "Polarity High", |
108 | "Polarity Low" |
109 | "Polarity Low" |
109 | }; |
110 | }; |
110 | #endif /* LAPIC_VERBOSE */ |
111 | #endif /* LAPIC_VERBOSE */ |
111 | 112 | ||
112 | 113 | ||
113 | static void apic_spurious(int n, void *stack); |
114 | static void apic_spurious(int n, void *stack); |
114 | static void l_apic_timer_interrupt(int n, void *stack); |
115 | static void l_apic_timer_interrupt(int n, void *stack); |
115 | 116 | ||
116 | /** Initialize APIC on BSP. */ |
117 | /** Initialize APIC on BSP. */ |
117 | void apic_init(void) |
118 | void apic_init(void) |
118 | { |
119 | { |
119 | io_apic_id_t idreg; |
120 | io_apic_id_t idreg; |
120 | int i; |
121 | int i; |
121 | 122 | ||
122 | exc_register(VECTOR_APIC_SPUR, "apic_spurious", apic_spurious); |
123 | exc_register(VECTOR_APIC_SPUR, "apic_spurious", apic_spurious); |
123 | 124 | ||
124 | enable_irqs_function = io_apic_enable_irqs; |
125 | enable_irqs_function = io_apic_enable_irqs; |
125 | disable_irqs_function = io_apic_disable_irqs; |
126 | disable_irqs_function = io_apic_disable_irqs; |
126 | eoi_function = l_apic_eoi; |
127 | eoi_function = l_apic_eoi; |
127 | 128 | ||
128 | /* |
129 | /* |
129 | * Configure interrupt routing. |
130 | * Configure interrupt routing. |
130 | * IRQ 0 remains masked as the time signal is generated by l_apic's themselves. |
131 | * IRQ 0 remains masked as the time signal is generated by l_apic's themselves. |
131 | * Other interrupts will be forwarded to the lowest priority CPU. |
132 | * Other interrupts will be forwarded to the lowest priority CPU. |
132 | */ |
133 | */ |
133 | io_apic_disable_irqs(0xffff); |
134 | io_apic_disable_irqs(0xffff); |
134 | exc_register(VECTOR_CLK, "l_apic_timer", l_apic_timer_interrupt); |
135 | exc_register(VECTOR_CLK, "l_apic_timer", l_apic_timer_interrupt); |
135 | for (i = 0; i < IRQ_COUNT; i++) { |
136 | for (i = 0; i < IRQ_COUNT; i++) { |
136 | int pin; |
137 | int pin; |
137 | 138 | ||
138 | if ((pin = smp_irq_to_pin(i)) != -1) { |
139 | if ((pin = smp_irq_to_pin(i)) != -1) { |
139 | io_apic_change_ioredtbl(pin, DEST_ALL, IVT_IRQBASE+i, LOPRI); |
140 | io_apic_change_ioredtbl(pin, DEST_ALL, IVT_IRQBASE+i, LOPRI); |
140 | } |
141 | } |
141 | } |
142 | } |
142 | 143 | ||
143 | /* |
144 | /* |
144 | * Ensure that io_apic has unique ID. |
145 | * Ensure that io_apic has unique ID. |
145 | */ |
146 | */ |
146 | idreg.value = io_apic_read(IOAPICID); |
147 | idreg.value = io_apic_read(IOAPICID); |
147 | if ((1<<idreg.apic_id) & apic_id_mask) { /* see if IO APIC ID is used already */ |
148 | if ((1<<idreg.apic_id) & apic_id_mask) { /* see if IO APIC ID is used already */ |
148 | for (i = 0; i < APIC_ID_COUNT; i++) { |
149 | for (i = 0; i < APIC_ID_COUNT; i++) { |
149 | if (!((1<<i) & apic_id_mask)) { |
150 | if (!((1<<i) & apic_id_mask)) { |
150 | idreg.apic_id = i; |
151 | idreg.apic_id = i; |
151 | io_apic_write(IOAPICID, idreg.value); |
152 | io_apic_write(IOAPICID, idreg.value); |
152 | break; |
153 | break; |
153 | } |
154 | } |
154 | } |
155 | } |
155 | } |
156 | } |
156 | 157 | ||
157 | /* |
158 | /* |
158 | * Configure the BSP's lapic. |
159 | * Configure the BSP's lapic. |
159 | */ |
160 | */ |
160 | l_apic_init(); |
161 | l_apic_init(); |
161 | 162 | ||
162 | l_apic_debug(); |
163 | l_apic_debug(); |
163 | } |
164 | } |
164 | 165 | ||
165 | /** APIC spurious interrupt handler. |
166 | /** APIC spurious interrupt handler. |
166 | * |
167 | * |
167 | * @param n Interrupt vector. |
168 | * @param n Interrupt vector. |
168 | * @param stack Interrupted stack. |
169 | * @param stack Interrupted stack. |
169 | */ |
170 | */ |
170 | void apic_spurious(int n, void *stack) |
171 | void apic_spurious(int n, void *stack) |
171 | { |
172 | { |
172 | printf("cpu%d: APIC spurious interrupt\n", CPU->id); |
173 | printf("cpu%d: APIC spurious interrupt\n", CPU->id); |
173 | } |
174 | } |
174 | 175 | ||
175 | /** Poll for APIC errors. |
176 | /** Poll for APIC errors. |
176 | * |
177 | * |
177 | * Examine Error Status Register and report all errors found. |
178 | * Examine Error Status Register and report all errors found. |
178 | * |
179 | * |
179 | * @return 0 on error, 1 on success. |
180 | * @return 0 on error, 1 on success. |
180 | */ |
181 | */ |
181 | int apic_poll_errors(void) |
182 | int apic_poll_errors(void) |
182 | { |
183 | { |
183 | esr_t esr; |
184 | esr_t esr; |
184 | 185 | ||
185 | esr.value = l_apic[ESR]; |
186 | esr.value = l_apic[ESR]; |
186 | 187 | ||
187 | if (esr.send_checksum_error) |
188 | if (esr.send_checksum_error) |
188 | printf("Send Checksum Error\n"); |
189 | printf("Send Checksum Error\n"); |
189 | if (esr.receive_checksum_error) |
190 | if (esr.receive_checksum_error) |
190 | printf("Receive Checksum Error\n"); |
191 | printf("Receive Checksum Error\n"); |
191 | if (esr.send_accept_error) |
192 | if (esr.send_accept_error) |
192 | printf("Send Accept Error\n"); |
193 | printf("Send Accept Error\n"); |
193 | if (esr.receive_accept_error) |
194 | if (esr.receive_accept_error) |
194 | printf("Receive Accept Error\n"); |
195 | printf("Receive Accept Error\n"); |
195 | if (esr.send_illegal_vector) |
196 | if (esr.send_illegal_vector) |
196 | printf("Send Illegal Vector\n"); |
197 | printf("Send Illegal Vector\n"); |
197 | if (esr.received_illegal_vector) |
198 | if (esr.received_illegal_vector) |
198 | printf("Received Illegal Vector\n"); |
199 | printf("Received Illegal Vector\n"); |
199 | if (esr.illegal_register_address) |
200 | if (esr.illegal_register_address) |
200 | printf("Illegal Register Address\n"); |
201 | printf("Illegal Register Address\n"); |
201 | 202 | ||
202 | return !esr.err_bitmap; |
203 | return !esr.err_bitmap; |
203 | } |
204 | } |
204 | 205 | ||
205 | /** Send all CPUs excluding CPU IPI vector. |
206 | /** Send all CPUs excluding CPU IPI vector. |
206 | * |
207 | * |
207 | * @param vector Interrupt vector to be sent. |
208 | * @param vector Interrupt vector to be sent. |
208 | * |
209 | * |
209 | * @return 0 on failure, 1 on success. |
210 | * @return 0 on failure, 1 on success. |
210 | */ |
211 | */ |
211 | int l_apic_broadcast_custom_ipi(__u8 vector) |
212 | int l_apic_broadcast_custom_ipi(__u8 vector) |
212 | { |
213 | { |
213 | icr_t icr; |
214 | icr_t icr; |
214 | 215 | ||
215 | icr.lo = l_apic[ICRlo]; |
216 | icr.lo = l_apic[ICRlo]; |
216 | icr.delmod = DELMOD_FIXED; |
217 | icr.delmod = DELMOD_FIXED; |
217 | icr.destmod = DESTMOD_LOGIC; |
218 | icr.destmod = DESTMOD_LOGIC; |
218 | icr.level = LEVEL_ASSERT; |
219 | icr.level = LEVEL_ASSERT; |
219 | icr.shorthand = SHORTHAND_ALL_EXCL; |
220 | icr.shorthand = SHORTHAND_ALL_EXCL; |
220 | icr.trigger_mode = TRIGMOD_LEVEL; |
221 | icr.trigger_mode = TRIGMOD_LEVEL; |
221 | icr.vector = vector; |
222 | icr.vector = vector; |
222 | 223 | ||
223 | l_apic[ICRlo] = icr.lo; |
224 | l_apic[ICRlo] = icr.lo; |
224 | 225 | ||
225 | icr.lo = l_apic[ICRlo]; |
226 | icr.lo = l_apic[ICRlo]; |
226 | if (icr.delivs == DELIVS_PENDING) |
227 | if (icr.delivs == DELIVS_PENDING) |
227 | printf("IPI is pending.\n"); |
228 | printf("IPI is pending.\n"); |
228 | 229 | ||
229 | return apic_poll_errors(); |
230 | return apic_poll_errors(); |
230 | } |
231 | } |
231 | 232 | ||
232 | /** Universal Start-up Algorithm for bringing up the AP processors. |
233 | /** Universal Start-up Algorithm for bringing up the AP processors. |
233 | * |
234 | * |
234 | * @param apicid APIC ID of the processor to be brought up. |
235 | * @param apicid APIC ID of the processor to be brought up. |
235 | * |
236 | * |
236 | * @return 0 on failure, 1 on success. |
237 | * @return 0 on failure, 1 on success. |
237 | */ |
238 | */ |
238 | int l_apic_send_init_ipi(__u8 apicid) |
239 | int l_apic_send_init_ipi(__u8 apicid) |
239 | { |
240 | { |
240 | icr_t icr; |
241 | icr_t icr; |
241 | int i; |
242 | int i; |
242 | 243 | ||
243 | /* |
244 | /* |
244 | * Read the ICR register in and zero all non-reserved fields. |
245 | * Read the ICR register in and zero all non-reserved fields. |
245 | */ |
246 | */ |
246 | icr.lo = l_apic[ICRlo]; |
247 | icr.lo = l_apic[ICRlo]; |
247 | icr.hi = l_apic[ICRhi]; |
248 | icr.hi = l_apic[ICRhi]; |
248 | 249 | ||
249 | icr.delmod = DELMOD_INIT; |
250 | icr.delmod = DELMOD_INIT; |
250 | icr.destmod = DESTMOD_PHYS; |
251 | icr.destmod = DESTMOD_PHYS; |
251 | icr.level = LEVEL_ASSERT; |
252 | icr.level = LEVEL_ASSERT; |
252 | icr.trigger_mode = TRIGMOD_LEVEL; |
253 | icr.trigger_mode = TRIGMOD_LEVEL; |
253 | icr.shorthand = SHORTHAND_NONE; |
254 | icr.shorthand = SHORTHAND_NONE; |
254 | icr.vector = 0; |
255 | icr.vector = 0; |
255 | icr.dest = apicid; |
256 | icr.dest = apicid; |
256 | 257 | ||
257 | l_apic[ICRhi] = icr.hi; |
258 | l_apic[ICRhi] = icr.hi; |
258 | l_apic[ICRlo] = icr.lo; |
259 | l_apic[ICRlo] = icr.lo; |
259 | 260 | ||
260 | /* |
261 | /* |
261 | * According to MP Specification, 20us should be enough to |
262 | * According to MP Specification, 20us should be enough to |
262 | * deliver the IPI. |
263 | * deliver the IPI. |
263 | */ |
264 | */ |
264 | delay(20); |
265 | delay(20); |
265 | 266 | ||
266 | if (!apic_poll_errors()) return 0; |
267 | if (!apic_poll_errors()) return 0; |
267 | 268 | ||
268 | icr.lo = l_apic[ICRlo]; |
269 | icr.lo = l_apic[ICRlo]; |
269 | if (icr.delivs == DELIVS_PENDING) |
270 | if (icr.delivs == DELIVS_PENDING) |
270 | printf("IPI is pending.\n"); |
271 | printf("IPI is pending.\n"); |
271 | 272 | ||
272 | icr.delmod = DELMOD_INIT; |
273 | icr.delmod = DELMOD_INIT; |
273 | icr.destmod = DESTMOD_PHYS; |
274 | icr.destmod = DESTMOD_PHYS; |
274 | icr.level = LEVEL_DEASSERT; |
275 | icr.level = LEVEL_DEASSERT; |
275 | icr.shorthand = SHORTHAND_NONE; |
276 | icr.shorthand = SHORTHAND_NONE; |
276 | icr.trigger_mode = TRIGMOD_LEVEL; |
277 | icr.trigger_mode = TRIGMOD_LEVEL; |
277 | icr.vector = 0; |
278 | icr.vector = 0; |
278 | l_apic[ICRlo] = icr.lo; |
279 | l_apic[ICRlo] = icr.lo; |
279 | 280 | ||
280 | /* |
281 | /* |
281 | * Wait 10ms as MP Specification specifies. |
282 | * Wait 10ms as MP Specification specifies. |
282 | */ |
283 | */ |
283 | delay(10000); |
284 | delay(10000); |
284 | 285 | ||
285 | if (!is_82489DX_apic(l_apic[LAVR])) { |
286 | if (!is_82489DX_apic(l_apic[LAVR])) { |
286 | /* |
287 | /* |
287 | * If this is not 82489DX-based l_apic we must send two STARTUP IPI's. |
288 | * If this is not 82489DX-based l_apic we must send two STARTUP IPI's. |
288 | */ |
289 | */ |
289 | for (i = 0; i<2; i++) { |
290 | for (i = 0; i<2; i++) { |
290 | icr.lo = l_apic[ICRlo]; |
291 | icr.lo = l_apic[ICRlo]; |
291 | icr.vector = ((__address) ap_boot) / 4096; /* calculate the reset vector */ |
292 | icr.vector = ((__address) ap_boot) / 4096; /* calculate the reset vector */ |
292 | icr.delmod = DELMOD_STARTUP; |
293 | icr.delmod = DELMOD_STARTUP; |
293 | icr.destmod = DESTMOD_PHYS; |
294 | icr.destmod = DESTMOD_PHYS; |
294 | icr.level = LEVEL_ASSERT; |
295 | icr.level = LEVEL_ASSERT; |
295 | icr.shorthand = SHORTHAND_NONE; |
296 | icr.shorthand = SHORTHAND_NONE; |
296 | icr.trigger_mode = TRIGMOD_LEVEL; |
297 | icr.trigger_mode = TRIGMOD_LEVEL; |
297 | l_apic[ICRlo] = icr.lo; |
298 | l_apic[ICRlo] = icr.lo; |
298 | delay(200); |
299 | delay(200); |
299 | } |
300 | } |
300 | } |
301 | } |
301 | 302 | ||
302 | return apic_poll_errors(); |
303 | return apic_poll_errors(); |
303 | } |
304 | } |
304 | 305 | ||
305 | /** Initialize Local APIC. */ |
306 | /** Initialize Local APIC. */ |
306 | void l_apic_init(void) |
307 | void l_apic_init(void) |
307 | { |
308 | { |
308 | lvt_error_t error; |
309 | lvt_error_t error; |
309 | lvt_lint_t lint; |
310 | lvt_lint_t lint; |
310 | svr_t svr; |
311 | svr_t svr; |
311 | icr_t icr; |
312 | icr_t icr; |
312 | tdcr_t tdcr; |
313 | tdcr_t tdcr; |
313 | lvt_tm_t tm; |
314 | lvt_tm_t tm; |
314 | ldr_t ldr; |
315 | ldr_t ldr; |
315 | dfr_t dfr; |
316 | dfr_t dfr; |
316 | __u32 t1, t2; |
317 | __u32 t1, t2; |
317 | 318 | ||
318 | /* Initialize LVT Error register. */ |
319 | /* Initialize LVT Error register. */ |
319 | error.value = l_apic[LVT_Err]; |
320 | error.value = l_apic[LVT_Err]; |
320 | error.masked = true; |
321 | error.masked = true; |
321 | l_apic[LVT_Err] = error.value; |
322 | l_apic[LVT_Err] = error.value; |
322 | 323 | ||
323 | /* Initialize LVT LINT0 register. */ |
324 | /* Initialize LVT LINT0 register. */ |
324 | lint.value = l_apic[LVT_LINT0]; |
325 | lint.value = l_apic[LVT_LINT0]; |
325 | lint.masked = true; |
326 | lint.masked = true; |
326 | l_apic[LVT_LINT0] = lint.value; |
327 | l_apic[LVT_LINT0] = lint.value; |
327 | 328 | ||
328 | /* Initialize LVT LINT1 register. */ |
329 | /* Initialize LVT LINT1 register. */ |
329 | lint.value = l_apic[LVT_LINT1]; |
330 | lint.value = l_apic[LVT_LINT1]; |
330 | lint.masked = true; |
331 | lint.masked = true; |
331 | l_apic[LVT_LINT1] = lint.value; |
332 | l_apic[LVT_LINT1] = lint.value; |
332 | 333 | ||
333 | /* Spurious-Interrupt Vector Register initialization. */ |
334 | /* Spurious-Interrupt Vector Register initialization. */ |
334 | svr.value = l_apic[SVR]; |
335 | svr.value = l_apic[SVR]; |
335 | svr.vector = VECTOR_APIC_SPUR; |
336 | svr.vector = VECTOR_APIC_SPUR; |
336 | svr.lapic_enabled = true; |
337 | svr.lapic_enabled = true; |
337 | l_apic[SVR] = svr.value; |
338 | l_apic[SVR] = svr.value; |
338 | 339 | ||
339 | l_apic[TPR] &= TPRClear; |
340 | l_apic[TPR] &= TPRClear; |
340 | 341 | ||
341 | if (CPU->arch.family >= 6) |
342 | if (CPU->arch.family >= 6) |
342 | enable_l_apic_in_msr(); |
343 | enable_l_apic_in_msr(); |
343 | 344 | ||
344 | /* Interrupt Command Register initialization. */ |
345 | /* Interrupt Command Register initialization. */ |
345 | icr.lo = l_apic[ICRlo]; |
346 | icr.lo = l_apic[ICRlo]; |
346 | icr.delmod = DELMOD_INIT; |
347 | icr.delmod = DELMOD_INIT; |
347 | icr.destmod = DESTMOD_PHYS; |
348 | icr.destmod = DESTMOD_PHYS; |
348 | icr.level = LEVEL_DEASSERT; |
349 | icr.level = LEVEL_DEASSERT; |
349 | icr.shorthand = SHORTHAND_ALL_INCL; |
350 | icr.shorthand = SHORTHAND_ALL_INCL; |
350 | icr.trigger_mode = TRIGMOD_LEVEL; |
351 | icr.trigger_mode = TRIGMOD_LEVEL; |
351 | l_apic[ICRlo] = icr.lo; |
352 | l_apic[ICRlo] = icr.lo; |
352 | 353 | ||
353 | /* Timer Divide Configuration Register initialization. */ |
354 | /* Timer Divide Configuration Register initialization. */ |
354 | tdcr.value = l_apic[TDCR]; |
355 | tdcr.value = l_apic[TDCR]; |
355 | tdcr.div_value = DIVIDE_1; |
356 | tdcr.div_value = DIVIDE_1; |
356 | l_apic[TDCR] = tdcr.value; |
357 | l_apic[TDCR] = tdcr.value; |
357 | 358 | ||
358 | /* Program local timer. */ |
359 | /* Program local timer. */ |
359 | tm.value = l_apic[LVT_Tm]; |
360 | tm.value = l_apic[LVT_Tm]; |
360 | tm.vector = VECTOR_CLK; |
361 | tm.vector = VECTOR_CLK; |
361 | tm.mode = TIMER_PERIODIC; |
362 | tm.mode = TIMER_PERIODIC; |
362 | tm.masked = false; |
363 | tm.masked = false; |
363 | l_apic[LVT_Tm] = tm.value; |
364 | l_apic[LVT_Tm] = tm.value; |
364 | 365 | ||
365 | /* Measure and configure the timer to generate timer interrupt each ms. */ |
366 | /* Measure and configure the timer to generate timer interrupt each ms. */ |
366 | t1 = l_apic[CCRT]; |
367 | t1 = l_apic[CCRT]; |
367 | l_apic[ICRT] = 0xffffffff; |
368 | l_apic[ICRT] = 0xffffffff; |
368 | 369 | ||
369 | while (l_apic[CCRT] == t1) |
370 | while (l_apic[CCRT] == t1) |
370 | ; |
371 | ; |
371 | 372 | ||
372 | t1 = l_apic[CCRT]; |
373 | t1 = l_apic[CCRT]; |
373 | delay(1000); |
374 | delay(1000); |
374 | t2 = l_apic[CCRT]; |
375 | t2 = l_apic[CCRT]; |
375 | 376 | ||
376 | l_apic[ICRT] = t1-t2; |
377 | l_apic[ICRT] = t1-t2; |
377 | 378 | ||
378 | /* Program Logical Destination Register. */ |
379 | /* Program Logical Destination Register. */ |
379 | ldr.value = l_apic[LDR]; |
380 | ldr.value = l_apic[LDR]; |
380 | if (CPU->id < sizeof(CPU->id)*8) /* size in bits */ |
381 | if (CPU->id < sizeof(CPU->id)*8) /* size in bits */ |
381 | ldr.id = (1<<CPU->id); |
382 | ldr.id = (1<<CPU->id); |
382 | l_apic[LDR] = ldr.value; |
383 | l_apic[LDR] = ldr.value; |
383 | 384 | ||
384 | /* Program Destination Format Register for Flat mode. */ |
385 | /* Program Destination Format Register for Flat mode. */ |
385 | dfr.value = l_apic[DFR]; |
386 | dfr.value = l_apic[DFR]; |
386 | dfr.model = MODEL_FLAT; |
387 | dfr.model = MODEL_FLAT; |
387 | l_apic[DFR] = dfr.value; |
388 | l_apic[DFR] = dfr.value; |
388 | } |
389 | } |
389 | 390 | ||
390 | /** Local APIC End of Interrupt. */ |
391 | /** Local APIC End of Interrupt. */ |
391 | void l_apic_eoi(void) |
392 | void l_apic_eoi(void) |
392 | { |
393 | { |
393 | l_apic[EOI] = 0; |
394 | l_apic[EOI] = 0; |
394 | } |
395 | } |
395 | 396 | ||
396 | /** Dump content of Local APIC registers. */ |
397 | /** Dump content of Local APIC registers. */ |
397 | void l_apic_debug(void) |
398 | void l_apic_debug(void) |
398 | { |
399 | { |
399 | #ifdef LAPIC_VERBOSE |
400 | #ifdef LAPIC_VERBOSE |
400 | lvt_tm_t tm; |
401 | lvt_tm_t tm; |
401 | lvt_lint_t lint; |
402 | lvt_lint_t lint; |
402 | lvt_error_t error; |
403 | lvt_error_t error; |
403 | 404 | ||
404 | printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id()); |
405 | printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id()); |
405 | 406 | ||
406 | tm.value = l_apic[LVT_Tm]; |
407 | tm.value = l_apic[LVT_Tm]; |
407 | printf("LVT Tm: vector=%B, %s, %s, %s\n", tm.vector, delivs_str[tm.delivs], mask_str[tm.masked], tm_mode_str[tm.mode]); |
408 | printf("LVT Tm: vector=%B, %s, %s, %s\n", tm.vector, delivs_str[tm.delivs], mask_str[tm.masked], tm_mode_str[tm.mode]); |
408 | lint.value = l_apic[LVT_LINT0]; |
409 | lint.value = l_apic[LVT_LINT0]; |
409 | printf("LVT LINT0: vector=%B, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]); |
410 | printf("LVT LINT0: vector=%B, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]); |
410 | lint.value = l_apic[LVT_LINT1]; |
411 | lint.value = l_apic[LVT_LINT1]; |
411 | printf("LVT LINT1: vector=%B, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]); |
412 | printf("LVT LINT1: vector=%B, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]); |
412 | error.value = l_apic[LVT_Err]; |
413 | error.value = l_apic[LVT_Err]; |
413 | printf("LVT Err: vector=%B, %s, %s\n", error.vector, delivs_str[error.delivs], mask_str[error.masked]); |
414 | printf("LVT Err: vector=%B, %s, %s\n", error.vector, delivs_str[error.delivs], mask_str[error.masked]); |
414 | #endif |
415 | #endif |
415 | } |
416 | } |
416 | 417 | ||
417 | /** Local APIC Timer Interrupt. |
418 | /** Local APIC Timer Interrupt. |
418 | * |
419 | * |
419 | * @param n Interrupt vector number. |
420 | * @param n Interrupt vector number. |
420 | * @param stack Interrupted stack. |
421 | * @param stack Interrupted stack. |
421 | */ |
422 | */ |
422 | void l_apic_timer_interrupt(int n, void *stack) |
423 | void l_apic_timer_interrupt(int n, void *stack) |
423 | { |
424 | { |
424 | l_apic_eoi(); |
425 | l_apic_eoi(); |
425 | clock(); |
426 | clock(); |
426 | } |
427 | } |
427 | 428 | ||
428 | /** Get Local APIC ID. |
429 | /** Get Local APIC ID. |
429 | * |
430 | * |
430 | * @return Local APIC ID. |
431 | * @return Local APIC ID. |
431 | */ |
432 | */ |
432 | __u8 l_apic_id(void) |
433 | __u8 l_apic_id(void) |
433 | { |
434 | { |
434 | l_apic_id_t idreg; |
435 | l_apic_id_t idreg; |
435 | 436 | ||
436 | idreg.value = l_apic[L_APIC_ID]; |
437 | idreg.value = l_apic[L_APIC_ID]; |
437 | return idreg.apic_id; |
438 | return idreg.apic_id; |
438 | } |
439 | } |
439 | 440 | ||
440 | /** Read from IO APIC register. |
441 | /** Read from IO APIC register. |
441 | * |
442 | * |
442 | * @param address IO APIC register address. |
443 | * @param address IO APIC register address. |
443 | * |
444 | * |
444 | * @return Content of the addressed IO APIC register. |
445 | * @return Content of the addressed IO APIC register. |
445 | */ |
446 | */ |
446 | __u32 io_apic_read(__u8 address) |
447 | __u32 io_apic_read(__u8 address) |
447 | { |
448 | { |
448 | io_regsel_t regsel; |
449 | io_regsel_t regsel; |
449 | 450 | ||
450 | regsel.value = io_apic[IOREGSEL]; |
451 | regsel.value = io_apic[IOREGSEL]; |
451 | regsel.reg_addr = address; |
452 | regsel.reg_addr = address; |
452 | io_apic[IOREGSEL] = regsel.value; |
453 | io_apic[IOREGSEL] = regsel.value; |
453 | return io_apic[IOWIN]; |
454 | return io_apic[IOWIN]; |
454 | } |
455 | } |
455 | 456 | ||
456 | /** Write to IO APIC register. |
457 | /** Write to IO APIC register. |
457 | * |
458 | * |
458 | * @param address IO APIC register address. |
459 | * @param address IO APIC register address. |
459 | * @param Content to be written to the addressed IO APIC register. |
460 | * @param Content to be written to the addressed IO APIC register. |
460 | */ |
461 | */ |
461 | void io_apic_write(__u8 address, __u32 x) |
462 | void io_apic_write(__u8 address, __u32 x) |
462 | { |
463 | { |
463 | io_regsel_t regsel; |
464 | io_regsel_t regsel; |
464 | 465 | ||
465 | regsel.value = io_apic[IOREGSEL]; |
466 | regsel.value = io_apic[IOREGSEL]; |
466 | regsel.reg_addr = address; |
467 | regsel.reg_addr = address; |
467 | io_apic[IOREGSEL] = regsel.value; |
468 | io_apic[IOREGSEL] = regsel.value; |
468 | io_apic[IOWIN] = x; |
469 | io_apic[IOWIN] = x; |
469 | } |
470 | } |
470 | 471 | ||
471 | /** Change some attributes of one item in I/O Redirection Table. |
472 | /** Change some attributes of one item in I/O Redirection Table. |
472 | * |
473 | * |
473 | * @param pin IO APIC pin number. |
474 | * @param pin IO APIC pin number. |
474 | * @param dest Interrupt destination address. |
475 | * @param dest Interrupt destination address. |
475 | * @param v Interrupt vector to trigger. |
476 | * @param v Interrupt vector to trigger. |
476 | * @param flags Flags. |
477 | * @param flags Flags. |
477 | */ |
478 | */ |
478 | void io_apic_change_ioredtbl(int pin, int dest, __u8 v, int flags) |
479 | void io_apic_change_ioredtbl(int pin, int dest, __u8 v, int flags) |
479 | { |
480 | { |
480 | io_redirection_reg_t reg; |
481 | io_redirection_reg_t reg; |
481 | int dlvr = DELMOD_FIXED; |
482 | int dlvr = DELMOD_FIXED; |
482 | 483 | ||
483 | if (flags & LOPRI) |
484 | if (flags & LOPRI) |
484 | dlvr = DELMOD_LOWPRI; |
485 | dlvr = DELMOD_LOWPRI; |
485 | 486 | ||
486 | reg.lo = io_apic_read(IOREDTBL + pin*2); |
487 | reg.lo = io_apic_read(IOREDTBL + pin*2); |
487 | reg.hi = io_apic_read(IOREDTBL + pin*2 + 1); |
488 | reg.hi = io_apic_read(IOREDTBL + pin*2 + 1); |
488 | 489 | ||
489 | reg.dest = dest; |
490 | reg.dest = dest; |
490 | reg.destmod = DESTMOD_LOGIC; |
491 | reg.destmod = DESTMOD_LOGIC; |
491 | reg.trigger_mode = TRIGMOD_EDGE; |
492 | reg.trigger_mode = TRIGMOD_EDGE; |
492 | reg.intpol = POLARITY_HIGH; |
493 | reg.intpol = POLARITY_HIGH; |
493 | reg.delmod = dlvr; |
494 | reg.delmod = dlvr; |
494 | reg.intvec = v; |
495 | reg.intvec = v; |
495 | 496 | ||
496 | io_apic_write(IOREDTBL + pin*2, reg.lo); |
497 | io_apic_write(IOREDTBL + pin*2, reg.lo); |
497 | io_apic_write(IOREDTBL + pin*2 + 1, reg.hi); |
498 | io_apic_write(IOREDTBL + pin*2 + 1, reg.hi); |
498 | } |
499 | } |
499 | 500 | ||
500 | /** Mask IRQs in IO APIC. |
501 | /** Mask IRQs in IO APIC. |
501 | * |
502 | * |
502 | * @param irqmask Bitmask of IRQs to be masked (0 = do not mask, 1 = mask). |
503 | * @param irqmask Bitmask of IRQs to be masked (0 = do not mask, 1 = mask). |
503 | */ |
504 | */ |
504 | void io_apic_disable_irqs(__u16 irqmask) |
505 | void io_apic_disable_irqs(__u16 irqmask) |
505 | { |
506 | { |
506 | io_redirection_reg_t reg; |
507 | io_redirection_reg_t reg; |
507 | int i, pin; |
508 | int i, pin; |
508 | 509 | ||
509 | for (i=0;i<16;i++) { |
510 | for (i=0;i<16;i++) { |
510 | if (irqmask & (1<<i)) { |
511 | if (irqmask & (1<<i)) { |
511 | /* |
512 | /* |
512 | * Mask the signal input in IO APIC if there is a |
513 | * Mask the signal input in IO APIC if there is a |
513 | * mapping for the respective IRQ number. |
514 | * mapping for the respective IRQ number. |
514 | */ |
515 | */ |
515 | pin = smp_irq_to_pin(i); |
516 | pin = smp_irq_to_pin(i); |
516 | if (pin != -1) { |
517 | if (pin != -1) { |
517 | reg.lo = io_apic_read(IOREDTBL + pin*2); |
518 | reg.lo = io_apic_read(IOREDTBL + pin*2); |
518 | reg.masked = true; |
519 | reg.masked = true; |
519 | io_apic_write(IOREDTBL + pin*2, reg.lo); |
520 | io_apic_write(IOREDTBL + pin*2, reg.lo); |
520 | } |
521 | } |
521 | 522 | ||
522 | } |
523 | } |
523 | } |
524 | } |
524 | } |
525 | } |
525 | 526 | ||
526 | /** Unmask IRQs in IO APIC. |
527 | /** Unmask IRQs in IO APIC. |
527 | * |
528 | * |
528 | * @param irqmask Bitmask of IRQs to be unmasked (0 = do not unmask, 1 = unmask). |
529 | * @param irqmask Bitmask of IRQs to be unmasked (0 = do not unmask, 1 = unmask). |
529 | */ |
530 | */ |
530 | void io_apic_enable_irqs(__u16 irqmask) |
531 | void io_apic_enable_irqs(__u16 irqmask) |
531 | { |
532 | { |
532 | int i, pin; |
533 | int i, pin; |
533 | io_redirection_reg_t reg; |
534 | io_redirection_reg_t reg; |
534 | 535 | ||
535 | for (i=0;i<16;i++) { |
536 | for (i=0;i<16;i++) { |
536 | if (irqmask & (1<<i)) { |
537 | if (irqmask & (1<<i)) { |
537 | /* |
538 | /* |
538 | * Unmask the signal input in IO APIC if there is a |
539 | * Unmask the signal input in IO APIC if there is a |
539 | * mapping for the respective IRQ number. |
540 | * mapping for the respective IRQ number. |
540 | */ |
541 | */ |
541 | pin = smp_irq_to_pin(i); |
542 | pin = smp_irq_to_pin(i); |
542 | if (pin != -1) { |
543 | if (pin != -1) { |
543 | reg.lo = io_apic_read(IOREDTBL + pin*2); |
544 | reg.lo = io_apic_read(IOREDTBL + pin*2); |
544 | reg.masked = false; |
545 | reg.masked = false; |
545 | io_apic_write(IOREDTBL + pin*2, reg.lo); |
546 | io_apic_write(IOREDTBL + pin*2, reg.lo); |
546 | } |
547 | } |
547 | 548 | ||
548 | } |
549 | } |
549 | } |
550 | } |
550 | } |
551 | } |
551 | 552 | ||
552 | #endif /* CONFIG_SMP */ |
553 | #endif /* CONFIG_SMP */ |
553 | 554 |