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1 | /* |
1 | /* |
2 | * Copyright (C) 2001-2004 Jakub Jermar |
2 | * Copyright (C) 2001-2004 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
- | 29 | /** @addtogroup ia32 |
|
- | 30 | * @{ |
|
- | 31 | */ |
|
- | 32 | /** @file |
|
- | 33 | */ |
|
- | 34 | ||
29 | #ifndef __APIC_H__ |
35 | #ifndef __APIC_H__ |
30 | #define __APIC_H__ |
36 | #define __APIC_H__ |
31 | 37 | ||
32 | #include <arch/types.h> |
38 | #include <arch/types.h> |
33 | #include <cpu.h> |
39 | #include <cpu.h> |
34 | 40 | ||
35 | #define FIXED (0<<0) |
41 | #define FIXED (0<<0) |
36 | #define LOPRI (1<<0) |
42 | #define LOPRI (1<<0) |
37 | 43 | ||
38 | #define APIC_ID_COUNT 16 |
44 | #define APIC_ID_COUNT 16 |
39 | 45 | ||
40 | /* local APIC macros */ |
46 | /* local APIC macros */ |
41 | #define IPI_INIT 0 |
47 | #define IPI_INIT 0 |
42 | #define IPI_STARTUP 0 |
48 | #define IPI_STARTUP 0 |
43 | 49 | ||
44 | /** Delivery modes. */ |
50 | /** Delivery modes. */ |
45 | #define DELMOD_FIXED 0x0 |
51 | #define DELMOD_FIXED 0x0 |
46 | #define DELMOD_LOWPRI 0x1 |
52 | #define DELMOD_LOWPRI 0x1 |
47 | #define DELMOD_SMI 0x2 |
53 | #define DELMOD_SMI 0x2 |
48 | /* 0x3 reserved */ |
54 | /* 0x3 reserved */ |
49 | #define DELMOD_NMI 0x4 |
55 | #define DELMOD_NMI 0x4 |
50 | #define DELMOD_INIT 0x5 |
56 | #define DELMOD_INIT 0x5 |
51 | #define DELMOD_STARTUP 0x6 |
57 | #define DELMOD_STARTUP 0x6 |
52 | #define DELMOD_EXTINT 0x7 |
58 | #define DELMOD_EXTINT 0x7 |
53 | 59 | ||
54 | /** Destination modes. */ |
60 | /** Destination modes. */ |
55 | #define DESTMOD_PHYS 0x0 |
61 | #define DESTMOD_PHYS 0x0 |
56 | #define DESTMOD_LOGIC 0x1 |
62 | #define DESTMOD_LOGIC 0x1 |
57 | 63 | ||
58 | /** Trigger Modes. */ |
64 | /** Trigger Modes. */ |
59 | #define TRIGMOD_EDGE 0x0 |
65 | #define TRIGMOD_EDGE 0x0 |
60 | #define TRIGMOD_LEVEL 0x1 |
66 | #define TRIGMOD_LEVEL 0x1 |
61 | 67 | ||
62 | /** Levels. */ |
68 | /** Levels. */ |
63 | #define LEVEL_DEASSERT 0x0 |
69 | #define LEVEL_DEASSERT 0x0 |
64 | #define LEVEL_ASSERT 0x1 |
70 | #define LEVEL_ASSERT 0x1 |
65 | 71 | ||
66 | /** Destination Shorthands. */ |
72 | /** Destination Shorthands. */ |
67 | #define SHORTHAND_NONE 0x0 |
73 | #define SHORTHAND_NONE 0x0 |
68 | #define SHORTHAND_SELF 0x1 |
74 | #define SHORTHAND_SELF 0x1 |
69 | #define SHORTHAND_ALL_INCL 0x2 |
75 | #define SHORTHAND_ALL_INCL 0x2 |
70 | #define SHORTHAND_ALL_EXCL 0x3 |
76 | #define SHORTHAND_ALL_EXCL 0x3 |
71 | 77 | ||
72 | /** Interrupt Input Pin Polarities. */ |
78 | /** Interrupt Input Pin Polarities. */ |
73 | #define POLARITY_HIGH 0x0 |
79 | #define POLARITY_HIGH 0x0 |
74 | #define POLARITY_LOW 0x1 |
80 | #define POLARITY_LOW 0x1 |
75 | 81 | ||
76 | /** Divide Values. (Bit 2 is always 0) */ |
82 | /** Divide Values. (Bit 2 is always 0) */ |
77 | #define DIVIDE_2 0x0 |
83 | #define DIVIDE_2 0x0 |
78 | #define DIVIDE_4 0x1 |
84 | #define DIVIDE_4 0x1 |
79 | #define DIVIDE_8 0x2 |
85 | #define DIVIDE_8 0x2 |
80 | #define DIVIDE_16 0x3 |
86 | #define DIVIDE_16 0x3 |
81 | #define DIVIDE_32 0x8 |
87 | #define DIVIDE_32 0x8 |
82 | #define DIVIDE_64 0x9 |
88 | #define DIVIDE_64 0x9 |
83 | #define DIVIDE_128 0xa |
89 | #define DIVIDE_128 0xa |
84 | #define DIVIDE_1 0xb |
90 | #define DIVIDE_1 0xb |
85 | 91 | ||
86 | /** Timer Modes. */ |
92 | /** Timer Modes. */ |
87 | #define TIMER_ONESHOT 0x0 |
93 | #define TIMER_ONESHOT 0x0 |
88 | #define TIMER_PERIODIC 0x1 |
94 | #define TIMER_PERIODIC 0x1 |
89 | 95 | ||
90 | /** Delivery status. */ |
96 | /** Delivery status. */ |
91 | #define DELIVS_IDLE 0x0 |
97 | #define DELIVS_IDLE 0x0 |
92 | #define DELIVS_PENDING 0x1 |
98 | #define DELIVS_PENDING 0x1 |
93 | 99 | ||
94 | /** Destination masks. */ |
100 | /** Destination masks. */ |
95 | #define DEST_ALL 0xff |
101 | #define DEST_ALL 0xff |
96 | 102 | ||
97 | /** Dest format models. */ |
103 | /** Dest format models. */ |
98 | #define MODEL_FLAT 0xf |
104 | #define MODEL_FLAT 0xf |
99 | #define MODEL_CLUSTER 0x0 |
105 | #define MODEL_CLUSTER 0x0 |
100 | 106 | ||
101 | /** Interrupt Command Register. */ |
107 | /** Interrupt Command Register. */ |
102 | #define ICRlo (0x300/sizeof(__u32)) |
108 | #define ICRlo (0x300/sizeof(__u32)) |
103 | #define ICRhi (0x310/sizeof(__u32)) |
109 | #define ICRhi (0x310/sizeof(__u32)) |
104 | struct icr { |
110 | struct icr { |
105 | union { |
111 | union { |
106 | __u32 lo; |
112 | __u32 lo; |
107 | struct { |
113 | struct { |
108 | __u8 vector; /**< Interrupt Vector. */ |
114 | __u8 vector; /**< Interrupt Vector. */ |
109 | unsigned delmod : 3; /**< Delivery Mode. */ |
115 | unsigned delmod : 3; /**< Delivery Mode. */ |
110 | unsigned destmod : 1; /**< Destination Mode. */ |
116 | unsigned destmod : 1; /**< Destination Mode. */ |
111 | unsigned delivs : 1; /**< Delivery status (RO). */ |
117 | unsigned delivs : 1; /**< Delivery status (RO). */ |
112 | unsigned : 1; /**< Reserved. */ |
118 | unsigned : 1; /**< Reserved. */ |
113 | unsigned level : 1; /**< Level. */ |
119 | unsigned level : 1; /**< Level. */ |
114 | unsigned trigger_mode : 1; /**< Trigger Mode. */ |
120 | unsigned trigger_mode : 1; /**< Trigger Mode. */ |
115 | unsigned : 2; /**< Reserved. */ |
121 | unsigned : 2; /**< Reserved. */ |
116 | unsigned shorthand : 2; /**< Destination Shorthand. */ |
122 | unsigned shorthand : 2; /**< Destination Shorthand. */ |
117 | unsigned : 12; /**< Reserved. */ |
123 | unsigned : 12; /**< Reserved. */ |
118 | } __attribute__ ((packed)); |
124 | } __attribute__ ((packed)); |
119 | }; |
125 | }; |
120 | union { |
126 | union { |
121 | __u32 hi; |
127 | __u32 hi; |
122 | struct { |
128 | struct { |
123 | unsigned : 24; /**< Reserved. */ |
129 | unsigned : 24; /**< Reserved. */ |
124 | __u8 dest; /**< Destination field. */ |
130 | __u8 dest; /**< Destination field. */ |
125 | } __attribute__ ((packed)); |
131 | } __attribute__ ((packed)); |
126 | }; |
132 | }; |
127 | } __attribute__ ((packed)); |
133 | } __attribute__ ((packed)); |
128 | typedef struct icr icr_t; |
134 | typedef struct icr icr_t; |
129 | 135 | ||
130 | /* End Of Interrupt. */ |
136 | /* End Of Interrupt. */ |
131 | #define EOI (0x0b0/sizeof(__u32)) |
137 | #define EOI (0x0b0/sizeof(__u32)) |
132 | 138 | ||
133 | /** Error Status Register. */ |
139 | /** Error Status Register. */ |
134 | #define ESR (0x280/sizeof(__u32)) |
140 | #define ESR (0x280/sizeof(__u32)) |
135 | union esr { |
141 | union esr { |
136 | __u32 value; |
142 | __u32 value; |
137 | __u8 err_bitmap; |
143 | __u8 err_bitmap; |
138 | struct { |
144 | struct { |
139 | unsigned send_checksum_error : 1; |
145 | unsigned send_checksum_error : 1; |
140 | unsigned receive_checksum_error : 1; |
146 | unsigned receive_checksum_error : 1; |
141 | unsigned send_accept_error : 1; |
147 | unsigned send_accept_error : 1; |
142 | unsigned receive_accept_error : 1; |
148 | unsigned receive_accept_error : 1; |
143 | unsigned : 1; |
149 | unsigned : 1; |
144 | unsigned send_illegal_vector : 1; |
150 | unsigned send_illegal_vector : 1; |
145 | unsigned received_illegal_vector : 1; |
151 | unsigned received_illegal_vector : 1; |
146 | unsigned illegal_register_address : 1; |
152 | unsigned illegal_register_address : 1; |
147 | unsigned : 24; |
153 | unsigned : 24; |
148 | } __attribute__ ((packed)); |
154 | } __attribute__ ((packed)); |
149 | }; |
155 | }; |
150 | typedef union esr esr_t; |
156 | typedef union esr esr_t; |
151 | 157 | ||
152 | /* Task Priority Register */ |
158 | /* Task Priority Register */ |
153 | #define TPR (0x080/sizeof(__u32)) |
159 | #define TPR (0x080/sizeof(__u32)) |
154 | union tpr { |
160 | union tpr { |
155 | __u32 value; |
161 | __u32 value; |
156 | struct { |
162 | struct { |
157 | unsigned pri_sc : 4; /**< Task Priority Sub-Class. */ |
163 | unsigned pri_sc : 4; /**< Task Priority Sub-Class. */ |
158 | unsigned pri : 4; /**< Task Priority. */ |
164 | unsigned pri : 4; /**< Task Priority. */ |
159 | } __attribute__ ((packed)); |
165 | } __attribute__ ((packed)); |
160 | }; |
166 | }; |
161 | typedef union tpr tpr_t; |
167 | typedef union tpr tpr_t; |
162 | 168 | ||
163 | /** Spurious-Interrupt Vector Register. */ |
169 | /** Spurious-Interrupt Vector Register. */ |
164 | #define SVR (0x0f0/sizeof(__u32)) |
170 | #define SVR (0x0f0/sizeof(__u32)) |
165 | union svr { |
171 | union svr { |
166 | __u32 value; |
172 | __u32 value; |
167 | struct { |
173 | struct { |
168 | __u8 vector; /**< Spurious Vector. */ |
174 | __u8 vector; /**< Spurious Vector. */ |
169 | unsigned lapic_enabled : 1; /**< APIC Software Enable/Disable. */ |
175 | unsigned lapic_enabled : 1; /**< APIC Software Enable/Disable. */ |
170 | unsigned focus_checking : 1; /**< Focus Processor Checking. */ |
176 | unsigned focus_checking : 1; /**< Focus Processor Checking. */ |
171 | unsigned : 22; /**< Reserved. */ |
177 | unsigned : 22; /**< Reserved. */ |
172 | } __attribute__ ((packed)); |
178 | } __attribute__ ((packed)); |
173 | }; |
179 | }; |
174 | typedef union svr svr_t; |
180 | typedef union svr svr_t; |
175 | 181 | ||
176 | /** Time Divide Configuration Register. */ |
182 | /** Time Divide Configuration Register. */ |
177 | #define TDCR (0x3e0/sizeof(__u32)) |
183 | #define TDCR (0x3e0/sizeof(__u32)) |
178 | union tdcr { |
184 | union tdcr { |
179 | __u32 value; |
185 | __u32 value; |
180 | struct { |
186 | struct { |
181 | unsigned div_value : 4; /**< Divide Value, bit 2 is always 0. */ |
187 | unsigned div_value : 4; /**< Divide Value, bit 2 is always 0. */ |
182 | unsigned : 28; /**< Reserved. */ |
188 | unsigned : 28; /**< Reserved. */ |
183 | } __attribute__ ((packed)); |
189 | } __attribute__ ((packed)); |
184 | }; |
190 | }; |
185 | typedef union tdcr tdcr_t; |
191 | typedef union tdcr tdcr_t; |
186 | 192 | ||
187 | /* Initial Count Register for Timer */ |
193 | /* Initial Count Register for Timer */ |
188 | #define ICRT (0x380/sizeof(__u32)) |
194 | #define ICRT (0x380/sizeof(__u32)) |
189 | 195 | ||
190 | /* Current Count Register for Timer */ |
196 | /* Current Count Register for Timer */ |
191 | #define CCRT (0x390/sizeof(__u32)) |
197 | #define CCRT (0x390/sizeof(__u32)) |
192 | 198 | ||
193 | /** LVT Timer register. */ |
199 | /** LVT Timer register. */ |
194 | #define LVT_Tm (0x320/sizeof(__u32)) |
200 | #define LVT_Tm (0x320/sizeof(__u32)) |
195 | union lvt_tm { |
201 | union lvt_tm { |
196 | __u32 value; |
202 | __u32 value; |
197 | struct { |
203 | struct { |
198 | __u8 vector; /**< Local Timer Interrupt vector. */ |
204 | __u8 vector; /**< Local Timer Interrupt vector. */ |
199 | unsigned : 4; /**< Reserved. */ |
205 | unsigned : 4; /**< Reserved. */ |
200 | unsigned delivs : 1; /**< Delivery status (RO). */ |
206 | unsigned delivs : 1; /**< Delivery status (RO). */ |
201 | unsigned : 3; /**< Reserved. */ |
207 | unsigned : 3; /**< Reserved. */ |
202 | unsigned masked : 1; /**< Interrupt Mask. */ |
208 | unsigned masked : 1; /**< Interrupt Mask. */ |
203 | unsigned mode : 1; /**< Timer Mode. */ |
209 | unsigned mode : 1; /**< Timer Mode. */ |
204 | unsigned : 14; /**< Reserved. */ |
210 | unsigned : 14; /**< Reserved. */ |
205 | } __attribute__ ((packed)); |
211 | } __attribute__ ((packed)); |
206 | }; |
212 | }; |
207 | typedef union lvt_tm lvt_tm_t; |
213 | typedef union lvt_tm lvt_tm_t; |
208 | 214 | ||
209 | /** LVT LINT registers. */ |
215 | /** LVT LINT registers. */ |
210 | #define LVT_LINT0 (0x350/sizeof(__u32)) |
216 | #define LVT_LINT0 (0x350/sizeof(__u32)) |
211 | #define LVT_LINT1 (0x360/sizeof(__u32)) |
217 | #define LVT_LINT1 (0x360/sizeof(__u32)) |
212 | union lvt_lint { |
218 | union lvt_lint { |
213 | __u32 value; |
219 | __u32 value; |
214 | struct { |
220 | struct { |
215 | __u8 vector; /**< LINT Interrupt vector. */ |
221 | __u8 vector; /**< LINT Interrupt vector. */ |
216 | unsigned delmod : 3; /**< Delivery Mode. */ |
222 | unsigned delmod : 3; /**< Delivery Mode. */ |
217 | unsigned : 1; /**< Reserved. */ |
223 | unsigned : 1; /**< Reserved. */ |
218 | unsigned delivs : 1; /**< Delivery status (RO). */ |
224 | unsigned delivs : 1; /**< Delivery status (RO). */ |
219 | unsigned intpol : 1; /**< Interrupt Input Pin Polarity. */ |
225 | unsigned intpol : 1; /**< Interrupt Input Pin Polarity. */ |
220 | unsigned irr : 1; /**< Remote IRR (RO). */ |
226 | unsigned irr : 1; /**< Remote IRR (RO). */ |
221 | unsigned trigger_mode : 1; /**< Trigger Mode. */ |
227 | unsigned trigger_mode : 1; /**< Trigger Mode. */ |
222 | unsigned masked : 1; /**< Interrupt Mask. */ |
228 | unsigned masked : 1; /**< Interrupt Mask. */ |
223 | unsigned : 15; /**< Reserved. */ |
229 | unsigned : 15; /**< Reserved. */ |
224 | } __attribute__ ((packed)); |
230 | } __attribute__ ((packed)); |
225 | }; |
231 | }; |
226 | typedef union lvt_lint lvt_lint_t; |
232 | typedef union lvt_lint lvt_lint_t; |
227 | 233 | ||
228 | /** LVT Error register. */ |
234 | /** LVT Error register. */ |
229 | #define LVT_Err (0x370/sizeof(__u32)) |
235 | #define LVT_Err (0x370/sizeof(__u32)) |
230 | union lvt_error { |
236 | union lvt_error { |
231 | __u32 value; |
237 | __u32 value; |
232 | struct { |
238 | struct { |
233 | __u8 vector; /**< Local Timer Interrupt vector. */ |
239 | __u8 vector; /**< Local Timer Interrupt vector. */ |
234 | unsigned : 4; /**< Reserved. */ |
240 | unsigned : 4; /**< Reserved. */ |
235 | unsigned delivs : 1; /**< Delivery status (RO). */ |
241 | unsigned delivs : 1; /**< Delivery status (RO). */ |
236 | unsigned : 3; /**< Reserved. */ |
242 | unsigned : 3; /**< Reserved. */ |
237 | unsigned masked : 1; /**< Interrupt Mask. */ |
243 | unsigned masked : 1; /**< Interrupt Mask. */ |
238 | unsigned : 15; /**< Reserved. */ |
244 | unsigned : 15; /**< Reserved. */ |
239 | } __attribute__ ((packed)); |
245 | } __attribute__ ((packed)); |
240 | }; |
246 | }; |
241 | typedef union lvt_error lvt_error_t; |
247 | typedef union lvt_error lvt_error_t; |
242 | 248 | ||
243 | /** Local APIC ID Register. */ |
249 | /** Local APIC ID Register. */ |
244 | #define L_APIC_ID (0x020/sizeof(__u32)) |
250 | #define L_APIC_ID (0x020/sizeof(__u32)) |
245 | union l_apic_id { |
251 | union l_apic_id { |
246 | __u32 value; |
252 | __u32 value; |
247 | struct { |
253 | struct { |
248 | unsigned : 24; /**< Reserved. */ |
254 | unsigned : 24; /**< Reserved. */ |
249 | __u8 apic_id; /**< Local APIC ID. */ |
255 | __u8 apic_id; /**< Local APIC ID. */ |
250 | } __attribute__ ((packed)); |
256 | } __attribute__ ((packed)); |
251 | }; |
257 | }; |
252 | typedef union l_apic_id l_apic_id_t; |
258 | typedef union l_apic_id l_apic_id_t; |
253 | 259 | ||
254 | /** Local APIC Version Register */ |
260 | /** Local APIC Version Register */ |
255 | #define LAVR (0x030/sizeof(__u32)) |
261 | #define LAVR (0x030/sizeof(__u32)) |
256 | #define LAVR_Mask 0xff |
262 | #define LAVR_Mask 0xff |
257 | #define is_local_apic(x) (((x)&LAVR_Mask&0xf0)==0x1) |
263 | #define is_local_apic(x) (((x)&LAVR_Mask&0xf0)==0x1) |
258 | #define is_82489DX_apic(x) ((((x)&LAVR_Mask&0xf0)==0x0)) |
264 | #define is_82489DX_apic(x) ((((x)&LAVR_Mask&0xf0)==0x0)) |
259 | #define is_local_xapic(x) (((x)&LAVR_Mask)==0x14) |
265 | #define is_local_xapic(x) (((x)&LAVR_Mask)==0x14) |
260 | 266 | ||
261 | /** Logical Destination Register. */ |
267 | /** Logical Destination Register. */ |
262 | #define LDR (0x0d0/sizeof(__u32)) |
268 | #define LDR (0x0d0/sizeof(__u32)) |
263 | union ldr { |
269 | union ldr { |
264 | __u32 value; |
270 | __u32 value; |
265 | struct { |
271 | struct { |
266 | unsigned : 24; /**< Reserved. */ |
272 | unsigned : 24; /**< Reserved. */ |
267 | __u8 id; /**< Logical APIC ID. */ |
273 | __u8 id; /**< Logical APIC ID. */ |
268 | } __attribute__ ((packed)); |
274 | } __attribute__ ((packed)); |
269 | }; |
275 | }; |
270 | typedef union ldr ldr_t; |
276 | typedef union ldr ldr_t; |
271 | 277 | ||
272 | /** Destination Format Register. */ |
278 | /** Destination Format Register. */ |
273 | #define DFR (0x0e0/sizeof(__u32)) |
279 | #define DFR (0x0e0/sizeof(__u32)) |
274 | union dfr { |
280 | union dfr { |
275 | __u32 value; |
281 | __u32 value; |
276 | struct { |
282 | struct { |
277 | unsigned : 28; /**< Reserved, all ones. */ |
283 | unsigned : 28; /**< Reserved, all ones. */ |
278 | unsigned model : 4; /**< Model. */ |
284 | unsigned model : 4; /**< Model. */ |
279 | } __attribute__ ((packed)); |
285 | } __attribute__ ((packed)); |
280 | }; |
286 | }; |
281 | typedef union dfr dfr_t; |
287 | typedef union dfr dfr_t; |
282 | 288 | ||
283 | /* IO APIC */ |
289 | /* IO APIC */ |
284 | #define IOREGSEL (0x00/sizeof(__u32)) |
290 | #define IOREGSEL (0x00/sizeof(__u32)) |
285 | #define IOWIN (0x10/sizeof(__u32)) |
291 | #define IOWIN (0x10/sizeof(__u32)) |
286 | 292 | ||
287 | #define IOAPICID 0x00 |
293 | #define IOAPICID 0x00 |
288 | #define IOAPICVER 0x01 |
294 | #define IOAPICVER 0x01 |
289 | #define IOAPICARB 0x02 |
295 | #define IOAPICARB 0x02 |
290 | #define IOREDTBL 0x10 |
296 | #define IOREDTBL 0x10 |
291 | 297 | ||
292 | /** I/O Register Select Register. */ |
298 | /** I/O Register Select Register. */ |
293 | union io_regsel { |
299 | union io_regsel { |
294 | __u32 value; |
300 | __u32 value; |
295 | struct { |
301 | struct { |
296 | __u8 reg_addr; /**< APIC Register Address. */ |
302 | __u8 reg_addr; /**< APIC Register Address. */ |
297 | unsigned : 24; /**< Reserved. */ |
303 | unsigned : 24; /**< Reserved. */ |
298 | } __attribute__ ((packed)); |
304 | } __attribute__ ((packed)); |
299 | }; |
305 | }; |
300 | typedef union io_regsel io_regsel_t; |
306 | typedef union io_regsel io_regsel_t; |
301 | 307 | ||
302 | /** I/O Redirection Register. */ |
308 | /** I/O Redirection Register. */ |
303 | struct io_redirection_reg { |
309 | struct io_redirection_reg { |
304 | union { |
310 | union { |
305 | __u32 lo; |
311 | __u32 lo; |
306 | struct { |
312 | struct { |
307 | __u8 intvec; /**< Interrupt Vector. */ |
313 | __u8 intvec; /**< Interrupt Vector. */ |
308 | unsigned delmod : 3; /**< Delivery Mode. */ |
314 | unsigned delmod : 3; /**< Delivery Mode. */ |
309 | unsigned destmod : 1; /**< Destination mode. */ |
315 | unsigned destmod : 1; /**< Destination mode. */ |
310 | unsigned delivs : 1; /**< Delivery status (RO). */ |
316 | unsigned delivs : 1; /**< Delivery status (RO). */ |
311 | unsigned intpol : 1; /**< Interrupt Input Pin Polarity. */ |
317 | unsigned intpol : 1; /**< Interrupt Input Pin Polarity. */ |
312 | unsigned irr : 1; /**< Remote IRR (RO). */ |
318 | unsigned irr : 1; /**< Remote IRR (RO). */ |
313 | unsigned trigger_mode : 1; /**< Trigger Mode. */ |
319 | unsigned trigger_mode : 1; /**< Trigger Mode. */ |
314 | unsigned masked : 1; /**< Interrupt Mask. */ |
320 | unsigned masked : 1; /**< Interrupt Mask. */ |
315 | unsigned : 15; /**< Reserved. */ |
321 | unsigned : 15; /**< Reserved. */ |
316 | } __attribute__ ((packed)); |
322 | } __attribute__ ((packed)); |
317 | }; |
323 | }; |
318 | union { |
324 | union { |
319 | __u32 hi; |
325 | __u32 hi; |
320 | struct { |
326 | struct { |
321 | unsigned : 24; /**< Reserved. */ |
327 | unsigned : 24; /**< Reserved. */ |
322 | __u8 dest : 8; /**< Destination Field. */ |
328 | __u8 dest : 8; /**< Destination Field. */ |
323 | } __attribute__ ((packed)); |
329 | } __attribute__ ((packed)); |
324 | }; |
330 | }; |
325 | 331 | ||
326 | } __attribute__ ((packed)); |
332 | } __attribute__ ((packed)); |
327 | typedef struct io_redirection_reg io_redirection_reg_t; |
333 | typedef struct io_redirection_reg io_redirection_reg_t; |
328 | 334 | ||
329 | 335 | ||
330 | /** IO APIC Identification Register. */ |
336 | /** IO APIC Identification Register. */ |
331 | union io_apic_id { |
337 | union io_apic_id { |
332 | __u32 value; |
338 | __u32 value; |
333 | struct { |
339 | struct { |
334 | unsigned : 24; /**< Reserved. */ |
340 | unsigned : 24; /**< Reserved. */ |
335 | unsigned apic_id : 4; /**< IO APIC ID. */ |
341 | unsigned apic_id : 4; /**< IO APIC ID. */ |
336 | unsigned : 4; /**< Reserved. */ |
342 | unsigned : 4; /**< Reserved. */ |
337 | } __attribute__ ((packed)); |
343 | } __attribute__ ((packed)); |
338 | }; |
344 | }; |
339 | typedef union io_apic_id io_apic_id_t; |
345 | typedef union io_apic_id io_apic_id_t; |
340 | 346 | ||
341 | extern volatile __u32 *l_apic; |
347 | extern volatile __u32 *l_apic; |
342 | extern volatile __u32 *io_apic; |
348 | extern volatile __u32 *io_apic; |
343 | 349 | ||
344 | extern __u32 apic_id_mask; |
350 | extern __u32 apic_id_mask; |
345 | 351 | ||
346 | extern void apic_init(void); |
352 | extern void apic_init(void); |
347 | 353 | ||
348 | extern void l_apic_init(void); |
354 | extern void l_apic_init(void); |
349 | extern void l_apic_eoi(void); |
355 | extern void l_apic_eoi(void); |
350 | extern int l_apic_broadcast_custom_ipi(__u8 vector); |
356 | extern int l_apic_broadcast_custom_ipi(__u8 vector); |
351 | extern int l_apic_send_init_ipi(__u8 apicid); |
357 | extern int l_apic_send_init_ipi(__u8 apicid); |
352 | extern void l_apic_debug(void); |
358 | extern void l_apic_debug(void); |
353 | extern __u8 l_apic_id(void); |
359 | extern __u8 l_apic_id(void); |
354 | 360 | ||
355 | extern __u32 io_apic_read(__u8 address); |
361 | extern __u32 io_apic_read(__u8 address); |
356 | extern void io_apic_write(__u8 address , __u32 x); |
362 | extern void io_apic_write(__u8 address , __u32 x); |
357 | extern void io_apic_change_ioredtbl(int pin, int dest, __u8 v, int flags); |
363 | extern void io_apic_change_ioredtbl(int pin, int dest, __u8 v, int flags); |
358 | extern void io_apic_disable_irqs(__u16 irqmask); |
364 | extern void io_apic_disable_irqs(__u16 irqmask); |
359 | extern void io_apic_enable_irqs(__u16 irqmask); |
365 | extern void io_apic_enable_irqs(__u16 irqmask); |
360 | 366 | ||
361 | #endif |
367 | #endif |
- | 368 | ||
- | 369 | /** @} |
|
- | 370 | */ |
|
- | 371 | ||
362 | 372 |