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1 | /* |
1 | /* |
2 | * Copyright (C) 2001-2004 Jakub Jermar |
2 | * Copyright (C) 2001-2004 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | #ifndef __ia32_ASM_H__ |
29 | #ifndef __ia32_ASM_H__ |
30 | #define __ia32_ASM_H__ |
30 | #define __ia32_ASM_H__ |
31 | 31 | ||
32 | #include <arch/types.h> |
32 | #include <arch/types.h> |
33 | #include <typedefs.h> |
33 | #include <typedefs.h> |
34 | #include <mm/page.h> |
34 | #include <mm/page.h> |
35 | #include <synch/spinlock.h> |
35 | #include <synch/spinlock.h> |
- | 36 | #include <arch/boot/memmap.h> |
|
36 | 37 | ||
37 | extern __u32 interrupt_handler_size; |
38 | extern __u32 interrupt_handler_size; |
38 | 39 | ||
39 | extern void paging_on(void); |
40 | extern void paging_on(void); |
40 | 41 | ||
41 | extern void interrupt_handlers(void); |
42 | extern void interrupt_handlers(void); |
42 | 43 | ||
43 | extern __u8 inb(int port); |
44 | extern __u8 inb(int port); |
44 | extern __u16 inw(int port); |
45 | extern __u16 inw(int port); |
45 | extern __u32 inl(int port); |
46 | extern __u32 inl(int port); |
46 | 47 | ||
47 | extern void outb(int port, __u8 b); |
48 | extern void outb(int port, __u8 b); |
48 | extern void outw(int port, __u16 w); |
49 | extern void outw(int port, __u16 w); |
49 | extern void outl(int port, __u32 l); |
50 | extern void outl(int port, __u32 l); |
50 | 51 | ||
51 | extern void enable_l_apic_in_msr(void); |
52 | extern void enable_l_apic_in_msr(void); |
52 | 53 | ||
53 | /** Halt CPU |
54 | /** Halt CPU |
54 | * |
55 | * |
55 | * Halt the current CPU until interrupt event. |
56 | * Halt the current CPU until interrupt event. |
56 | */ |
57 | */ |
57 | static inline void cpu_halt(void) { __asm__("hlt"); }; |
58 | static inline void cpu_halt(void) { __asm__("hlt"); }; |
58 | static inline void cpu_sleep(void) { __asm__("hlt"); }; |
59 | static inline void cpu_sleep(void) { __asm__("hlt"); }; |
59 | 60 | ||
60 | /** Read CR2 |
61 | /** Read CR2 |
61 | * |
62 | * |
62 | * Return value in CR2 |
63 | * Return value in CR2 |
63 | * |
64 | * |
64 | * @return Value read. |
65 | * @return Value read. |
65 | */ |
66 | */ |
66 | static inline __u32 read_cr2(void) { __u32 v; __asm__ volatile ("movl %%cr2,%0" : "=r" (v)); return v; } |
67 | static inline __u32 read_cr2(void) { __u32 v; __asm__ volatile ("movl %%cr2,%0" : "=r" (v)); return v; } |
67 | 68 | ||
68 | /** Write CR3 |
69 | /** Write CR3 |
69 | * |
70 | * |
70 | * Write value to CR3. |
71 | * Write value to CR3. |
71 | * |
72 | * |
72 | * @param v Value to be written. |
73 | * @param v Value to be written. |
73 | */ |
74 | */ |
74 | static inline void write_cr3(__u32 v) { __asm__ volatile ("movl %0,%%cr3\n" : : "r" (v)); } |
75 | static inline void write_cr3(__u32 v) { __asm__ volatile ("movl %0,%%cr3\n" : : "r" (v)); } |
75 | 76 | ||
76 | /** Read CR3 |
77 | /** Read CR3 |
77 | * |
78 | * |
78 | * Return value in CR3 |
79 | * Return value in CR3 |
79 | * |
80 | * |
80 | * @return Value read. |
81 | * @return Value read. |
81 | */ |
82 | */ |
82 | static inline __u32 read_cr3(void) { __u32 v; __asm__ volatile ("movl %%cr3,%0" : "=r" (v)); return v; } |
83 | static inline __u32 read_cr3(void) { __u32 v; __asm__ volatile ("movl %%cr3,%0" : "=r" (v)); return v; } |
83 | 84 | ||
84 | /** Write DR0 |
85 | /** Write DR0 |
85 | * |
86 | * |
86 | * Write value to DR0. |
87 | * Write value to DR0. |
87 | * |
88 | * |
88 | * @param v Value to be written. |
89 | * @param v Value to be written. |
89 | */ |
90 | */ |
90 | static inline void write_dr0(__u32 v) { __asm__ volatile ("movl %0,%%dr0\n" : : "r" (v)); } |
91 | static inline void write_dr0(__u32 v) { __asm__ volatile ("movl %0,%%dr0\n" : : "r" (v)); } |
91 | 92 | ||
92 | /** Read DR0 |
93 | /** Read DR0 |
93 | * |
94 | * |
94 | * Return value in DR0 |
95 | * Return value in DR0 |
95 | * |
96 | * |
96 | * @return Value read. |
97 | * @return Value read. |
97 | */ |
98 | */ |
98 | static inline __u32 read_dr0(void) { __u32 v; __asm__ volatile ("movl %%dr0,%0" : "=r" (v)); return v; } |
99 | static inline __u32 read_dr0(void) { __u32 v; __asm__ volatile ("movl %%dr0,%0" : "=r" (v)); return v; } |
99 | 100 | ||
100 | /** Set priority level low |
101 | /** Set priority level low |
101 | * |
102 | * |
102 | * Enable interrupts and return previous |
103 | * Enable interrupts and return previous |
103 | * value of EFLAGS. |
104 | * value of EFLAGS. |
104 | */ |
105 | */ |
105 | static inline pri_t cpu_priority_low(void) { |
106 | static inline pri_t cpu_priority_low(void) { |
106 | pri_t v; |
107 | pri_t v; |
107 | __asm__ volatile ( |
108 | __asm__ volatile ( |
108 | "pushf\n" |
109 | "pushf\n" |
109 | "popl %0\n" |
110 | "popl %0\n" |
110 | "sti\n" |
111 | "sti\n" |
111 | : "=r" (v) |
112 | : "=r" (v) |
112 | ); |
113 | ); |
113 | return v; |
114 | return v; |
114 | } |
115 | } |
115 | 116 | ||
116 | /** Set priority level high |
117 | /** Set priority level high |
117 | * |
118 | * |
118 | * Disable interrupts and return previous |
119 | * Disable interrupts and return previous |
119 | * value of EFLAGS. |
120 | * value of EFLAGS. |
120 | */ |
121 | */ |
121 | static inline pri_t cpu_priority_high(void) { |
122 | static inline pri_t cpu_priority_high(void) { |
122 | pri_t v; |
123 | pri_t v; |
123 | __asm__ volatile ( |
124 | __asm__ volatile ( |
124 | "pushf\n" |
125 | "pushf\n" |
125 | "popl %0\n" |
126 | "popl %0\n" |
126 | "cli\n" |
127 | "cli\n" |
127 | : "=r" (v) |
128 | : "=r" (v) |
128 | ); |
129 | ); |
129 | return v; |
130 | return v; |
130 | } |
131 | } |
131 | 132 | ||
132 | /** Restore priority level |
133 | /** Restore priority level |
133 | * |
134 | * |
134 | * Restore EFLAGS. |
135 | * Restore EFLAGS. |
135 | */ |
136 | */ |
136 | static inline void cpu_priority_restore(pri_t pri) { |
137 | static inline void cpu_priority_restore(pri_t pri) { |
137 | __asm__ volatile ( |
138 | __asm__ volatile ( |
138 | "pushl %0\n" |
139 | "pushl %0\n" |
139 | "popf\n" |
140 | "popf\n" |
140 | : : "r" (pri) |
141 | : : "r" (pri) |
141 | ); |
142 | ); |
142 | } |
143 | } |
143 | 144 | ||
144 | /** Return raw priority level |
145 | /** Return raw priority level |
145 | * |
146 | * |
146 | * Return EFLAFS. |
147 | * Return EFLAFS. |
147 | */ |
148 | */ |
148 | static inline pri_t cpu_priority_read(void) { |
149 | static inline pri_t cpu_priority_read(void) { |
149 | pri_t v; |
150 | pri_t v; |
150 | __asm__ volatile ( |
151 | __asm__ volatile ( |
151 | "pushf\n" |
152 | "pushf\n" |
152 | "popl %0\n" |
153 | "popl %0\n" |
153 | : "=r" (v) |
154 | : "=r" (v) |
154 | ); |
155 | ); |
155 | return v; |
156 | return v; |
156 | } |
157 | } |
157 | 158 | ||
158 | #endif |
159 | #endif |
159 | 160 |