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1 | /* |
1 | /* |
2 | * Copyright (c) 2007 Petr Stepan |
2 | * Copyright (c) 2007 Petr Stepan |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup arm32 |
29 | /** @addtogroup arm32 |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | */ |
33 | */ |
34 | 34 | ||
35 | #include<arch/asm.h> |
35 | #include<arch/asm.h> |
36 | #include<arch/regutils.h> |
36 | #include<arch/regutils.h> |
37 | 37 | ||
38 | 38 | ||
39 | /** Disable interrupts. |
39 | /** Disable interrupts. |
40 | * |
40 | * |
41 | * @return Old interrupt priority level. |
41 | * @return Old interrupt priority level. |
42 | */ |
42 | */ |
43 | ipl_t interrupts_disable(void) |
43 | ipl_t interrupts_disable(void) |
44 | { |
44 | { |
45 | ipl_t ipl = status_reg_read(); |
45 | ipl_t ipl = current_status_reg_read(); |
46 | 46 | ||
47 | status_reg_control_write(ipl & ~status_reg_ie_enabled_bit); |
47 | current_status_reg_control_write(ipl & ~STATUS_REG_IE_ENABLED_BIT); |
48 | 48 | ||
49 | return ipl; |
49 | return ipl; |
50 | } |
50 | } |
51 | 51 | ||
52 | /** Enable interrupts. |
52 | /** Enable interrupts. |
53 | * |
53 | * |
54 | * @return Old interrupt priority level. |
54 | * @return Old interrupt priority level. |
55 | */ |
55 | */ |
56 | ipl_t interrupts_enable(void) |
56 | ipl_t interrupts_enable(void) |
57 | { |
57 | { |
58 | ipl_t ipl = status_reg_read(); |
58 | ipl_t ipl = current_status_reg_read(); |
59 | 59 | ||
60 | status_reg_control_write(ipl | status_reg_ie_enabled_bit); |
60 | current_status_reg_control_write(ipl | STATUS_REG_IE_ENABLED_BIT); |
61 | 61 | ||
62 | return ipl; |
62 | return ipl; |
63 | } |
63 | } |
64 | 64 | ||
65 | /** Restore interrupt priority level. |
65 | /** Restore interrupt priority level. |
66 | * |
66 | * |
67 | * @param ipl Saved interrupt priority level. |
67 | * @param ipl Saved interrupt priority level. |
68 | */ |
68 | */ |
69 | void interrupts_restore(ipl_t ipl) |
69 | void interrupts_restore(ipl_t ipl) |
70 | { |
70 | { |
71 | status_reg_control_write(status_reg_read() | (ipl & status_reg_ie_enabled_bit)); |
71 | current_status_reg_control_write(current_status_reg_read() | |
- | 72 | (ipl & STATUS_REG_IE_ENABLED_BIT)); |
|
72 | } |
73 | } |
73 | 74 | ||
74 | /** Read interrupt priority level. |
75 | /** Read interrupt priority level. |
75 | * |
76 | * |
76 | * @return Current interrupt priority level. |
77 | * @return Current interrupt priority level. |
77 | */ |
78 | */ |
78 | ipl_t interrupts_read(void) |
79 | ipl_t interrupts_read(void) |
79 | { |
80 | { |
80 | return status_reg_read(); |
81 | return current_status_reg_read(); |
81 | } |
82 | } |
82 | 83 | ||
83 | /** @} |
84 | /** @} |
84 | */ |
85 | */ |
85 | 86 |