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1 | /* |
1 | /* |
2 | * Copyright (c) 2007 Petr Stepan |
2 | * Copyright (c) 2007 Petr Stepan |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup arm32 |
29 | /** @addtogroup arm32 |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | * @brief Interrupts controlling routines. |
33 | * @brief Interrupts controlling routines. |
34 | */ |
34 | */ |
35 | 35 | ||
36 | #include <arch/asm.h> |
36 | #include <arch/asm.h> |
37 | #include <arch/regutils.h> |
37 | #include <arch/regutils.h> |
38 | #include <ddi/irq.h> |
38 | #include <ddi/irq.h> |
39 | #include <arch/machine.h> |
39 | #include <arch/machine.h> |
40 | #include <interrupt.h> |
40 | #include <interrupt.h> |
41 | 41 | ||
42 | /** Initial size of a table holding interrupt handlers. */ |
42 | /** Initial size of a table holding interrupt handlers. */ |
43 | #define IRQ_COUNT 8 |
43 | #define IRQ_COUNT 8 |
44 | 44 | ||
45 | - | ||
46 | /** Disable interrupts. |
45 | /** Disable interrupts. |
47 | * |
46 | * |
48 | * @return Old interrupt priority level. |
47 | * @return Old interrupt priority level. |
49 | */ |
48 | */ |
50 | ipl_t interrupts_disable(void) |
49 | ipl_t interrupts_disable(void) |
51 | { |
50 | { |
52 | ipl_t ipl = current_status_reg_read(); |
51 | ipl_t ipl = current_status_reg_read(); |
53 | 52 | ||
54 | current_status_reg_control_write(STATUS_REG_IRQ_DISABLED_BIT | ipl); |
53 | current_status_reg_control_write(STATUS_REG_IRQ_DISABLED_BIT | ipl); |
55 | 54 | ||
56 | return ipl; |
55 | return ipl; |
57 | } |
56 | } |
58 | 57 | ||
59 | - | ||
60 | /** Enable interrupts. |
58 | /** Enable interrupts. |
61 | * |
59 | * |
62 | * @return Old interrupt priority level. |
60 | * @return Old interrupt priority level. |
63 | */ |
61 | */ |
64 | ipl_t interrupts_enable(void) |
62 | ipl_t interrupts_enable(void) |
65 | { |
63 | { |
66 | ipl_t ipl = current_status_reg_read(); |
64 | ipl_t ipl = current_status_reg_read(); |
67 | 65 | ||
68 | current_status_reg_control_write(ipl & ~STATUS_REG_IRQ_DISABLED_BIT); |
66 | current_status_reg_control_write(ipl & ~STATUS_REG_IRQ_DISABLED_BIT); |
69 | 67 | ||
70 | return ipl; |
68 | return ipl; |
71 | } |
69 | } |
72 | 70 | ||
73 | - | ||
74 | /** Restore interrupt priority level. |
71 | /** Restore interrupt priority level. |
75 | * |
72 | * |
76 | * @param ipl Saved interrupt priority level. |
73 | * @param ipl Saved interrupt priority level. |
77 | */ |
74 | */ |
78 | void interrupts_restore(ipl_t ipl) |
75 | void interrupts_restore(ipl_t ipl) |
79 | { |
76 | { |
80 | current_status_reg_control_write( |
77 | current_status_reg_control_write( |
81 | (current_status_reg_read() & ~STATUS_REG_IRQ_DISABLED_BIT) | |
78 | (current_status_reg_read() & ~STATUS_REG_IRQ_DISABLED_BIT) | |
82 | (ipl & STATUS_REG_IRQ_DISABLED_BIT) |
79 | (ipl & STATUS_REG_IRQ_DISABLED_BIT)); |
83 | ); |
- | |
84 | } |
80 | } |
85 | 81 | ||
86 | - | ||
87 | /** Read interrupt priority level. |
82 | /** Read interrupt priority level. |
88 | * |
83 | * |
89 | * @return Current interrupt priority level. |
84 | * @return Current interrupt priority level. |
90 | */ |
85 | */ |
91 | ipl_t interrupts_read(void) |
86 | ipl_t interrupts_read(void) |
92 | { |
87 | { |
93 | return current_status_reg_read(); |
88 | return current_status_reg_read(); |
94 | } |
89 | } |
95 | 90 | ||
96 | - | ||
97 | /** Initialize basic tables for exception dispatching |
91 | /** Initialize basic tables for exception dispatching |
98 | * and starts the timer. |
92 | * and starts the timer. |
99 | */ |
93 | */ |
100 | void interrupt_init(void) |
94 | void interrupt_init(void) |
101 | { |
95 | { |
102 | irq_init(IRQ_COUNT, IRQ_COUNT); |
96 | irq_init(IRQ_COUNT, IRQ_COUNT); |
103 | machine_timer_irq_start(); |
97 | machine_timer_irq_start(); |
104 | } |
98 | } |
105 | 99 | ||
106 | - | ||
107 | /** @} |
100 | /** @} |
108 | */ |
101 | */ |
109 | 102 |