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1 | /* |
1 | /* |
2 | * Copyright (C) 2005 Ondrej Palkovsky |
2 | * Copyright (C) 2005 Ondrej Palkovsky |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup amd64 amd64 |
29 | /** @addtogroup amd64 |
30 | * @ingroup others |
- | |
31 | * @{ |
30 | * @{ |
32 | */ |
31 | */ |
33 | /** @file |
32 | /** @file |
34 | */ |
33 | */ |
35 | 34 | ||
36 | #include <arch.h> |
35 | #include <arch.h> |
37 | 36 | ||
38 | #include <arch/types.h> |
37 | #include <arch/types.h> |
39 | 38 | ||
40 | #include <config.h> |
39 | #include <config.h> |
41 | 40 | ||
42 | #include <proc/thread.h> |
41 | #include <proc/thread.h> |
43 | #include <arch/drivers/ega.h> |
42 | #include <arch/drivers/ega.h> |
44 | #include <arch/drivers/vesa.h> |
43 | #include <arch/drivers/vesa.h> |
45 | #include <genarch/i8042/i8042.h> |
44 | #include <genarch/i8042/i8042.h> |
46 | #include <arch/drivers/i8254.h> |
45 | #include <arch/drivers/i8254.h> |
47 | #include <arch/drivers/i8259.h> |
46 | #include <arch/drivers/i8259.h> |
48 | 47 | ||
49 | #include <arch/bios/bios.h> |
48 | #include <arch/bios/bios.h> |
50 | #include <arch/mm/memory_init.h> |
49 | #include <arch/mm/memory_init.h> |
51 | #include <arch/cpu.h> |
50 | #include <arch/cpu.h> |
52 | #include <print.h> |
51 | #include <print.h> |
53 | #include <arch/cpuid.h> |
52 | #include <arch/cpuid.h> |
54 | #include <genarch/acpi/acpi.h> |
53 | #include <genarch/acpi/acpi.h> |
55 | #include <panic.h> |
54 | #include <panic.h> |
56 | #include <interrupt.h> |
55 | #include <interrupt.h> |
57 | #include <arch/syscall.h> |
56 | #include <arch/syscall.h> |
58 | #include <arch/debugger.h> |
57 | #include <arch/debugger.h> |
59 | #include <syscall/syscall.h> |
58 | #include <syscall/syscall.h> |
60 | #include <console/console.h> |
59 | #include <console/console.h> |
61 | 60 | ||
62 | 61 | ||
63 | /** Disable I/O on non-privileged levels |
62 | /** Disable I/O on non-privileged levels |
64 | * |
63 | * |
65 | * Clean IOPL(12,13) and NT(14) flags in EFLAGS register |
64 | * Clean IOPL(12,13) and NT(14) flags in EFLAGS register |
66 | */ |
65 | */ |
67 | static void clean_IOPL_NT_flags(void) |
66 | static void clean_IOPL_NT_flags(void) |
68 | { |
67 | { |
69 | asm |
68 | asm |
70 | ( |
69 | ( |
71 | "pushfq;" |
70 | "pushfq;" |
72 | "pop %%rax;" |
71 | "pop %%rax;" |
73 | "and $~(0x7000),%%rax;" |
72 | "and $~(0x7000),%%rax;" |
74 | "pushq %%rax;" |
73 | "pushq %%rax;" |
75 | "popfq;" |
74 | "popfq;" |
76 | : |
75 | : |
77 | : |
76 | : |
78 | :"%rax" |
77 | :"%rax" |
79 | ); |
78 | ); |
80 | } |
79 | } |
81 | 80 | ||
82 | /** Disable alignment check |
81 | /** Disable alignment check |
83 | * |
82 | * |
84 | * Clean AM(18) flag in CR0 register |
83 | * Clean AM(18) flag in CR0 register |
85 | */ |
84 | */ |
86 | static void clean_AM_flag(void) |
85 | static void clean_AM_flag(void) |
87 | { |
86 | { |
88 | asm |
87 | asm |
89 | ( |
88 | ( |
90 | "mov %%cr0,%%rax;" |
89 | "mov %%cr0,%%rax;" |
91 | "and $~(0x40000),%%rax;" |
90 | "and $~(0x40000),%%rax;" |
92 | "mov %%rax,%%cr0;" |
91 | "mov %%rax,%%cr0;" |
93 | : |
92 | : |
94 | : |
93 | : |
95 | :"%rax" |
94 | :"%rax" |
96 | ); |
95 | ); |
97 | } |
96 | } |
98 | 97 | ||
99 | void arch_pre_mm_init(void) |
98 | void arch_pre_mm_init(void) |
100 | { |
99 | { |
101 | struct cpu_info cpuid_s; |
100 | struct cpu_info cpuid_s; |
102 | 101 | ||
103 | cpuid(AMD_CPUID_EXTENDED,&cpuid_s); |
102 | cpuid(AMD_CPUID_EXTENDED,&cpuid_s); |
104 | if (! (cpuid_s.cpuid_edx & (1<<AMD_EXT_NOEXECUTE))) |
103 | if (! (cpuid_s.cpuid_edx & (1<<AMD_EXT_NOEXECUTE))) |
105 | panic("Processor does not support No-execute pages.\n"); |
104 | panic("Processor does not support No-execute pages.\n"); |
106 | 105 | ||
107 | cpuid(INTEL_CPUID_STANDARD,&cpuid_s); |
106 | cpuid(INTEL_CPUID_STANDARD,&cpuid_s); |
108 | if (! (cpuid_s.cpuid_edx & (1<<INTEL_FXSAVE))) |
107 | if (! (cpuid_s.cpuid_edx & (1<<INTEL_FXSAVE))) |
109 | panic("Processor does not support FXSAVE/FXRESTORE.\n"); |
108 | panic("Processor does not support FXSAVE/FXRESTORE.\n"); |
110 | 109 | ||
111 | if (! (cpuid_s.cpuid_edx & (1<<INTEL_SSE2))) |
110 | if (! (cpuid_s.cpuid_edx & (1<<INTEL_SSE2))) |
112 | panic("Processor does not support SSE2 instructions.\n"); |
111 | panic("Processor does not support SSE2 instructions.\n"); |
113 | 112 | ||
114 | /* Enable No-execute pages */ |
113 | /* Enable No-execute pages */ |
115 | set_efer_flag(AMD_NXE_FLAG); |
114 | set_efer_flag(AMD_NXE_FLAG); |
116 | /* Enable FPU */ |
115 | /* Enable FPU */ |
117 | cpu_setup_fpu(); |
116 | cpu_setup_fpu(); |
118 | 117 | ||
119 | /* Initialize segmentation */ |
118 | /* Initialize segmentation */ |
120 | pm_init(); |
119 | pm_init(); |
121 | 120 | ||
122 | /* Disable I/O on nonprivileged levels |
121 | /* Disable I/O on nonprivileged levels |
123 | * clear the NT(nested-thread) flag |
122 | * clear the NT(nested-thread) flag |
124 | */ |
123 | */ |
125 | clean_IOPL_NT_flags(); |
124 | clean_IOPL_NT_flags(); |
126 | /* Disable alignment check */ |
125 | /* Disable alignment check */ |
127 | clean_AM_flag(); |
126 | clean_AM_flag(); |
128 | 127 | ||
129 | if (config.cpu_active == 1) { |
128 | if (config.cpu_active == 1) { |
130 | bios_init(); |
129 | bios_init(); |
131 | i8259_init(); /* PIC */ |
130 | i8259_init(); /* PIC */ |
132 | i8254_init(); /* hard clock */ |
131 | i8254_init(); /* hard clock */ |
133 | 132 | ||
134 | #ifdef CONFIG_SMP |
133 | #ifdef CONFIG_SMP |
135 | exc_register(VECTOR_TLB_SHOOTDOWN_IPI, "tlb_shootdown", |
134 | exc_register(VECTOR_TLB_SHOOTDOWN_IPI, "tlb_shootdown", |
136 | tlb_shootdown_ipi); |
135 | tlb_shootdown_ipi); |
137 | #endif /* CONFIG_SMP */ |
136 | #endif /* CONFIG_SMP */ |
138 | } |
137 | } |
139 | } |
138 | } |
140 | 139 | ||
141 | void arch_post_mm_init(void) |
140 | void arch_post_mm_init(void) |
142 | { |
141 | { |
143 | if (config.cpu_active == 1) { |
142 | if (config.cpu_active == 1) { |
144 | #ifdef CONFIG_FB |
143 | #ifdef CONFIG_FB |
145 | if (vesa_present()) |
144 | if (vesa_present()) |
146 | vesa_init(); |
145 | vesa_init(); |
147 | else |
146 | else |
148 | #endif |
147 | #endif |
149 | ega_init(); /* video */ |
148 | ega_init(); /* video */ |
150 | /* Enable debugger */ |
149 | /* Enable debugger */ |
151 | debugger_init(); |
150 | debugger_init(); |
152 | /* Merge all memory zones to 1 big zone */ |
151 | /* Merge all memory zones to 1 big zone */ |
153 | zone_merge_all(); |
152 | zone_merge_all(); |
154 | } |
153 | } |
155 | /* Setup fast SYSCALL/SYSRET */ |
154 | /* Setup fast SYSCALL/SYSRET */ |
156 | syscall_setup_cpu(); |
155 | syscall_setup_cpu(); |
157 | 156 | ||
158 | } |
157 | } |
159 | 158 | ||
160 | void arch_pre_smp_init(void) |
159 | void arch_pre_smp_init(void) |
161 | { |
160 | { |
162 | if (config.cpu_active == 1) { |
161 | if (config.cpu_active == 1) { |
163 | memory_print_map(); |
162 | memory_print_map(); |
164 | 163 | ||
165 | #ifdef CONFIG_SMP |
164 | #ifdef CONFIG_SMP |
166 | acpi_init(); |
165 | acpi_init(); |
167 | #endif /* CONFIG_SMP */ |
166 | #endif /* CONFIG_SMP */ |
168 | } |
167 | } |
169 | } |
168 | } |
170 | 169 | ||
171 | void arch_post_smp_init(void) |
170 | void arch_post_smp_init(void) |
172 | { |
171 | { |
173 | i8042_init(); /* keyboard controller */ |
172 | i8042_init(); /* keyboard controller */ |
174 | } |
173 | } |
175 | 174 | ||
176 | void calibrate_delay_loop(void) |
175 | void calibrate_delay_loop(void) |
177 | { |
176 | { |
178 | i8254_calibrate_delay_loop(); |
177 | i8254_calibrate_delay_loop(); |
179 | i8254_normal_operation(); |
178 | i8254_normal_operation(); |
180 | } |
179 | } |
181 | 180 | ||
182 | /** Set thread-local-storage pointer |
181 | /** Set thread-local-storage pointer |
183 | * |
182 | * |
184 | * TLS pointer is set in FS register. Unfortunately the 64-bit |
183 | * TLS pointer is set in FS register. Unfortunately the 64-bit |
185 | * part can be set only in CPL0 mode. |
184 | * part can be set only in CPL0 mode. |
186 | * |
185 | * |
187 | * The specs say, that on %fs:0 there is stored contents of %fs register, |
186 | * The specs say, that on %fs:0 there is stored contents of %fs register, |
188 | * we need not to go to CPL0 to read it. |
187 | * we need not to go to CPL0 to read it. |
189 | */ |
188 | */ |
190 | __native sys_tls_set(__native addr) |
189 | __native sys_tls_set(__native addr) |
191 | { |
190 | { |
192 | THREAD->arch.tls = addr; |
191 | THREAD->arch.tls = addr; |
193 | write_msr(AMD_MSR_FS, addr); |
192 | write_msr(AMD_MSR_FS, addr); |
194 | return 0; |
193 | return 0; |
195 | } |
194 | } |
196 | 195 | ||
197 | /** Acquire console back for kernel |
196 | /** Acquire console back for kernel |
198 | * |
197 | * |
199 | */ |
198 | */ |
200 | void arch_grab_console(void) |
199 | void arch_grab_console(void) |
201 | { |
200 | { |
202 | i8042_grab(); |
201 | i8042_grab(); |
203 | } |
202 | } |
204 | /** Return console to userspace |
203 | /** Return console to userspace |
205 | * |
204 | * |
206 | */ |
205 | */ |
207 | void arch_release_console(void) |
206 | void arch_release_console(void) |
208 | { |
207 | { |
209 | i8042_release(); |
208 | i8042_release(); |
210 | } |
209 | } |
211 | 210 | ||
212 | /** @} |
211 | /** @} |
213 | */ |
212 | */ |
214 | 213 | ||
215 | 214 |