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1 | /* |
1 | /* |
2 | * Copyright (C) 2001-2004 Jakub Jermar |
2 | * Copyright (C) 2001-2004 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup amd64interrupt |
29 | /** @addtogroup amd64interrupt |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | */ |
33 | */ |
34 | 34 | ||
35 | #ifndef __ia32_INTERRUPT_H__ |
35 | #ifndef __ia32_INTERRUPT_H__ |
36 | #define __ia32_INTERRUPT_H__ |
36 | #define __ia32_INTERRUPT_H__ |
37 | 37 | ||
38 | #include <arch/types.h> |
38 | #include <arch/types.h> |
39 | #include <arch/pm.h> |
39 | #include <arch/pm.h> |
40 | 40 | ||
41 | #define IVT_ITEMS IDT_ITEMS |
41 | #define IVT_ITEMS IDT_ITEMS |
42 | 42 | ||
43 | #define EXC_COUNT 32 |
43 | #define EXC_COUNT 32 |
44 | #define IRQ_COUNT 16 |
44 | #define IRQ_COUNT 16 |
45 | 45 | ||
46 | #define IVT_EXCBASE 0 |
46 | #define IVT_EXCBASE 0 |
47 | #define IVT_IRQBASE (IVT_EXCBASE+EXC_COUNT) |
47 | #define IVT_IRQBASE (IVT_EXCBASE+EXC_COUNT) |
48 | #define IVT_FREEBASE (IVT_IRQBASE+IRQ_COUNT) |
48 | #define IVT_FREEBASE (IVT_IRQBASE+IRQ_COUNT) |
49 | 49 | ||
50 | #define IRQ_CLK 0 |
50 | #define IRQ_CLK 0 |
51 | #define IRQ_KBD 1 |
51 | #define IRQ_KBD 1 |
52 | #define IRQ_PIC1 2 |
52 | #define IRQ_PIC1 2 |
53 | #define IRQ_PIC_SPUR 7 |
53 | #define IRQ_PIC_SPUR 7 |
54 | 54 | ||
55 | /* this one must have four least significant bits set to ones */ |
55 | /* this one must have four least significant bits set to ones */ |
56 | #define VECTOR_APIC_SPUR (IVT_ITEMS-1) |
56 | #define VECTOR_APIC_SPUR (IVT_ITEMS-1) |
57 | 57 | ||
58 | #if (((VECTOR_APIC_SPUR + 1)%16) || VECTOR_APIC_SPUR >= IVT_ITEMS) |
58 | #if (((VECTOR_APIC_SPUR + 1)%16) || VECTOR_APIC_SPUR >= IVT_ITEMS) |
59 | #error Wrong definition of VECTOR_APIC_SPUR |
59 | #error Wrong definition of VECTOR_APIC_SPUR |
60 | #endif |
60 | #endif |
61 | 61 | ||
62 | #define VECTOR_DEBUG 1 |
62 | #define VECTOR_DEBUG 1 |
63 | #define VECTOR_PIC_SPUR (IVT_IRQBASE+IRQ_PIC_SPUR) |
63 | #define VECTOR_PIC_SPUR (IVT_IRQBASE+IRQ_PIC_SPUR) |
64 | #define VECTOR_CLK (IVT_IRQBASE+IRQ_CLK) |
64 | #define VECTOR_CLK (IVT_IRQBASE+IRQ_CLK) |
65 | #define VECTOR_KBD (IVT_IRQBASE+IRQ_KBD) |
65 | #define VECTOR_KBD (IVT_IRQBASE+IRQ_KBD) |
66 | 66 | ||
67 | #define VECTOR_TLB_SHOOTDOWN_IPI (IVT_FREEBASE+0) |
67 | #define VECTOR_TLB_SHOOTDOWN_IPI (IVT_FREEBASE+0) |
68 | #define VECTOR_WAKEUP_IPI (IVT_FREEBASE+1) |
68 | #define VECTOR_WAKEUP_IPI (IVT_FREEBASE+1) |
69 | #define VECTOR_DEBUG_IPI (IVT_FREEBASE+2) |
69 | #define VECTOR_DEBUG_IPI (IVT_FREEBASE+2) |
70 | 70 | ||
71 | /** This is passed to interrupt handlers */ |
71 | /** This is passed to interrupt handlers */ |
72 | struct istate { |
72 | struct istate { |
73 | __u64 rax; |
73 | uint64_t rax; |
74 | __u64 rbx; |
74 | uint64_t rbx; |
75 | __u64 rcx; |
75 | uint64_t rcx; |
76 | __u64 rdx; |
76 | uint64_t rdx; |
77 | __u64 rsi; |
77 | uint64_t rsi; |
78 | __u64 rdi; |
78 | uint64_t rdi; |
79 | __u64 r8; |
79 | uint64_t r8; |
80 | __u64 r9; |
80 | uint64_t r9; |
81 | __u64 r10; |
81 | uint64_t r10; |
82 | __u64 r11; |
82 | uint64_t r11; |
83 | __u64 r12; |
83 | uint64_t r12; |
84 | __u64 r13; |
84 | uint64_t r13; |
85 | __u64 r14; |
85 | uint64_t r14; |
86 | __u64 r15; |
86 | uint64_t r15; |
87 | __u64 rbp; |
87 | uint64_t rbp; |
88 | __u64 error_word; |
88 | uint64_t error_word; |
89 | __u64 rip; |
89 | uint64_t rip; |
90 | __u64 cs; |
90 | uint64_t cs; |
91 | __u64 rflags; |
91 | uint64_t rflags; |
92 | __u64 stack[]; /* Additional data on stack */ |
92 | uint64_t stack[]; /* Additional data on stack */ |
93 | }; |
93 | }; |
94 | 94 | ||
95 | /** Return true if exception happened while in userspace */ |
95 | /** Return true if exception happened while in userspace */ |
96 | static inline int istate_from_uspace(istate_t *istate) |
96 | static inline int istate_from_uspace(istate_t *istate) |
97 | { |
97 | { |
98 | return !(istate->rip & 0x8000000000000000); |
98 | return !(istate->rip & 0x8000000000000000); |
99 | } |
99 | } |
100 | 100 | ||
101 | static inline void istate_set_retaddr(istate_t *istate, __address retaddr) |
101 | static inline void istate_set_retaddr(istate_t *istate, uintptr_t retaddr) |
102 | { |
102 | { |
103 | istate->rip = retaddr; |
103 | istate->rip = retaddr; |
104 | } |
104 | } |
105 | static inline __native istate_get_pc(istate_t *istate) |
105 | static inline unative_t istate_get_pc(istate_t *istate) |
106 | { |
106 | { |
107 | return istate->rip; |
107 | return istate->rip; |
108 | } |
108 | } |
109 | 109 | ||
110 | extern void (* disable_irqs_function)(__u16 irqmask); |
110 | extern void (* disable_irqs_function)(uint16_t irqmask); |
111 | extern void (* enable_irqs_function)(__u16 irqmask); |
111 | extern void (* enable_irqs_function)(uint16_t irqmask); |
112 | extern void (* eoi_function)(void); |
112 | extern void (* eoi_function)(void); |
113 | 113 | ||
114 | extern void print_info_errcode(int n, istate_t *istate); |
114 | extern void print_info_errcode(int n, istate_t *istate); |
115 | extern void null_interrupt(int n, istate_t *istate); |
115 | extern void null_interrupt(int n, istate_t *istate); |
116 | extern void gp_fault(int n, istate_t *istate); |
116 | extern void gp_fault(int n, istate_t *istate); |
117 | extern void nm_fault(int n, istate_t *istate); |
117 | extern void nm_fault(int n, istate_t *istate); |
118 | extern void ss_fault(int n, istate_t *istate); |
118 | extern void ss_fault(int n, istate_t *istate); |
119 | extern void page_fault(int n, istate_t *istate); |
119 | extern void page_fault(int n, istate_t *istate); |
120 | extern void syscall(int n, istate_t *istate); |
120 | extern void syscall(int n, istate_t *istate); |
121 | extern void tlb_shootdown_ipi(int n, istate_t *istate); |
121 | extern void tlb_shootdown_ipi(int n, istate_t *istate); |
122 | 122 | ||
123 | extern void trap_virtual_enable_irqs(__u16 irqmask); |
123 | extern void trap_virtual_enable_irqs(uint16_t irqmask); |
124 | extern void trap_virtual_disable_irqs(__u16 irqmask); |
124 | extern void trap_virtual_disable_irqs(uint16_t irqmask); |
125 | extern void trap_virtual_eoi(void); |
125 | extern void trap_virtual_eoi(void); |
126 | /* AMD64 - specific page handler */ |
126 | /* AMD64 - specific page handler */ |
127 | extern void ident_page_fault(int n, istate_t *istate); |
127 | extern void ident_page_fault(int n, istate_t *istate); |
128 | 128 | ||
129 | #endif |
129 | #endif |
130 | 130 | ||
131 | /** @} |
131 | /** @} |
132 | */ |
132 | */ |
133 | 133 | ||
134 | 134 |