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1 | /* |
1 | /* |
2 | * Copyright (c) 2005 Jakub Jermar |
2 | * Copyright (c) 2005 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup amd64 |
29 | /** @addtogroup amd64 |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | */ |
33 | */ |
34 | 34 | ||
35 | #ifndef KERN_amd64_ASM_H_ |
35 | #ifndef KERN_amd64_ASM_H_ |
36 | #define KERN_amd64_ASM_H_ |
36 | #define KERN_amd64_ASM_H_ |
37 | 37 | ||
38 | #include <config.h> |
38 | #include <config.h> |
39 | 39 | ||
40 | extern void asm_delay_loop(uint32_t t); |
40 | extern void asm_delay_loop(uint32_t t); |
41 | extern void asm_fake_loop(uint32_t t); |
41 | extern void asm_fake_loop(uint32_t t); |
42 | 42 | ||
43 | /** Return base address of current stack. |
43 | /** Return base address of current stack. |
44 | * |
44 | * |
45 | * Return the base address of the current stack. |
45 | * Return the base address of the current stack. |
46 | * The stack is assumed to be STACK_SIZE bytes long. |
46 | * The stack is assumed to be STACK_SIZE bytes long. |
47 | * The stack must start on page boundary. |
47 | * The stack must start on page boundary. |
48 | */ |
48 | */ |
49 | static inline uintptr_t get_stack_base(void) |
49 | static inline uintptr_t get_stack_base(void) |
50 | { |
50 | { |
51 | uintptr_t v; |
51 | uintptr_t v; |
52 | 52 | ||
53 | asm volatile ("andq %%rsp, %0\n" : "=r" (v) : "0" (~((uint64_t)STACK_SIZE-1))); |
53 | asm volatile ("andq %%rsp, %0\n" : "=r" (v) : "0" (~((uint64_t)STACK_SIZE-1))); |
54 | 54 | ||
55 | return v; |
55 | return v; |
56 | } |
56 | } |
57 | 57 | ||
58 | static inline void cpu_sleep(void) |
58 | static inline void cpu_sleep(void) |
59 | { |
59 | { |
60 | asm volatile ("hlt\n"); |
60 | asm volatile ("hlt\n"); |
61 | } |
61 | } |
62 | 62 | ||
63 | static inline void cpu_halt(void) |
63 | static inline void cpu_halt(void) |
64 | { |
64 | { |
65 | asm volatile ("hlt\n"); |
65 | asm volatile ("hlt\n"); |
66 | } |
66 | } |
67 | 67 | ||
68 | 68 | ||
69 | /** Byte from port |
69 | /** Byte from port |
70 | * |
70 | * |
71 | * Get byte from port |
71 | * Get byte from port |
72 | * |
72 | * |
73 | * @param port Port to read from |
73 | * @param port Port to read from |
74 | * @return Value read |
74 | * @return Value read |
75 | */ |
75 | */ |
76 | static inline uint8_t pio_read_8(ioport8_t *port) |
76 | static inline uint8_t pio_read_8(ioport8_t *port) |
77 | { |
77 | { |
78 | uint8_t val; |
78 | uint8_t val; |
79 | 79 | ||
80 | asm volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port)); |
80 | asm volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port)); |
81 | return val; |
81 | return val; |
82 | } |
82 | } |
83 | 83 | ||
- | 84 | /** Word from port |
|
- | 85 | * |
|
- | 86 | * Get word from port |
|
- | 87 | * |
|
- | 88 | * @param port Port to read from |
|
- | 89 | * @return Value read |
|
- | 90 | */ |
|
- | 91 | static inline uint16_t pio_read_16(ioport16_t *port) |
|
- | 92 | { |
|
- | 93 | uint16_t val; |
|
- | 94 | ||
- | 95 | asm volatile ("inw %w1, %w0 \n" : "=a" (val) : "d" (port)); |
|
- | 96 | return val; |
|
- | 97 | } |
|
- | 98 | ||
- | 99 | /** Double word from port |
|
- | 100 | * |
|
- | 101 | * Get double word from port |
|
- | 102 | * |
|
- | 103 | * @param port Port to read from |
|
- | 104 | * @return Value read |
|
- | 105 | */ |
|
- | 106 | static inline uint32_t pio_read_32(ioport32_t *port) |
|
- | 107 | { |
|
- | 108 | uint32_t val; |
|
- | 109 | ||
- | 110 | asm volatile ("inl %w1, %0 \n" : "=a" (val) : "d" (port)); |
|
- | 111 | return val; |
|
- | 112 | } |
|
- | 113 | ||
84 | /** Byte to port |
114 | /** Byte to port |
85 | * |
115 | * |
86 | * Output byte to port |
116 | * Output byte to port |
87 | * |
117 | * |
88 | * @param port Port to write to |
118 | * @param port Port to write to |
89 | * @param val Value to write |
119 | * @param val Value to write |
90 | */ |
120 | */ |
91 | static inline void pio_write_8(ioport8_t *port, uint8_t val) |
121 | static inline void pio_write_8(ioport8_t *port, uint8_t val) |
92 | { |
122 | { |
93 | asm volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port)); |
123 | asm volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port)); |
94 | } |
124 | } |
- | 125 | ||
- | 126 | /** Word to port |
|
- | 127 | * |
|
- | 128 | * Output word to port |
|
- | 129 | * |
|
- | 130 | * @param port Port to write to |
|
- | 131 | * @param val Value to write |
|
- | 132 | */ |
|
- | 133 | static inline void pio_write_16(ioport16_t *port, uint16_t val) |
|
- | 134 | { |
|
- | 135 | asm volatile ("outw %w0, %w1\n" : : "a" (val), "d" (port)); |
|
- | 136 | } |
|
- | 137 | ||
- | 138 | /** Double word to port |
|
- | 139 | * |
|
- | 140 | * Output double word to port |
|
- | 141 | * |
|
- | 142 | * @param port Port to write to |
|
- | 143 | * @param val Value to write |
|
- | 144 | */ |
|
- | 145 | static inline void pio_write_32(ioport32_t *port, uint32_t val) |
|
- | 146 | { |
|
- | 147 | asm volatile ("outl %0, %w1\n" : : "a" (val), "d" (port)); |
|
- | 148 | } |
|
95 | 149 | ||
96 | /** Swap Hidden part of GS register with visible one */ |
150 | /** Swap Hidden part of GS register with visible one */ |
97 | static inline void swapgs(void) |
151 | static inline void swapgs(void) |
98 | { |
152 | { |
99 | asm volatile("swapgs"); |
153 | asm volatile("swapgs"); |
100 | } |
154 | } |
101 | 155 | ||
102 | /** Enable interrupts. |
156 | /** Enable interrupts. |
103 | * |
157 | * |
104 | * Enable interrupts and return previous |
158 | * Enable interrupts and return previous |
105 | * value of EFLAGS. |
159 | * value of EFLAGS. |
106 | * |
160 | * |
107 | * @return Old interrupt priority level. |
161 | * @return Old interrupt priority level. |
108 | */ |
162 | */ |
109 | static inline ipl_t interrupts_enable(void) { |
163 | static inline ipl_t interrupts_enable(void) { |
110 | ipl_t v; |
164 | ipl_t v; |
111 | __asm__ volatile ( |
165 | __asm__ volatile ( |
112 | "pushfq\n" |
166 | "pushfq\n" |
113 | "popq %0\n" |
167 | "popq %0\n" |
114 | "sti\n" |
168 | "sti\n" |
115 | : "=r" (v) |
169 | : "=r" (v) |
116 | ); |
170 | ); |
117 | return v; |
171 | return v; |
118 | } |
172 | } |
119 | 173 | ||
120 | /** Disable interrupts. |
174 | /** Disable interrupts. |
121 | * |
175 | * |
122 | * Disable interrupts and return previous |
176 | * Disable interrupts and return previous |
123 | * value of EFLAGS. |
177 | * value of EFLAGS. |
124 | * |
178 | * |
125 | * @return Old interrupt priority level. |
179 | * @return Old interrupt priority level. |
126 | */ |
180 | */ |
127 | static inline ipl_t interrupts_disable(void) { |
181 | static inline ipl_t interrupts_disable(void) { |
128 | ipl_t v; |
182 | ipl_t v; |
129 | __asm__ volatile ( |
183 | __asm__ volatile ( |
130 | "pushfq\n" |
184 | "pushfq\n" |
131 | "popq %0\n" |
185 | "popq %0\n" |
132 | "cli\n" |
186 | "cli\n" |
133 | : "=r" (v) |
187 | : "=r" (v) |
134 | ); |
188 | ); |
135 | return v; |
189 | return v; |
136 | } |
190 | } |
137 | 191 | ||
138 | /** Restore interrupt priority level. |
192 | /** Restore interrupt priority level. |
139 | * |
193 | * |
140 | * Restore EFLAGS. |
194 | * Restore EFLAGS. |
141 | * |
195 | * |
142 | * @param ipl Saved interrupt priority level. |
196 | * @param ipl Saved interrupt priority level. |
143 | */ |
197 | */ |
144 | static inline void interrupts_restore(ipl_t ipl) { |
198 | static inline void interrupts_restore(ipl_t ipl) { |
145 | __asm__ volatile ( |
199 | __asm__ volatile ( |
146 | "pushq %0\n" |
200 | "pushq %0\n" |
147 | "popfq\n" |
201 | "popfq\n" |
148 | : : "r" (ipl) |
202 | : : "r" (ipl) |
149 | ); |
203 | ); |
150 | } |
204 | } |
151 | 205 | ||
152 | /** Return interrupt priority level. |
206 | /** Return interrupt priority level. |
153 | * |
207 | * |
154 | * Return EFLAFS. |
208 | * Return EFLAFS. |
155 | * |
209 | * |
156 | * @return Current interrupt priority level. |
210 | * @return Current interrupt priority level. |
157 | */ |
211 | */ |
158 | static inline ipl_t interrupts_read(void) { |
212 | static inline ipl_t interrupts_read(void) { |
159 | ipl_t v; |
213 | ipl_t v; |
160 | __asm__ volatile ( |
214 | __asm__ volatile ( |
161 | "pushfq\n" |
215 | "pushfq\n" |
162 | "popq %0\n" |
216 | "popq %0\n" |
163 | : "=r" (v) |
217 | : "=r" (v) |
164 | ); |
218 | ); |
165 | return v; |
219 | return v; |
166 | } |
220 | } |
167 | 221 | ||
168 | /** Write to MSR */ |
222 | /** Write to MSR */ |
169 | static inline void write_msr(uint32_t msr, uint64_t value) |
223 | static inline void write_msr(uint32_t msr, uint64_t value) |
170 | { |
224 | { |
171 | __asm__ volatile ( |
225 | __asm__ volatile ( |
172 | "wrmsr;" : : "c" (msr), |
226 | "wrmsr;" : : "c" (msr), |
173 | "a" ((uint32_t)(value)), |
227 | "a" ((uint32_t)(value)), |
174 | "d" ((uint32_t)(value >> 32)) |
228 | "d" ((uint32_t)(value >> 32)) |
175 | ); |
229 | ); |
176 | } |
230 | } |
177 | 231 | ||
178 | static inline unative_t read_msr(uint32_t msr) |
232 | static inline unative_t read_msr(uint32_t msr) |
179 | { |
233 | { |
180 | uint32_t ax, dx; |
234 | uint32_t ax, dx; |
181 | 235 | ||
182 | __asm__ volatile ( |
236 | __asm__ volatile ( |
183 | "rdmsr;" : "=a"(ax), "=d"(dx) : "c" (msr) |
237 | "rdmsr;" : "=a"(ax), "=d"(dx) : "c" (msr) |
184 | ); |
238 | ); |
185 | return ((uint64_t)dx << 32) | ax; |
239 | return ((uint64_t)dx << 32) | ax; |
186 | } |
240 | } |
187 | 241 | ||
188 | 242 | ||
189 | /** Enable local APIC |
243 | /** Enable local APIC |
190 | * |
244 | * |
191 | * Enable local APIC in MSR. |
245 | * Enable local APIC in MSR. |
192 | */ |
246 | */ |
193 | static inline void enable_l_apic_in_msr() |
247 | static inline void enable_l_apic_in_msr() |
194 | { |
248 | { |
195 | __asm__ volatile ( |
249 | __asm__ volatile ( |
196 | "movl $0x1b, %%ecx\n" |
250 | "movl $0x1b, %%ecx\n" |
197 | "rdmsr\n" |
251 | "rdmsr\n" |
198 | "orl $(1<<11),%%eax\n" |
252 | "orl $(1<<11),%%eax\n" |
199 | "orl $(0xfee00000),%%eax\n" |
253 | "orl $(0xfee00000),%%eax\n" |
200 | "wrmsr\n" |
254 | "wrmsr\n" |
201 | : |
255 | : |
202 | : |
256 | : |
203 | :"%eax","%ecx","%edx" |
257 | :"%eax","%ecx","%edx" |
204 | ); |
258 | ); |
205 | } |
259 | } |
206 | 260 | ||
207 | static inline uintptr_t * get_ip() |
261 | static inline uintptr_t * get_ip() |
208 | { |
262 | { |
209 | uintptr_t *ip; |
263 | uintptr_t *ip; |
210 | 264 | ||
211 | __asm__ volatile ( |
265 | __asm__ volatile ( |
212 | "mov %%rip, %0" |
266 | "mov %%rip, %0" |
213 | : "=r" (ip) |
267 | : "=r" (ip) |
214 | ); |
268 | ); |
215 | return ip; |
269 | return ip; |
216 | } |
270 | } |
217 | 271 | ||
218 | /** Invalidate TLB Entry. |
272 | /** Invalidate TLB Entry. |
219 | * |
273 | * |
220 | * @param addr Address on a page whose TLB entry is to be invalidated. |
274 | * @param addr Address on a page whose TLB entry is to be invalidated. |
221 | */ |
275 | */ |
222 | static inline void invlpg(uintptr_t addr) |
276 | static inline void invlpg(uintptr_t addr) |
223 | { |
277 | { |
224 | __asm__ volatile ("invlpg %0\n" :: "m" (*((unative_t *)addr))); |
278 | __asm__ volatile ("invlpg %0\n" :: "m" (*((unative_t *)addr))); |
225 | } |
279 | } |
226 | 280 | ||
227 | /** Load GDTR register from memory. |
281 | /** Load GDTR register from memory. |
228 | * |
282 | * |
229 | * @param gdtr_reg Address of memory from where to load GDTR. |
283 | * @param gdtr_reg Address of memory from where to load GDTR. |
230 | */ |
284 | */ |
231 | static inline void gdtr_load(struct ptr_16_64 *gdtr_reg) |
285 | static inline void gdtr_load(struct ptr_16_64 *gdtr_reg) |
232 | { |
286 | { |
233 | __asm__ volatile ("lgdtq %0\n" : : "m" (*gdtr_reg)); |
287 | __asm__ volatile ("lgdtq %0\n" : : "m" (*gdtr_reg)); |
234 | } |
288 | } |
235 | 289 | ||
236 | /** Store GDTR register to memory. |
290 | /** Store GDTR register to memory. |
237 | * |
291 | * |
238 | * @param gdtr_reg Address of memory to where to load GDTR. |
292 | * @param gdtr_reg Address of memory to where to load GDTR. |
239 | */ |
293 | */ |
240 | static inline void gdtr_store(struct ptr_16_64 *gdtr_reg) |
294 | static inline void gdtr_store(struct ptr_16_64 *gdtr_reg) |
241 | { |
295 | { |
242 | __asm__ volatile ("sgdtq %0\n" : : "m" (*gdtr_reg)); |
296 | __asm__ volatile ("sgdtq %0\n" : : "m" (*gdtr_reg)); |
243 | } |
297 | } |
244 | 298 | ||
245 | /** Load IDTR register from memory. |
299 | /** Load IDTR register from memory. |
246 | * |
300 | * |
247 | * @param idtr_reg Address of memory from where to load IDTR. |
301 | * @param idtr_reg Address of memory from where to load IDTR. |
248 | */ |
302 | */ |
249 | static inline void idtr_load(struct ptr_16_64 *idtr_reg) |
303 | static inline void idtr_load(struct ptr_16_64 *idtr_reg) |
250 | { |
304 | { |
251 | __asm__ volatile ("lidtq %0\n" : : "m" (*idtr_reg)); |
305 | __asm__ volatile ("lidtq %0\n" : : "m" (*idtr_reg)); |
252 | } |
306 | } |
253 | 307 | ||
254 | /** Load TR from descriptor table. |
308 | /** Load TR from descriptor table. |
255 | * |
309 | * |
256 | * @param sel Selector specifying descriptor of TSS segment. |
310 | * @param sel Selector specifying descriptor of TSS segment. |
257 | */ |
311 | */ |
258 | static inline void tr_load(uint16_t sel) |
312 | static inline void tr_load(uint16_t sel) |
259 | { |
313 | { |
260 | __asm__ volatile ("ltr %0" : : "r" (sel)); |
314 | __asm__ volatile ("ltr %0" : : "r" (sel)); |
261 | } |
315 | } |
262 | 316 | ||
263 | #define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \ |
317 | #define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \ |
264 | { \ |
318 | { \ |
265 | unative_t res; \ |
319 | unative_t res; \ |
266 | __asm__ volatile ("movq %%" #reg ", %0" : "=r" (res) ); \ |
320 | __asm__ volatile ("movq %%" #reg ", %0" : "=r" (res) ); \ |
267 | return res; \ |
321 | return res; \ |
268 | } |
322 | } |
269 | 323 | ||
270 | #define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \ |
324 | #define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \ |
271 | { \ |
325 | { \ |
272 | __asm__ volatile ("movq %0, %%" #reg : : "r" (regn)); \ |
326 | __asm__ volatile ("movq %0, %%" #reg : : "r" (regn)); \ |
273 | } |
327 | } |
274 | 328 | ||
275 | GEN_READ_REG(cr0) |
329 | GEN_READ_REG(cr0) |
276 | GEN_READ_REG(cr2) |
330 | GEN_READ_REG(cr2) |
277 | GEN_READ_REG(cr3) |
331 | GEN_READ_REG(cr3) |
278 | GEN_WRITE_REG(cr3) |
332 | GEN_WRITE_REG(cr3) |
279 | 333 | ||
280 | GEN_READ_REG(dr0) |
334 | GEN_READ_REG(dr0) |
281 | GEN_READ_REG(dr1) |
335 | GEN_READ_REG(dr1) |
282 | GEN_READ_REG(dr2) |
336 | GEN_READ_REG(dr2) |
283 | GEN_READ_REG(dr3) |
337 | GEN_READ_REG(dr3) |
284 | GEN_READ_REG(dr6) |
338 | GEN_READ_REG(dr6) |
285 | GEN_READ_REG(dr7) |
339 | GEN_READ_REG(dr7) |
286 | 340 | ||
287 | GEN_WRITE_REG(dr0) |
341 | GEN_WRITE_REG(dr0) |
288 | GEN_WRITE_REG(dr1) |
342 | GEN_WRITE_REG(dr1) |
289 | GEN_WRITE_REG(dr2) |
343 | GEN_WRITE_REG(dr2) |
290 | GEN_WRITE_REG(dr3) |
344 | GEN_WRITE_REG(dr3) |
291 | GEN_WRITE_REG(dr6) |
345 | GEN_WRITE_REG(dr6) |
292 | GEN_WRITE_REG(dr7) |
346 | GEN_WRITE_REG(dr7) |
293 | 347 | ||
294 | extern size_t interrupt_handler_size; |
348 | extern size_t interrupt_handler_size; |
295 | extern void interrupt_handlers(void); |
349 | extern void interrupt_handlers(void); |
296 | 350 | ||
297 | #endif |
351 | #endif |
298 | 352 | ||
299 | /** @} |
353 | /** @} |
300 | */ |
354 | */ |
301 | 355 |