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1 | /* |
1 | /* |
2 | * Copyright (C) 2006 Ondrej Palkovsky |
2 | * Copyright (C) 2006 Ondrej Palkovsky |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** IRQ notification framework |
29 | /** IRQ notification framework |
30 | * |
30 | * |
31 | * This framework allows applications to register to receive a notification |
31 | * This framework allows applications to register to receive a notification |
32 | * when interrupt is detected. The application may provide a simple 'top-half' |
32 | * when interrupt is detected. The application may provide a simple 'top-half' |
33 | * handler as part of its registration, which can perform simple operations |
33 | * handler as part of its registration, which can perform simple operations |
34 | * (read/write port/memory, add information to notification ipc message). |
34 | * (read/write port/memory, add information to notification ipc message). |
35 | * |
35 | * |
36 | * The structure of a notification message is as follows: |
36 | * The structure of a notification message is as follows: |
37 | * - METHOD: IPC_M_INTERRUPT |
37 | * - METHOD: IPC_M_INTERRUPT |
38 | * - ARG1: interrupt number |
38 | * - ARG1: interrupt number |
39 | * - ARG2: payload modified by a 'top-half' handler |
39 | * - ARG2: payload modified by a 'top-half' handler |
40 | * - ARG3: interrupt counter (may be needed to assure correct order |
40 | * - ARG3: interrupt counter (may be needed to assure correct order |
41 | * in multithreaded drivers) |
41 | * in multithreaded drivers) |
42 | */ |
42 | */ |
43 | 43 | ||
44 | #include <arch.h> |
44 | #include <arch.h> |
45 | #include <mm/slab.h> |
45 | #include <mm/slab.h> |
46 | #include <errno.h> |
46 | #include <errno.h> |
47 | #include <ipc/ipc.h> |
47 | #include <ipc/ipc.h> |
48 | #include <ipc/irq.h> |
48 | #include <ipc/irq.h> |
49 | #include <atomic.h> |
49 | #include <atomic.h> |
- | 50 | #include <syscall/copy.h> |
|
50 | 51 | ||
51 | typedef struct { |
52 | typedef struct { |
52 | SPINLOCK_DECLARE(lock); |
53 | SPINLOCK_DECLARE(lock); |
53 | answerbox_t *box; |
54 | answerbox_t *box; |
54 | irq_code_t *code; |
55 | irq_code_t *code; |
55 | atomic_t counter; |
56 | atomic_t counter; |
56 | } ipc_irq_t; |
57 | } ipc_irq_t; |
57 | 58 | ||
58 | 59 | ||
59 | static ipc_irq_t *irq_conns = NULL; |
60 | static ipc_irq_t *irq_conns = NULL; |
60 | static int irq_conns_size; |
61 | static int irq_conns_size; |
61 | 62 | ||
62 | #include <print.h> |
63 | #include <print.h> |
63 | /* Execute code associated with IRQ notification */ |
64 | /* Execute code associated with IRQ notification */ |
64 | static void code_execute(call_t *call, irq_code_t *code) |
65 | static void code_execute(call_t *call, irq_code_t *code) |
65 | { |
66 | { |
66 | int i; |
67 | int i; |
67 | 68 | ||
68 | if (!code) |
69 | if (!code) |
69 | return; |
70 | return; |
70 | 71 | ||
71 | for (i=0; i < code->cmdcount;i++) { |
72 | for (i=0; i < code->cmdcount;i++) { |
72 | switch (code->cmds[i].cmd) { |
73 | switch (code->cmds[i].cmd) { |
73 | case CMD_MEM_READ_1: |
74 | case CMD_MEM_READ_1: |
74 | IPC_SET_ARG2(call->data, *((__u8 *)code->cmds[i].addr)); |
75 | IPC_SET_ARG2(call->data, *((__u8 *)code->cmds[i].addr)); |
75 | break; |
76 | break; |
76 | case CMD_MEM_READ_2: |
77 | case CMD_MEM_READ_2: |
77 | IPC_SET_ARG2(call->data, *((__u16 *)code->cmds[i].addr)); |
78 | IPC_SET_ARG2(call->data, *((__u16 *)code->cmds[i].addr)); |
78 | break; |
79 | break; |
79 | case CMD_MEM_READ_4: |
80 | case CMD_MEM_READ_4: |
80 | IPC_SET_ARG2(call->data, *((__u32 *)code->cmds[i].addr)); |
81 | IPC_SET_ARG2(call->data, *((__u32 *)code->cmds[i].addr)); |
81 | break; |
82 | break; |
82 | case CMD_MEM_READ_8: |
83 | case CMD_MEM_READ_8: |
83 | IPC_SET_ARG2(call->data, *((__u64 *)code->cmds[i].addr)); |
84 | IPC_SET_ARG2(call->data, *((__u64 *)code->cmds[i].addr)); |
84 | break; |
85 | break; |
85 | case CMD_MEM_WRITE_1: |
86 | case CMD_MEM_WRITE_1: |
86 | *((__u8 *)code->cmds[i].addr) = code->cmds[i].value; |
87 | *((__u8 *)code->cmds[i].addr) = code->cmds[i].value; |
87 | break; |
88 | break; |
88 | case CMD_MEM_WRITE_2: |
89 | case CMD_MEM_WRITE_2: |
89 | *((__u16 *)code->cmds[i].addr) = code->cmds[i].value; |
90 | *((__u16 *)code->cmds[i].addr) = code->cmds[i].value; |
90 | break; |
91 | break; |
91 | case CMD_MEM_WRITE_4: |
92 | case CMD_MEM_WRITE_4: |
92 | *((__u32 *)code->cmds[i].addr) = code->cmds[i].value; |
93 | *((__u32 *)code->cmds[i].addr) = code->cmds[i].value; |
93 | break; |
94 | break; |
94 | case CMD_MEM_WRITE_8: |
95 | case CMD_MEM_WRITE_8: |
95 | *((__u64 *)code->cmds[i].addr) = code->cmds[i].value; |
96 | *((__u64 *)code->cmds[i].addr) = code->cmds[i].value; |
96 | break; |
97 | break; |
97 | #if defined(ia32) || defined(amd64) |
98 | #if defined(ia32) || defined(amd64) |
98 | case CMD_PORT_READ_1: |
99 | case CMD_PORT_READ_1: |
99 | IPC_SET_ARG2(call->data, inb((long)code->cmds[i].addr)); |
100 | IPC_SET_ARG2(call->data, inb((long)code->cmds[i].addr)); |
100 | break; |
101 | break; |
101 | case CMD_PORT_WRITE_1: |
102 | case CMD_PORT_WRITE_1: |
102 | outb((long)code->cmds[i].addr, code->cmds[i].value); |
103 | outb((long)code->cmds[i].addr, code->cmds[i].value); |
103 | break; |
104 | break; |
104 | #endif |
105 | #endif |
105 | default: |
106 | default: |
106 | break; |
107 | break; |
107 | } |
108 | } |
108 | } |
109 | } |
109 | } |
110 | } |
110 | 111 | ||
111 | static void code_free(irq_code_t *code) |
112 | static void code_free(irq_code_t *code) |
112 | { |
113 | { |
113 | if (code) { |
114 | if (code) { |
114 | free(code->cmds); |
115 | free(code->cmds); |
115 | free(code); |
116 | free(code); |
116 | } |
117 | } |
117 | } |
118 | } |
118 | 119 | ||
119 | static irq_code_t * code_from_uspace(irq_code_t *ucode) |
120 | static irq_code_t * code_from_uspace(irq_code_t *ucode) |
120 | { |
121 | { |
121 | irq_code_t *code; |
122 | irq_code_t *code; |
122 | irq_cmd_t *ucmds; |
123 | irq_cmd_t *ucmds; |
- | 124 | int rc; |
|
123 | 125 | ||
124 | code = malloc(sizeof(*code), 0); |
126 | code = malloc(sizeof(*code), 0); |
125 | copy_from_uspace(code, ucode, sizeof(*code)); |
127 | rc = copy_from_uspace(code, ucode, sizeof(*code)); |
- | 128 | if (rc != 0) { |
|
- | 129 | free(code); |
|
- | 130 | return NULL; |
|
- | 131 | } |
|
126 | 132 | ||
127 | if (code->cmdcount > IRQ_MAX_PROG_SIZE) { |
133 | if (code->cmdcount > IRQ_MAX_PROG_SIZE) { |
128 | free(code); |
134 | free(code); |
129 | return NULL; |
135 | return NULL; |
130 | } |
136 | } |
131 | ucmds = code->cmds; |
137 | ucmds = code->cmds; |
132 | code->cmds = malloc(sizeof(code->cmds[0]) * (code->cmdcount), 0); |
138 | code->cmds = malloc(sizeof(code->cmds[0]) * (code->cmdcount), 0); |
133 | copy_from_uspace(code->cmds, ucmds, sizeof(code->cmds[0]) * (code->cmdcount)); |
139 | rc = copy_from_uspace(code->cmds, ucmds, sizeof(code->cmds[0]) * (code->cmdcount)); |
- | 140 | if (rc != 0) { |
|
- | 141 | free(code->cmds); |
|
- | 142 | free(code); |
|
- | 143 | return NULL; |
|
- | 144 | } |
|
134 | 145 | ||
135 | return code; |
146 | return code; |
136 | } |
147 | } |
137 | 148 | ||
138 | /** Unregister task from irq */ |
149 | /** Unregister task from irq */ |
139 | void ipc_irq_unregister(answerbox_t *box, int irq) |
150 | void ipc_irq_unregister(answerbox_t *box, int irq) |
140 | { |
151 | { |
141 | ipl_t ipl; |
152 | ipl_t ipl; |
142 | 153 | ||
143 | ipl = interrupts_disable(); |
154 | ipl = interrupts_disable(); |
144 | spinlock_lock(&irq_conns[irq].lock); |
155 | spinlock_lock(&irq_conns[irq].lock); |
145 | if (irq_conns[irq].box == box) { |
156 | if (irq_conns[irq].box == box) { |
146 | irq_conns[irq].box = NULL; |
157 | irq_conns[irq].box = NULL; |
147 | code_free(irq_conns[irq].code); |
158 | code_free(irq_conns[irq].code); |
148 | irq_conns[irq].code = NULL; |
159 | irq_conns[irq].code = NULL; |
149 | } |
160 | } |
150 | 161 | ||
151 | spinlock_unlock(&irq_conns[irq].lock); |
162 | spinlock_unlock(&irq_conns[irq].lock); |
152 | interrupts_restore(ipl); |
163 | interrupts_restore(ipl); |
153 | } |
164 | } |
154 | 165 | ||
155 | /** Register an answerbox as a receiving end of interrupts notifications */ |
166 | /** Register an answerbox as a receiving end of interrupts notifications */ |
156 | int ipc_irq_register(answerbox_t *box, int irq, irq_code_t *ucode) |
167 | int ipc_irq_register(answerbox_t *box, int irq, irq_code_t *ucode) |
157 | { |
168 | { |
158 | ipl_t ipl; |
169 | ipl_t ipl; |
159 | irq_code_t *code; |
170 | irq_code_t *code; |
160 | 171 | ||
161 | ASSERT(irq_conns); |
172 | ASSERT(irq_conns); |
162 | 173 | ||
163 | if (ucode) { |
174 | if (ucode) { |
164 | code = code_from_uspace(ucode); |
175 | code = code_from_uspace(ucode); |
165 | if (!code) |
176 | if (!code) |
166 | return EBADMEM; |
177 | return EBADMEM; |
167 | } else |
178 | } else |
168 | code = NULL; |
179 | code = NULL; |
169 | 180 | ||
170 | ipl = interrupts_disable(); |
181 | ipl = interrupts_disable(); |
171 | spinlock_lock(&irq_conns[irq].lock); |
182 | spinlock_lock(&irq_conns[irq].lock); |
172 | 183 | ||
173 | if (irq_conns[irq].box) { |
184 | if (irq_conns[irq].box) { |
174 | spinlock_unlock(&irq_conns[irq].lock); |
185 | spinlock_unlock(&irq_conns[irq].lock); |
175 | interrupts_restore(ipl); |
186 | interrupts_restore(ipl); |
176 | code_free(code); |
187 | code_free(code); |
177 | return EEXISTS; |
188 | return EEXISTS; |
178 | } |
189 | } |
179 | irq_conns[irq].box = box; |
190 | irq_conns[irq].box = box; |
180 | irq_conns[irq].code = code; |
191 | irq_conns[irq].code = code; |
181 | atomic_set(&irq_conns[irq].counter, 0); |
192 | atomic_set(&irq_conns[irq].counter, 0); |
182 | spinlock_unlock(&irq_conns[irq].lock); |
193 | spinlock_unlock(&irq_conns[irq].lock); |
183 | interrupts_restore(ipl); |
194 | interrupts_restore(ipl); |
184 | 195 | ||
185 | return 0; |
196 | return 0; |
186 | } |
197 | } |
187 | 198 | ||
188 | /** Notify process that an irq had happend |
199 | /** Notify process that an irq had happend |
189 | * |
200 | * |
190 | * We expect interrupts to be disabled |
201 | * We expect interrupts to be disabled |
191 | */ |
202 | */ |
192 | void ipc_irq_send_notif(int irq) |
203 | void ipc_irq_send_notif(int irq) |
193 | { |
204 | { |
194 | call_t *call; |
205 | call_t *call; |
195 | 206 | ||
196 | ASSERT(irq_conns); |
207 | ASSERT(irq_conns); |
197 | spinlock_lock(&irq_conns[irq].lock); |
208 | spinlock_lock(&irq_conns[irq].lock); |
198 | 209 | ||
199 | if (irq_conns[irq].box) { |
210 | if (irq_conns[irq].box) { |
200 | call = ipc_call_alloc(FRAME_ATOMIC); |
211 | call = ipc_call_alloc(FRAME_ATOMIC); |
201 | call->flags |= IPC_CALL_NOTIF; |
212 | call->flags |= IPC_CALL_NOTIF; |
202 | IPC_SET_METHOD(call->data, IPC_M_INTERRUPT); |
213 | IPC_SET_METHOD(call->data, IPC_M_INTERRUPT); |
203 | IPC_SET_ARG1(call->data, irq); |
214 | IPC_SET_ARG1(call->data, irq); |
204 | IPC_SET_ARG3(call->data, atomic_preinc(&irq_conns[irq].counter)); |
215 | IPC_SET_ARG3(call->data, atomic_preinc(&irq_conns[irq].counter)); |
205 | 216 | ||
206 | /* Execute code to handle irq */ |
217 | /* Execute code to handle irq */ |
207 | code_execute(call, irq_conns[irq].code); |
218 | code_execute(call, irq_conns[irq].code); |
208 | 219 | ||
209 | spinlock_lock(&irq_conns[irq].box->irq_lock); |
220 | spinlock_lock(&irq_conns[irq].box->irq_lock); |
210 | list_append(&call->list, &irq_conns[irq].box->irq_notifs); |
221 | list_append(&call->list, &irq_conns[irq].box->irq_notifs); |
211 | spinlock_unlock(&irq_conns[irq].box->irq_lock); |
222 | spinlock_unlock(&irq_conns[irq].box->irq_lock); |
212 | 223 | ||
213 | waitq_wakeup(&irq_conns[irq].box->wq, 0); |
224 | waitq_wakeup(&irq_conns[irq].box->wq, 0); |
214 | } |
225 | } |
215 | 226 | ||
216 | spinlock_unlock(&irq_conns[irq].lock); |
227 | spinlock_unlock(&irq_conns[irq].lock); |
217 | } |
228 | } |
218 | 229 | ||
219 | 230 | ||
220 | /** Initialize table of interrupt handlers */ |
231 | /** Initialize table of interrupt handlers */ |
221 | void ipc_irq_make_table(int irqcount) |
232 | void ipc_irq_make_table(int irqcount) |
222 | { |
233 | { |
223 | int i; |
234 | int i; |
224 | 235 | ||
225 | irq_conns_size = irqcount; |
236 | irq_conns_size = irqcount; |
226 | irq_conns = malloc(irqcount * (sizeof(*irq_conns)), 0); |
237 | irq_conns = malloc(irqcount * (sizeof(*irq_conns)), 0); |
227 | for (i=0; i < irqcount; i++) { |
238 | for (i=0; i < irqcount; i++) { |
228 | spinlock_initialize(&irq_conns[i].lock, "irq_ipc_lock"); |
239 | spinlock_initialize(&irq_conns[i].lock, "irq_ipc_lock"); |
229 | irq_conns[i].box = NULL; |
240 | irq_conns[i].box = NULL; |
230 | irq_conns[i].code = NULL; |
241 | irq_conns[i].code = NULL; |
231 | } |
242 | } |
232 | } |
243 | } |
233 | 244 | ||
234 | /** Disconnect all irq's notifications |
245 | /** Disconnect all irq's notifications |
235 | * |
246 | * |
236 | * TODO: It may be better to do some linked list, so that |
247 | * TODO: It may be better to do some linked list, so that |
237 | * we wouldn't need to go through whole array every cleanup |
248 | * we wouldn't need to go through whole array every cleanup |
238 | */ |
249 | */ |
239 | void ipc_irq_cleanup(answerbox_t *box) |
250 | void ipc_irq_cleanup(answerbox_t *box) |
240 | { |
251 | { |
241 | int i; |
252 | int i; |
242 | ipl_t ipl; |
253 | ipl_t ipl; |
243 | 254 | ||
244 | for (i=0; i < irq_conns_size; i++) { |
255 | for (i=0; i < irq_conns_size; i++) { |
245 | ipl = interrupts_disable(); |
256 | ipl = interrupts_disable(); |
246 | spinlock_lock(&irq_conns[i].lock); |
257 | spinlock_lock(&irq_conns[i].lock); |
247 | if (irq_conns[i].box == box) |
258 | if (irq_conns[i].box == box) |
248 | irq_conns[i].box = NULL; |
259 | irq_conns[i].box = NULL; |
249 | spinlock_unlock(&irq_conns[i].lock); |
260 | spinlock_unlock(&irq_conns[i].lock); |
250 | interrupts_restore(ipl); |
261 | interrupts_restore(ipl); |
251 | } |
262 | } |
252 | } |
263 | } |
253 | 264 |