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| Rev 532 | Rev 534 | ||
|---|---|---|---|
| 1 | Memory management |
1 | Memory management |
| 2 | ================= |
2 | ================= |
| 3 | 3 | ||
| 4 | SPARTAN kernel deploys generic interface for 4-level page tables, |
4 | SPARTAN kernel deploys generic interface for 4-level page tables, |
| 5 | no matter what the real underlying hardware architecture is. |
5 | no matter what the real underlying hardware architecture is. |
| 6 | 6 | ||
| 7 | 7 | ||
| 8 | VADDR |
8 | VADDR |
| 9 | +-----------------------------------------------------------------------------+ |
9 | +-----------------------------------------------------------------------------+ |
| 10 | | PTL0_INDEX | PTL1_INDEX | PTL2_INDEX | PTL3_INDEX | OFFSET | |
10 | | PTL0_INDEX | PTL1_INDEX | PTL2_INDEX | PTL3_INDEX | OFFSET | |
| 11 | +-----------------------------------------------------------------------------+ |
11 | +-----------------------------------------------------------------------------+ |
| 12 | 12 | ||
| 13 | 13 | ||
| 14 | PTL0 PTL1 PTL2 PTL3 |
14 | PTL0 PTL1 PTL2 PTL3 |
| 15 | +--------+ +--------+ +--------+ +--------+ |
15 | +--------+ +--------+ +--------+ +--------+ |
| 16 | | | | | | PTL3 | -----\ | | |
16 | | | | | | PTL3 | -----\ | | |
| 17 | | | | | +--------+ | | | |
17 | | | | | +--------+ | | | |
| 18 | | | +--------+ | | | | | |
18 | | | +--------+ | | | | | |
| 19 | | | | PTL2 | -----\ | | | | | |
19 | | | | PTL2 | -----\ | | | | | |
| 20 | | | +--------+ | | | | | | |
20 | | | +--------+ | | | | | | |
| 21 | | | | | | | | | +--------+ |
21 | | | | | | | | | +--------+ |
| 22 | +--------+ | | | | | | | FRAME | |
22 | +--------+ | | | | | | | FRAME | |
| 23 | | PTL1 | -----\ | | | | | | +--------+ |
23 | | PTL1 | -----\ | | | | | | +--------+ |
| 24 | +--------+ | | | | | | | | | |
24 | +--------+ | | | | | | | | | |
| 25 | | | | | | | | | | | | |
25 | | | | | | | | | | | | |
| 26 | | | | | | | | | | | | |
26 | | | | | | | | | | | | |
| 27 | +--------+ \----> +--------+ \----> +--------+ \----> +--------+ |
27 | +--------+ \----> +--------+ \----> +--------+ \----> +--------+ |
| 28 | ^ |
28 | ^ |
| 29 | | |
29 | | |
| 30 | | |
30 | | |
| 31 | +--------+ |
31 | +--------+ |
| 32 | | PTL0 | |
32 | | PTL0 | |
| 33 | +--------+ |
33 | +--------+ |
| 34 | 34 | ||
| 35 | 35 | ||
| 36 | PTL0 Page Table Level 0 (Page Directory) |
36 | PTL0 Page Table Level 0 (Page Directory) |
| 37 | PTL1 Page Table Level 1 |
37 | PTL1 Page Table Level 1 |
| 38 | PTL2 Page Table Level 2 |
38 | PTL2 Page Table Level 2 |
| 39 | PTL3 Page Table Level 3 |
39 | PTL3 Page Table Level 3 |
| 40 | 40 | ||
| 41 | PTL0_INDEX Index into PTL0 |
41 | PTL0_INDEX Index into PTL0 |
| 42 | PTL1_INDEX Index into PTL1 |
42 | PTL1_INDEX Index into PTL1 |
| 43 | PTL2_INDEX Index into PTL2 |
43 | PTL2_INDEX Index into PTL2 |
| 44 | PTL3_INDEX Index into PTL3 |
44 | PTL3_INDEX Index into PTL3 |
| 45 | 45 | ||
| 46 | VADDR Virtual address for which mapping is looked up |
46 | VADDR Virtual address for which mapping is looked up |
| 47 | FRAME Physical address of memory frame to which VADDR is mapped |
47 | FRAME Physical address of memory frame to which VADDR is mapped |
| 48 | 48 | ||
| 49 | 49 | ||
| 50 | On architectures whose hardware has fewer levels, PTL2 and, if need be, PTL1 are |
50 | On architectures whose hardware has fewer levels, PTL2 and, if need be, PTL1 are |
| 51 | left out. TLB-only architectures are to define custom format for software page |
51 | left out. TLB-only architectures are to define custom format for software page |
| 52 | tables. |
52 | tables. |
| 53 | 53 | ||