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1 | # |
1 | # |
2 | # Copyright (C) 2003-2004 Jakub Jermar |
2 | # Copyright (C) 2003-2004 Jakub Jermar |
3 | # All rights reserved. |
3 | # All rights reserved. |
4 | # |
4 | # |
5 | # Redistribution and use in source and binary forms, with or without |
5 | # Redistribution and use in source and binary forms, with or without |
6 | # modification, are permitted provided that the following conditions |
6 | # modification, are permitted provided that the following conditions |
7 | # are met: |
7 | # are met: |
8 | # |
8 | # |
9 | # - Redistributions of source code must retain the above copyright |
9 | # - Redistributions of source code must retain the above copyright |
10 | # notice, this list of conditions and the following disclaimer. |
10 | # notice, this list of conditions and the following disclaimer. |
11 | # - Redistributions in binary form must reproduce the above copyright |
11 | # - Redistributions in binary form must reproduce the above copyright |
12 | # notice, this list of conditions and the following disclaimer in the |
12 | # notice, this list of conditions and the following disclaimer in the |
13 | # documentation and/or other materials provided with the distribution. |
13 | # documentation and/or other materials provided with the distribution. |
14 | # - The name of the author may not be used to endorse or promote products |
14 | # - The name of the author may not be used to endorse or promote products |
15 | # derived from this software without specific prior written permission. |
15 | # derived from this software without specific prior written permission. |
16 | # |
16 | # |
17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | # |
27 | # |
28 | 28 | ||
29 | #define __ASM__ |
- | |
30 | - | ||
31 | #include <arch/asm/regname.h> |
29 | #include <arch/asm/regname.h> |
32 | #include <arch/mm/page.h> |
30 | #include <arch/mm/page.h> |
33 | #include <arch/asm/boot.h> |
31 | #include <arch/asm/boot.h> |
34 | #include <arch/context_offset.h> |
32 | #include <arch/context_offset.h> |
35 | 33 | ||
36 | .text |
34 | .text |
37 | 35 | ||
38 | .set noat |
36 | .set noat |
39 | .set noreorder |
37 | .set noreorder |
40 | .set nomacro |
38 | .set nomacro |
41 | 39 | ||
42 | .global kernel_image_start |
40 | .global kernel_image_start |
43 | .global tlb_refill_entry |
41 | .global tlb_refill_entry |
44 | .global cache_error_entry |
42 | .global cache_error_entry |
45 | .global exception_entry |
43 | .global exception_entry |
46 | .global userspace_asm |
44 | .global userspace_asm |
47 | 45 | ||
48 | # Save registers to space defined by \r |
46 | # Save registers to space defined by \r |
49 | # We will change $at on the way |
47 | # We will change $at on the way |
50 | .macro REGISTERS_STORE r |
48 | .macro REGISTERS_STORE r |
51 | sw $at,EOFFSET_AT(\r) |
49 | sw $at,EOFFSET_AT(\r) |
52 | sw $v0,EOFFSET_V0(\r) |
50 | sw $v0,EOFFSET_V0(\r) |
53 | sw $v1,EOFFSET_V1(\r) |
51 | sw $v1,EOFFSET_V1(\r) |
54 | sw $a0,EOFFSET_A0(\r) |
52 | sw $a0,EOFFSET_A0(\r) |
55 | sw $a1,EOFFSET_A1(\r) |
53 | sw $a1,EOFFSET_A1(\r) |
56 | sw $a2,EOFFSET_A2(\r) |
54 | sw $a2,EOFFSET_A2(\r) |
57 | sw $a3,EOFFSET_A3(\r) |
55 | sw $a3,EOFFSET_A3(\r) |
58 | sw $t0,EOFFSET_T0(\r) |
56 | sw $t0,EOFFSET_T0(\r) |
59 | sw $t1,EOFFSET_T1(\r) |
57 | sw $t1,EOFFSET_T1(\r) |
60 | sw $t2,EOFFSET_T2(\r) |
58 | sw $t2,EOFFSET_T2(\r) |
61 | sw $t3,EOFFSET_T3(\r) |
59 | sw $t3,EOFFSET_T3(\r) |
62 | sw $t4,EOFFSET_T4(\r) |
60 | sw $t4,EOFFSET_T4(\r) |
63 | sw $t5,EOFFSET_T5(\r) |
61 | sw $t5,EOFFSET_T5(\r) |
64 | sw $t6,EOFFSET_T6(\r) |
62 | sw $t6,EOFFSET_T6(\r) |
65 | sw $t7,EOFFSET_T7(\r) |
63 | sw $t7,EOFFSET_T7(\r) |
66 | sw $t8,EOFFSET_T8(\r) |
64 | sw $t8,EOFFSET_T8(\r) |
67 | sw $t9,EOFFSET_T9(\r) |
65 | sw $t9,EOFFSET_T9(\r) |
68 | 66 | ||
69 | mflo $at |
67 | mflo $at |
70 | sw $at, EOFFSET_LO(\r) |
68 | sw $at, EOFFSET_LO(\r) |
71 | mfhi $at |
69 | mfhi $at |
72 | sw $at, EOFFSET_HI(\r) |
70 | sw $at, EOFFSET_HI(\r) |
73 | 71 | ||
74 | sw $s0,EOFFSET_S0(\r) |
72 | sw $s0,EOFFSET_S0(\r) |
75 | sw $s1,EOFFSET_S1(\r) |
73 | sw $s1,EOFFSET_S1(\r) |
76 | sw $s2,EOFFSET_S2(\r) |
74 | sw $s2,EOFFSET_S2(\r) |
77 | sw $s3,EOFFSET_S3(\r) |
75 | sw $s3,EOFFSET_S3(\r) |
78 | sw $s4,EOFFSET_S4(\r) |
76 | sw $s4,EOFFSET_S4(\r) |
79 | sw $s5,EOFFSET_S5(\r) |
77 | sw $s5,EOFFSET_S5(\r) |
80 | sw $s6,EOFFSET_S6(\r) |
78 | sw $s6,EOFFSET_S6(\r) |
81 | sw $s7,EOFFSET_S7(\r) |
79 | sw $s7,EOFFSET_S7(\r) |
82 | sw $s8,EOFFSET_S8(\r) |
80 | sw $s8,EOFFSET_S8(\r) |
83 | sw $gp,EOFFSET_GP(\r) |
81 | sw $gp,EOFFSET_GP(\r) |
84 | sw $ra,EOFFSET_RA(\r) |
82 | sw $ra,EOFFSET_RA(\r) |
85 | sw $sp,EOFFSET_SP(\r) |
83 | sw $sp,EOFFSET_SP(\r) |
86 | 84 | ||
87 | mfc0 $at, $status |
85 | mfc0 $at, $status |
88 | sw $at,EOFFSET_STATUS(\r) |
86 | sw $at,EOFFSET_STATUS(\r) |
89 | mfc0 $at, $epc |
87 | mfc0 $at, $epc |
90 | sw $at,EOFFSET_EPC(\r) |
88 | sw $at,EOFFSET_EPC(\r) |
91 | .endm |
89 | .endm |
92 | 90 | ||
93 | .macro REGISTERS_LOAD r |
91 | .macro REGISTERS_LOAD r |
94 | lw $v0,EOFFSET_V0(\r) |
92 | lw $v0,EOFFSET_V0(\r) |
95 | lw $v1,EOFFSET_V1(\r) |
93 | lw $v1,EOFFSET_V1(\r) |
96 | lw $a0,EOFFSET_A0(\r) |
94 | lw $a0,EOFFSET_A0(\r) |
97 | lw $a1,EOFFSET_A1(\r) |
95 | lw $a1,EOFFSET_A1(\r) |
98 | lw $a2,EOFFSET_A2(\r) |
96 | lw $a2,EOFFSET_A2(\r) |
99 | lw $a3,EOFFSET_A3(\r) |
97 | lw $a3,EOFFSET_A3(\r) |
100 | lw $t0,EOFFSET_T0(\r) |
98 | lw $t0,EOFFSET_T0(\r) |
101 | lw $t1,EOFFSET_T1(\r) |
99 | lw $t1,EOFFSET_T1(\r) |
102 | lw $t2,EOFFSET_T2(\r) |
100 | lw $t2,EOFFSET_T2(\r) |
103 | lw $t3,EOFFSET_T3(\r) |
101 | lw $t3,EOFFSET_T3(\r) |
104 | lw $t4,EOFFSET_T4(\r) |
102 | lw $t4,EOFFSET_T4(\r) |
105 | lw $t5,EOFFSET_T5(\r) |
103 | lw $t5,EOFFSET_T5(\r) |
106 | lw $t6,EOFFSET_T6(\r) |
104 | lw $t6,EOFFSET_T6(\r) |
107 | lw $t7,EOFFSET_T7(\r) |
105 | lw $t7,EOFFSET_T7(\r) |
108 | lw $t8,EOFFSET_T8(\r) |
106 | lw $t8,EOFFSET_T8(\r) |
109 | lw $t9,EOFFSET_T9(\r) |
107 | lw $t9,EOFFSET_T9(\r) |
110 | lw $s0,EOFFSET_S0(\r) |
108 | lw $s0,EOFFSET_S0(\r) |
111 | lw $s1,EOFFSET_S1(\r) |
109 | lw $s1,EOFFSET_S1(\r) |
112 | lw $s2,EOFFSET_S2(\r) |
110 | lw $s2,EOFFSET_S2(\r) |
113 | lw $s3,EOFFSET_S3(\r) |
111 | lw $s3,EOFFSET_S3(\r) |
114 | lw $s4,EOFFSET_S4(\r) |
112 | lw $s4,EOFFSET_S4(\r) |
115 | lw $s5,EOFFSET_S5(\r) |
113 | lw $s5,EOFFSET_S5(\r) |
116 | lw $s6,EOFFSET_S6(\r) |
114 | lw $s6,EOFFSET_S6(\r) |
117 | lw $s7,EOFFSET_S7(\r) |
115 | lw $s7,EOFFSET_S7(\r) |
118 | lw $s8,EOFFSET_S8(\r) |
116 | lw $s8,EOFFSET_S8(\r) |
119 | lw $gp,EOFFSET_GP(\r) |
117 | lw $gp,EOFFSET_GP(\r) |
120 | lw $ra,EOFFSET_RA(\r) |
118 | lw $ra,EOFFSET_RA(\r) |
121 | 119 | ||
122 | lw $at,EOFFSET_LO(\r) |
120 | lw $at,EOFFSET_LO(\r) |
123 | mtlo $at |
121 | mtlo $at |
124 | lw $at,EOFFSET_HI(\r) |
122 | lw $at,EOFFSET_HI(\r) |
125 | mthi $at |
123 | mthi $at |
126 | 124 | ||
127 | lw $at,EOFFSET_STATUS(\r) |
125 | lw $at,EOFFSET_STATUS(\r) |
128 | mtc0 $at, $status |
126 | mtc0 $at, $status |
129 | lw $at,EOFFSET_EPC(\r) |
127 | lw $at,EOFFSET_EPC(\r) |
130 | mtc0 $at, $epc |
128 | mtc0 $at, $epc |
131 | 129 | ||
132 | lw $at,EOFFSET_AT(\r) |
130 | lw $at,EOFFSET_AT(\r) |
133 | lw $sp,EOFFSET_SP(\r) |
131 | lw $sp,EOFFSET_SP(\r) |
134 | .endm |
132 | .endm |
135 | 133 | ||
136 | # Move kernel stack pointer address to register K0 |
134 | # Move kernel stack pointer address to register K0 |
137 | # - if we are in user mode, load the appropriate stack |
135 | # - if we are in user mode, load the appropriate stack |
138 | # address |
136 | # address |
139 | .macro KERNEL_STACK_TO_K0 |
137 | .macro KERNEL_STACK_TO_K0 |
140 | # If we are in user mode |
138 | # If we are in user mode |
141 | mfc0 $k0, $status |
139 | mfc0 $k0, $status |
142 | andi $k0, 0x10 |
140 | andi $k0, 0x10 |
143 | 141 | ||
144 | beq $k0, $0, 1f |
142 | beq $k0, $0, 1f |
145 | add $k0, $sp, 0 |
143 | add $k0, $sp, 0 |
146 | 144 | ||
147 | # Move $k0 pointer to kernel stack |
145 | # Move $k0 pointer to kernel stack |
148 | lui $k0, %hi(supervisor_sp) |
146 | lui $k0, %hi(supervisor_sp) |
149 | ori $k0, $k0, %lo(supervisor_sp) |
147 | ori $k0, $k0, %lo(supervisor_sp) |
150 | # Move $k0 (superveisor_sp) |
148 | # Move $k0 (superveisor_sp) |
151 | lw $k0, 0($k0) |
149 | lw $k0, 0($k0) |
152 | 1: |
150 | 1: |
153 | .endm |
151 | .endm |
154 | 152 | ||
155 | .org 0x0 |
153 | .org 0x0 |
156 | kernel_image_start: |
154 | kernel_image_start: |
157 | /* Load temporary stack */ |
155 | /* Load temporary stack */ |
158 | lui $sp, %hi(end_stack) |
156 | lui $sp, %hi(end_stack) |
159 | ori $sp, $sp, %lo(end_stack) |
157 | ori $sp, $sp, %lo(end_stack) |
160 | 158 | ||
161 | /* Not sure about this, but might be needed for PIC code???? */ |
159 | /* Not sure about this, but might be needed for PIC code???? */ |
162 | lui $gp, 0x8000 |
160 | lui $gp, 0x8000 |
163 | 161 | ||
164 | jal main_bsp |
162 | jal main_bsp |
165 | nop |
163 | nop |
166 | 164 | ||
167 | 165 | ||
168 | .space TEMP_STACK_SIZE |
166 | .space TEMP_STACK_SIZE |
169 | end_stack: |
167 | end_stack: |
170 | 168 | ||
171 | tlb_refill_entry: |
169 | tlb_refill_entry: |
172 | j tlb_refill_handler |
170 | j tlb_refill_handler |
173 | nop |
171 | nop |
174 | 172 | ||
175 | cache_error_entry: |
173 | cache_error_entry: |
176 | j cache_error_handler |
174 | j cache_error_handler |
177 | nop |
175 | nop |
178 | 176 | ||
179 | exception_entry: |
177 | exception_entry: |
180 | j exception_handler |
178 | j exception_handler |
181 | nop |
179 | nop |
182 | 180 | ||
183 | 181 | ||
184 | 182 | ||
185 | exception_handler: |
183 | exception_handler: |
186 | KERNEL_STACK_TO_K0 |
184 | KERNEL_STACK_TO_K0 |
187 | sub $k0, REGISTER_SPACE |
185 | sub $k0, REGISTER_SPACE |
188 | REGISTERS_STORE $k0 |
186 | REGISTERS_STORE $k0 |
189 | add $sp, $k0, 0 |
187 | add $sp, $k0, 0 |
190 | 188 | ||
191 | add $a0, $sp, 0 |
189 | add $a0, $sp, 0 |
192 | jal exception /* exception(register_space) */ |
190 | jal exception /* exception(register_space) */ |
193 | nop |
191 | nop |
194 | 192 | ||
195 | REGISTERS_LOAD $sp |
193 | REGISTERS_LOAD $sp |
196 | # The $sp is automatically restored to former value |
194 | # The $sp is automatically restored to former value |
197 | eret |
195 | eret |
198 | nop |
196 | nop |
199 | 197 | ||
200 | tlb_refill_handler: |
198 | tlb_refill_handler: |
201 | KERNEL_STACK_TO_K0 |
199 | KERNEL_STACK_TO_K0 |
202 | sub $k0, REGISTER_SPACE |
200 | sub $k0, REGISTER_SPACE |
203 | REGISTERS_STORE $k0 |
201 | REGISTERS_STORE $k0 |
204 | add $sp, $k0, 0 |
202 | add $sp, $k0, 0 |
205 | 203 | ||
206 | add $a0, $sp, 0 |
204 | add $a0, $sp, 0 |
207 | jal tlb_refill /* tlb_refill(register_space) */ |
205 | jal tlb_refill /* tlb_refill(register_space) */ |
208 | nop |
206 | nop |
209 | 207 | ||
210 | REGISTERS_LOAD $sp |
208 | REGISTERS_LOAD $sp |
211 | 209 | ||
212 | eret |
210 | eret |
213 | nop |
211 | nop |
214 | 212 | ||
215 | cache_error_handler: |
213 | cache_error_handler: |
216 | KERNEL_STACK_TO_K0 |
214 | KERNEL_STACK_TO_K0 |
217 | sub $sp, REGISTER_SPACE |
215 | sub $sp, REGISTER_SPACE |
218 | REGISTERS_STORE $sp |
216 | REGISTERS_STORE $sp |
219 | add $sp, $k0, 0 |
217 | add $sp, $k0, 0 |
220 | 218 | ||
221 | jal cache_error |
219 | jal cache_error |
222 | nop |
220 | nop |
223 | 221 | ||
224 | REGISTERS_LOAD $sp |
222 | REGISTERS_LOAD $sp |
225 | 223 | ||
226 | eret |
224 | eret |
227 | nop |
225 | nop |
228 | 226 | ||
229 | userspace_asm: |
227 | userspace_asm: |
230 | add $sp, $a0, 0 |
228 | add $sp, $a0, 0 |
231 | eret |
229 | eret |
232 | nop |
230 | nop |
233 | 231 | ||
234 | 232 |