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1 | /* |
1 | /* |
2 | * Copyright (C) 2003-2004 Jakub Jermar |
2 | * Copyright (C) 2003-2004 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | #include <arch/interrupt.h> |
29 | #include <arch/interrupt.h> |
30 | #include <arch/types.h> |
30 | #include <arch/types.h> |
31 | #include <arch.h> |
31 | #include <arch.h> |
32 | #include <arch/cp0.h> |
32 | #include <arch/cp0.h> |
33 | #include <time/clock.h> |
33 | #include <time/clock.h> |
34 | #include <panic.h> |
34 | #include <panic.h> |
35 | #include <print.h> |
35 | #include <print.h> |
36 | #include <symtab.h> |
36 | #include <symtab.h> |
37 | #include <arch/drivers/arc.h> |
37 | #include <arch/drivers/arc.h> |
38 | #include <arch/drivers/keyboard.h> |
38 | #include <arch/drivers/keyboard.h> |
39 | 39 | ||
40 | static void print_regdump(struct exception_regdump *pstate) |
40 | static void print_regdump(struct exception_regdump *pstate) |
41 | { |
41 | { |
42 | char *pcsymbol = ""; |
42 | char *pcsymbol = ""; |
43 | char *rasymbol = ""; |
43 | char *rasymbol = ""; |
44 | 44 | ||
45 | char *s = get_symtab_entry(pstate->epc); |
45 | char *s = get_symtab_entry(pstate->epc); |
46 | if (s) |
46 | if (s) |
47 | pcsymbol = s; |
47 | pcsymbol = s; |
48 | s = get_symtab_entry(pstate->ra); |
48 | s = get_symtab_entry(pstate->ra); |
49 | if (s) |
49 | if (s) |
50 | rasymbol = s; |
50 | rasymbol = s; |
51 | 51 | ||
52 | printf("PC: %X(%s) RA: %X(%s)\n",pstate->epc,pcsymbol, |
52 | printf("PC: %X(%s) RA: %X(%s)\n",pstate->epc,pcsymbol, |
53 | pstate->ra,rasymbol); |
53 | pstate->ra,rasymbol); |
54 | } |
54 | } |
55 | 55 | ||
56 | /** Disable interrupts. |
56 | /** Disable interrupts. |
57 | * |
57 | * |
58 | * @return Old interrupt priority level. |
58 | * @return Old interrupt priority level. |
59 | */ |
59 | */ |
60 | ipl_t interrupts_disable(void) |
60 | ipl_t interrupts_disable(void) |
61 | { |
61 | { |
62 | ipl_t ipl = (ipl_t) cp0_status_read(); |
62 | ipl_t ipl = (ipl_t) cp0_status_read(); |
63 | cp0_status_write(ipl & ~cp0_status_ie_enabled_bit); |
63 | cp0_status_write(ipl & ~cp0_status_ie_enabled_bit); |
64 | return ipl; |
64 | return ipl; |
65 | } |
65 | } |
66 | 66 | ||
67 | /** Enable interrupts. |
67 | /** Enable interrupts. |
68 | * |
68 | * |
69 | * @return Old interrupt priority level. |
69 | * @return Old interrupt priority level. |
70 | */ |
70 | */ |
71 | ipl_t interrupts_enable(void) |
71 | ipl_t interrupts_enable(void) |
72 | { |
72 | { |
73 | ipl_t ipl = (ipl_t) cp0_status_read(); |
73 | ipl_t ipl = (ipl_t) cp0_status_read(); |
74 | cp0_status_write(ipl | cp0_status_ie_enabled_bit); |
74 | cp0_status_write(ipl | cp0_status_ie_enabled_bit); |
75 | return ipl; |
75 | return ipl; |
76 | } |
76 | } |
77 | 77 | ||
78 | /** Restore interrupt priority level. |
78 | /** Restore interrupt priority level. |
79 | * |
79 | * |
80 | * @param ipl Saved interrupt priority level. |
80 | * @param ipl Saved interrupt priority level. |
81 | */ |
81 | */ |
82 | void interrupts_restore(ipl_t ipl) |
82 | void interrupts_restore(ipl_t ipl) |
83 | { |
83 | { |
84 | cp0_status_write(cp0_status_read() | (ipl & cp0_status_ie_enabled_bit)); |
84 | cp0_status_write(cp0_status_read() | (ipl & cp0_status_ie_enabled_bit)); |
85 | } |
85 | } |
86 | 86 | ||
87 | /** Read interrupt priority level. |
87 | /** Read interrupt priority level. |
88 | * |
88 | * |
89 | * @return Current interrupt priority level. |
89 | * @return Current interrupt priority level. |
90 | */ |
90 | */ |
91 | ipl_t interrupts_read(void) |
91 | ipl_t interrupts_read(void) |
92 | { |
92 | { |
93 | return cp0_status_read(); |
93 | return cp0_status_read(); |
94 | } |
94 | } |
95 | 95 | ||
96 | void interrupt(struct exception_regdump *pstate) |
96 | void interrupt(struct exception_regdump *pstate) |
97 | { |
97 | { |
98 | __u32 cause; |
98 | __u32 cause; |
99 | int i; |
99 | int i; |
100 | 100 | ||
101 | /* decode interrupt number and process the interrupt */ |
101 | /* decode interrupt number and process the interrupt */ |
102 | cause = (cp0_cause_read() >> 8) &0xff; |
102 | cause = (cp0_cause_read() >> 8) &0xff; |
103 | 103 | ||
104 | for (i = 0; i < 8; i++) { |
104 | for (i = 0; i < 8; i++) { |
105 | if (cause & (1 << i)) { |
105 | if (cause & (1 << i)) { |
106 | switch (i) { |
106 | switch (i) { |
107 | case 0: /* SW0 - Software interrupt 0 */ |
107 | case 0: /* SW0 - Software interrupt 0 */ |
108 | cp0_cause_write(cp0_cause_read() & ~(1 << 8)); /* clear SW0 interrupt */ |
108 | cp0_cause_write(cp0_cause_read() & ~(1 << 8)); /* clear SW0 interrupt */ |
109 | break; |
109 | break; |
110 | case 1: /* SW1 - Software interrupt 1 */ |
110 | case 1: /* SW1 - Software interrupt 1 */ |
111 | cp0_cause_write(cp0_cause_read() & ~(1 << 9)); /* clear SW1 interrupt */ |
111 | cp0_cause_write(cp0_cause_read() & ~(1 << 9)); /* clear SW1 interrupt */ |
112 | break; |
112 | break; |
113 | case 2: /* IRQ0 */ |
113 | case 2: /* IRQ0 */ |
114 | case KEYBOARD_IRQ: |
114 | case KEYBOARD_IRQ: |
115 | keyboard(); |
115 | keyboard(); |
116 | break; |
116 | break; |
117 | case 4: /* IRQ2 */ |
117 | case 4: /* IRQ2 */ |
118 | case 5: /* IRQ3 */ |
118 | case 5: /* IRQ3 */ |
119 | case 6: /* IRQ4 */ |
119 | case 6: /* IRQ4 */ |
120 | default: |
120 | default: |
121 | print_regdump(pstate); |
121 | print_regdump(pstate); |
122 | panic("unhandled interrupt %d\n", i); |
122 | panic("unhandled interrupt %d\n", i); |
123 | break; |
123 | break; |
124 | case TIMER_IRQ: |
124 | case TIMER_IRQ: |
125 | /* clear timer interrupt & set new */ |
125 | /* clear timer interrupt & set new */ |
126 | cp0_compare_write(cp0_count_read() + cp0_compare_value); |
126 | cp0_compare_write(cp0_count_read() + cp0_compare_value); |
127 | clock(); |
127 | clock(); |
- | 128 | keyboard_poll(); |
|
128 | break; |
129 | break; |
129 | } |
130 | } |
130 | } |
131 | } |
131 | } |
132 | } |
132 | 133 | ||
133 | } |
134 | } |
134 | 135 |