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1 | /* |
1 | /* |
2 | * Copyright (C) 2003-2004 Jakub Jermar |
2 | * Copyright (C) 2003-2004 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | #include <arch/interrupt.h> |
29 | #include <arch/interrupt.h> |
30 | #include <arch/types.h> |
30 | #include <arch/types.h> |
31 | #include <arch.h> |
31 | #include <arch.h> |
32 | #include <arch/cp0.h> |
32 | #include <arch/cp0.h> |
33 | #include <time/clock.h> |
33 | #include <time/clock.h> |
34 | #include <panic.h> |
34 | #include <panic.h> |
35 | #include <print.h> |
35 | #include <print.h> |
36 | #include <symtab.h> |
36 | #include <symtab.h> |
37 | #include <arch/drivers/arc.h> |
37 | #include <arch/drivers/arc.h> |
38 | 38 | ||
39 | static void print_regdump(struct exception_regdump *pstate) |
39 | static void print_regdump(struct exception_regdump *pstate) |
40 | { |
40 | { |
41 | char *pcsymbol = ""; |
41 | char *pcsymbol = ""; |
42 | char *rasymbol = ""; |
42 | char *rasymbol = ""; |
43 | 43 | ||
44 | char *s = get_symtab_entry(pstate->epc); |
44 | char *s = get_symtab_entry(pstate->epc); |
45 | if (s) |
45 | if (s) |
46 | pcsymbol = s; |
46 | pcsymbol = s; |
47 | s = get_symtab_entry(pstate->ra); |
47 | s = get_symtab_entry(pstate->ra); |
48 | if (s) |
48 | if (s) |
49 | rasymbol = s; |
49 | rasymbol = s; |
50 | 50 | ||
51 | printf("PC: %X(%s) RA: %X(%s)\n",pstate->epc,pcsymbol, |
51 | printf("PC: %X(%s) RA: %X(%s)\n",pstate->epc,pcsymbol, |
52 | pstate->ra,rasymbol); |
52 | pstate->ra,rasymbol); |
53 | } |
53 | } |
54 | 54 | ||
55 | /** Disable interrupts. |
55 | /** Disable interrupts. |
56 | * |
56 | * |
57 | * @return Old interrupt priority level. |
57 | * @return Old interrupt priority level. |
58 | */ |
58 | */ |
59 | ipl_t interrupts_disable(void) |
59 | ipl_t interrupts_disable(void) |
60 | { |
60 | { |
61 | ipl_t ipl = (ipl_t) cp0_status_read(); |
61 | ipl_t ipl = (ipl_t) cp0_status_read(); |
62 | cp0_status_write(ipl & ~cp0_status_ie_enabled_bit); |
62 | cp0_status_write(ipl & ~cp0_status_ie_enabled_bit); |
63 | return ipl; |
63 | return ipl; |
64 | } |
64 | } |
65 | 65 | ||
66 | /** Enable interrupts. |
66 | /** Enable interrupts. |
67 | * |
67 | * |
68 | * @return Old interrupt priority level. |
68 | * @return Old interrupt priority level. |
69 | */ |
69 | */ |
70 | ipl_t interrupts_enable(void) |
70 | ipl_t interrupts_enable(void) |
71 | { |
71 | { |
72 | ipl_t ipl = (ipl_t) cp0_status_read(); |
72 | ipl_t ipl = (ipl_t) cp0_status_read(); |
73 | cp0_status_write(ipl | cp0_status_ie_enabled_bit); |
73 | cp0_status_write(ipl | cp0_status_ie_enabled_bit); |
74 | return ipl; |
74 | return ipl; |
75 | } |
75 | } |
76 | 76 | ||
77 | /** Restore interrupt priority level. |
77 | /** Restore interrupt priority level. |
78 | * |
78 | * |
79 | * @param ipl Saved interrupt priority level. |
79 | * @param ipl Saved interrupt priority level. |
80 | */ |
80 | */ |
81 | void interrupts_restore(ipl_t ipl) |
81 | void interrupts_restore(ipl_t ipl) |
82 | { |
82 | { |
83 | cp0_status_write(cp0_status_read() | (ipl & cp0_status_ie_enabled_bit)); |
83 | cp0_status_write(cp0_status_read() | (ipl & cp0_status_ie_enabled_bit)); |
84 | } |
84 | } |
85 | 85 | ||
86 | /** Read interrupt priority level. |
86 | /** Read interrupt priority level. |
87 | * |
87 | * |
88 | * @return Current interrupt priority level. |
88 | * @return Current interrupt priority level. |
89 | */ |
89 | */ |
90 | ipl_t interrupts_read(void) |
90 | ipl_t interrupts_read(void) |
91 | { |
91 | { |
92 | return cp0_status_read(); |
92 | return cp0_status_read(); |
93 | } |
93 | } |
94 | 94 | ||
95 | void interrupt(struct exception_regdump *pstate) |
95 | void interrupt(struct exception_regdump *pstate) |
96 | { |
96 | { |
97 | __u32 cause; |
97 | __u32 cause; |
98 | int i; |
98 | int i; |
99 | 99 | ||
100 | /* decode interrupt number and process the interrupt */ |
100 | /* decode interrupt number and process the interrupt */ |
101 | cause = (cp0_cause_read() >> 8) &0xff; |
101 | cause = (cp0_cause_read() >> 8) &0xff; |
102 | 102 | ||
103 | for (i = 0; i < 8; i++) { |
103 | for (i = 0; i < 8; i++) { |
104 | if (cause & (1 << i)) { |
104 | if (cause & (1 << i)) { |
105 | switch (i) { |
105 | switch (i) { |
106 | case 0: /* SW0 - Software interrupt 0 */ |
106 | case 0: /* SW0 - Software interrupt 0 */ |
107 | cp0_cause_write(cp0_cause_read() & ~(1 << 8)); /* clear SW0 interrupt */ |
107 | cp0_cause_write(cp0_cause_read() & ~(1 << 8)); /* clear SW0 interrupt */ |
108 | break; |
108 | break; |
109 | case 1: /* SW1 - Software interrupt 1 */ |
109 | case 1: /* SW1 - Software interrupt 1 */ |
110 | cp0_cause_write(cp0_cause_read() & ~(1 << 9)); /* clear SW1 interrupt */ |
110 | cp0_cause_write(cp0_cause_read() & ~(1 << 9)); /* clear SW1 interrupt */ |
111 | break; |
111 | break; |
112 | case 2: /* IRQ0 */ |
112 | case 2: /* IRQ0 */ |
113 | case 3: /* IRQ1 */ |
113 | case 3: /* IRQ1 */ |
114 | case 4: /* IRQ2 */ |
114 | case 4: /* IRQ2 */ |
115 | case 5: /* IRQ3 */ |
115 | case 5: /* IRQ3 */ |
116 | case 6: /* IRQ4 */ |
116 | case 6: /* IRQ4 */ |
117 | default: |
117 | default: |
118 | print_regdump(pstate); |
118 | print_regdump(pstate); |
119 | panic("unhandled interrupt %d\n", i); |
119 | panic("unhandled interrupt %d\n", i); |
120 | break; |
120 | break; |
121 | case TIMER_INTERRUPT: |
121 | case TIMER_INTERRUPT: |
122 | /* clear timer interrupt & set new */ |
122 | /* clear timer interrupt & set new */ |
123 | cp0_compare_write(cp0_count_read() + cp0_compare_value); |
123 | cp0_compare_write(cp0_count_read() + cp0_compare_value); |
124 | clock(); |
124 | clock(); |
125 | break; |
125 | break; |
126 | } |
126 | } |
127 | } |
127 | } |
128 | } |
128 | } |
129 | 129 | ||
130 | } |
130 | } |
131 | 131 |