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1 | /* |
1 | /* |
2 | * Copyright (C) 2003-2004 Jakub Jermar |
2 | * Copyright (C) 2003-2004 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
- | 29 | /** @addtogroup mips32interrupt mips32 |
|
- | 30 | * @ingroup interrupt |
|
- | 31 | * @{ |
|
- | 32 | */ |
|
- | 33 | /** @file |
|
- | 34 | */ |
|
- | 35 | ||
29 | #include <interrupt.h> |
36 | #include <interrupt.h> |
30 | #include <arch/interrupt.h> |
37 | #include <arch/interrupt.h> |
31 | #include <arch/types.h> |
38 | #include <arch/types.h> |
32 | #include <arch.h> |
39 | #include <arch.h> |
33 | #include <arch/cp0.h> |
40 | #include <arch/cp0.h> |
34 | #include <time/clock.h> |
41 | #include <time/clock.h> |
35 | #include <arch/drivers/arc.h> |
42 | #include <arch/drivers/arc.h> |
36 | 43 | ||
37 | #include <ipc/sysipc.h> |
44 | #include <ipc/sysipc.h> |
38 | 45 | ||
39 | /** Disable interrupts. |
46 | /** Disable interrupts. |
40 | * |
47 | * |
41 | * @return Old interrupt priority level. |
48 | * @return Old interrupt priority level. |
42 | */ |
49 | */ |
43 | ipl_t interrupts_disable(void) |
50 | ipl_t interrupts_disable(void) |
44 | { |
51 | { |
45 | ipl_t ipl = (ipl_t) cp0_status_read(); |
52 | ipl_t ipl = (ipl_t) cp0_status_read(); |
46 | cp0_status_write(ipl & ~cp0_status_ie_enabled_bit); |
53 | cp0_status_write(ipl & ~cp0_status_ie_enabled_bit); |
47 | return ipl; |
54 | return ipl; |
48 | } |
55 | } |
49 | 56 | ||
50 | /** Enable interrupts. |
57 | /** Enable interrupts. |
51 | * |
58 | * |
52 | * @return Old interrupt priority level. |
59 | * @return Old interrupt priority level. |
53 | */ |
60 | */ |
54 | ipl_t interrupts_enable(void) |
61 | ipl_t interrupts_enable(void) |
55 | { |
62 | { |
56 | ipl_t ipl = (ipl_t) cp0_status_read(); |
63 | ipl_t ipl = (ipl_t) cp0_status_read(); |
57 | cp0_status_write(ipl | cp0_status_ie_enabled_bit); |
64 | cp0_status_write(ipl | cp0_status_ie_enabled_bit); |
58 | return ipl; |
65 | return ipl; |
59 | } |
66 | } |
60 | 67 | ||
61 | /** Restore interrupt priority level. |
68 | /** Restore interrupt priority level. |
62 | * |
69 | * |
63 | * @param ipl Saved interrupt priority level. |
70 | * @param ipl Saved interrupt priority level. |
64 | */ |
71 | */ |
65 | void interrupts_restore(ipl_t ipl) |
72 | void interrupts_restore(ipl_t ipl) |
66 | { |
73 | { |
67 | cp0_status_write(cp0_status_read() | (ipl & cp0_status_ie_enabled_bit)); |
74 | cp0_status_write(cp0_status_read() | (ipl & cp0_status_ie_enabled_bit)); |
68 | } |
75 | } |
69 | 76 | ||
70 | /** Read interrupt priority level. |
77 | /** Read interrupt priority level. |
71 | * |
78 | * |
72 | * @return Current interrupt priority level. |
79 | * @return Current interrupt priority level. |
73 | */ |
80 | */ |
74 | ipl_t interrupts_read(void) |
81 | ipl_t interrupts_read(void) |
75 | { |
82 | { |
76 | return cp0_status_read(); |
83 | return cp0_status_read(); |
77 | } |
84 | } |
78 | 85 | ||
79 | /* TODO: This is SMP unsafe!!! */ |
86 | /* TODO: This is SMP unsafe!!! */ |
80 | static unsigned long nextcount; |
87 | static unsigned long nextcount; |
81 | /** Start hardware clock */ |
88 | /** Start hardware clock */ |
82 | static void timer_start(void) |
89 | static void timer_start(void) |
83 | { |
90 | { |
84 | nextcount = cp0_compare_value + cp0_count_read(); |
91 | nextcount = cp0_compare_value + cp0_count_read(); |
85 | cp0_compare_write(nextcount); |
92 | cp0_compare_write(nextcount); |
86 | } |
93 | } |
87 | 94 | ||
88 | static void timer_exception(int n, istate_t *istate) |
95 | static void timer_exception(int n, istate_t *istate) |
89 | { |
96 | { |
90 | unsigned long drift; |
97 | unsigned long drift; |
91 | 98 | ||
92 | drift = cp0_count_read() - nextcount; |
99 | drift = cp0_count_read() - nextcount; |
93 | while (drift > cp0_compare_value) { |
100 | while (drift > cp0_compare_value) { |
94 | drift -= cp0_compare_value; |
101 | drift -= cp0_compare_value; |
95 | CPU->missed_clock_ticks++; |
102 | CPU->missed_clock_ticks++; |
96 | } |
103 | } |
97 | nextcount = cp0_count_read() + cp0_compare_value - drift; |
104 | nextcount = cp0_count_read() + cp0_compare_value - drift; |
98 | cp0_compare_write(nextcount); |
105 | cp0_compare_write(nextcount); |
99 | clock(); |
106 | clock(); |
100 | } |
107 | } |
101 | 108 | ||
102 | static void swint0(int n, istate_t *istate) |
109 | static void swint0(int n, istate_t *istate) |
103 | { |
110 | { |
104 | cp0_cause_write(cp0_cause_read() & ~(1 << 8)); /* clear SW0 interrupt */ |
111 | cp0_cause_write(cp0_cause_read() & ~(1 << 8)); /* clear SW0 interrupt */ |
105 | ipc_irq_send_notif(0); |
112 | ipc_irq_send_notif(0); |
106 | } |
113 | } |
107 | 114 | ||
108 | static void swint1(int n, istate_t *istate) |
115 | static void swint1(int n, istate_t *istate) |
109 | { |
116 | { |
110 | cp0_cause_write(cp0_cause_read() & ~(1 << 9)); /* clear SW1 interrupt */ |
117 | cp0_cause_write(cp0_cause_read() & ~(1 << 9)); /* clear SW1 interrupt */ |
111 | ipc_irq_send_notif(1); |
118 | ipc_irq_send_notif(1); |
112 | } |
119 | } |
113 | 120 | ||
114 | /* Initialize basic tables for exception dispatching */ |
121 | /* Initialize basic tables for exception dispatching */ |
115 | void interrupt_init(void) |
122 | void interrupt_init(void) |
116 | { |
123 | { |
117 | int_register(TIMER_IRQ, "timer", timer_exception); |
124 | int_register(TIMER_IRQ, "timer", timer_exception); |
118 | int_register(0, "swint0", swint0); |
125 | int_register(0, "swint0", swint0); |
119 | int_register(1, "swint1", swint1); |
126 | int_register(1, "swint1", swint1); |
120 | timer_start(); |
127 | timer_start(); |
121 | } |
128 | } |
122 | 129 | ||
123 | static void ipc_int(int n, istate_t *istate) |
130 | static void ipc_int(int n, istate_t *istate) |
124 | { |
131 | { |
125 | ipc_irq_send_notif(n-INT_OFFSET); |
132 | ipc_irq_send_notif(n-INT_OFFSET); |
126 | } |
133 | } |
127 | 134 | ||
128 | /* Reregister irq to be IPC-ready */ |
135 | /* Reregister irq to be IPC-ready */ |
129 | void irq_ipc_bind_arch(__native irq) |
136 | void irq_ipc_bind_arch(__native irq) |
130 | { |
137 | { |
131 | /* Do not allow to redefine timer */ |
138 | /* Do not allow to redefine timer */ |
132 | /* Swint0, Swint1 are already handled */ |
139 | /* Swint0, Swint1 are already handled */ |
133 | if (irq == TIMER_IRQ || irq < 2) |
140 | if (irq == TIMER_IRQ || irq < 2) |
134 | return; |
141 | return; |
135 | int_register(irq, "ipc_int", ipc_int); |
142 | int_register(irq, "ipc_int", ipc_int); |
136 | } |
143 | } |
- | 144 | ||
- | 145 | /** @} |
|
- | 146 | */ |
|
- | 147 | ||
137 | 148 |