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1 | /* |
1 | /* |
2 | * Copyright (C) 2003-2004 Jakub Jermar |
2 | * Copyright (C) 2003-2004 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | #include <interrupt.h> |
29 | #include <interrupt.h> |
30 | #include <arch/interrupt.h> |
30 | #include <arch/interrupt.h> |
31 | #include <arch/types.h> |
31 | #include <arch/types.h> |
32 | #include <arch.h> |
32 | #include <arch.h> |
33 | #include <arch/cp0.h> |
33 | #include <arch/cp0.h> |
34 | #include <time/clock.h> |
34 | #include <time/clock.h> |
35 | #include <arch/drivers/arc.h> |
35 | #include <arch/drivers/arc.h> |
36 | 36 | ||
37 | #include <ipc/sysipc.h> |
37 | #include <ipc/sysipc.h> |
38 | 38 | ||
39 | /** Disable interrupts. |
39 | /** Disable interrupts. |
40 | * |
40 | * |
41 | * @return Old interrupt priority level. |
41 | * @return Old interrupt priority level. |
42 | */ |
42 | */ |
43 | ipl_t interrupts_disable(void) |
43 | ipl_t interrupts_disable(void) |
44 | { |
44 | { |
45 | ipl_t ipl = (ipl_t) cp0_status_read(); |
45 | ipl_t ipl = (ipl_t) cp0_status_read(); |
46 | cp0_status_write(ipl & ~cp0_status_ie_enabled_bit); |
46 | cp0_status_write(ipl & ~cp0_status_ie_enabled_bit); |
47 | return ipl; |
47 | return ipl; |
48 | } |
48 | } |
49 | 49 | ||
50 | /** Enable interrupts. |
50 | /** Enable interrupts. |
51 | * |
51 | * |
52 | * @return Old interrupt priority level. |
52 | * @return Old interrupt priority level. |
53 | */ |
53 | */ |
54 | ipl_t interrupts_enable(void) |
54 | ipl_t interrupts_enable(void) |
55 | { |
55 | { |
56 | ipl_t ipl = (ipl_t) cp0_status_read(); |
56 | ipl_t ipl = (ipl_t) cp0_status_read(); |
57 | cp0_status_write(ipl | cp0_status_ie_enabled_bit); |
57 | cp0_status_write(ipl | cp0_status_ie_enabled_bit); |
58 | return ipl; |
58 | return ipl; |
59 | } |
59 | } |
60 | 60 | ||
61 | /** Restore interrupt priority level. |
61 | /** Restore interrupt priority level. |
62 | * |
62 | * |
63 | * @param ipl Saved interrupt priority level. |
63 | * @param ipl Saved interrupt priority level. |
64 | */ |
64 | */ |
65 | void interrupts_restore(ipl_t ipl) |
65 | void interrupts_restore(ipl_t ipl) |
66 | { |
66 | { |
67 | cp0_status_write(cp0_status_read() | (ipl & cp0_status_ie_enabled_bit)); |
67 | cp0_status_write(cp0_status_read() | (ipl & cp0_status_ie_enabled_bit)); |
68 | } |
68 | } |
69 | 69 | ||
70 | /** Read interrupt priority level. |
70 | /** Read interrupt priority level. |
71 | * |
71 | * |
72 | * @return Current interrupt priority level. |
72 | * @return Current interrupt priority level. |
73 | */ |
73 | */ |
74 | ipl_t interrupts_read(void) |
74 | ipl_t interrupts_read(void) |
75 | { |
75 | { |
76 | return cp0_status_read(); |
76 | return cp0_status_read(); |
77 | } |
77 | } |
78 | 78 | ||
79 | static void timer_exception(int n, istate_t *istate) |
79 | static void timer_exception(int n, istate_t *istate) |
80 | { |
80 | { |
81 | cp0_compare_write(cp0_count_read() + cp0_compare_value); |
81 | cp0_compare_write(cp0_count_read() + cp0_compare_value); |
82 | clock(); |
82 | clock(); |
83 | } |
83 | } |
84 | 84 | ||
85 | static void swint0(int n, istate_t *istate) |
85 | static void swint0(int n, istate_t *istate) |
86 | { |
86 | { |
87 | cp0_cause_write(cp0_cause_read() & ~(1 << 8)); /* clear SW0 interrupt */ |
87 | cp0_cause_write(cp0_cause_read() & ~(1 << 8)); /* clear SW0 interrupt */ |
88 | ipc_irq_send_notif(0); |
88 | ipc_irq_send_notif(0); |
89 | } |
89 | } |
90 | 90 | ||
91 | static void swint1(int n, istate_t *istate) |
91 | static void swint1(int n, istate_t *istate) |
92 | { |
92 | { |
93 | cp0_cause_write(cp0_cause_read() & ~(1 << 9)); /* clear SW1 interrupt */ |
93 | cp0_cause_write(cp0_cause_read() & ~(1 << 9)); /* clear SW1 interrupt */ |
94 | ipc_irq_send_notif(1); |
94 | ipc_irq_send_notif(1); |
95 | } |
95 | } |
96 | 96 | ||
97 | /* Initialize basic tables for exception dispatching */ |
97 | /* Initialize basic tables for exception dispatching */ |
98 | void interrupt_init(void) |
98 | void interrupt_init(void) |
99 | { |
99 | { |
100 | int_register(TIMER_IRQ, "timer", timer_exception); |
100 | int_register(TIMER_IRQ, "timer", timer_exception); |
101 | int_register(0, "swint0", swint0); |
101 | int_register(0, "swint0", swint0); |
102 | int_register(1, "swint1", swint1); |
102 | int_register(1, "swint1", swint1); |
103 | } |
103 | } |
104 | 104 | ||
105 | #include <print.h> |
- | |
106 | static void ipc_int(int n, istate_t *istate) |
105 | static void ipc_int(int n, istate_t *istate) |
107 | { |
106 | { |
108 | ipc_irq_send_notif(n-INT_OFFSET); |
107 | ipc_irq_send_notif(n-INT_OFFSET); |
109 | } |
108 | } |
110 | 109 | ||
111 | /* Reregister irq to be IPC-ready */ |
110 | /* Reregister irq to be IPC-ready */ |
112 | void irq_ipc_bind_arch(__native irq) |
111 | void irq_ipc_bind_arch(__native irq) |
113 | { |
112 | { |
114 | /* Do not allow to redefine timer */ |
113 | /* Do not allow to redefine timer */ |
115 | /* Swint0, Swint1 are already handled */ |
114 | /* Swint0, Swint1 are already handled */ |
116 | if (irq == TIMER_IRQ || irq < 2) |
115 | if (irq == TIMER_IRQ || irq < 2) |
117 | return; |
116 | return; |
118 | int_register(irq, "ipc_int", ipc_int); |
117 | int_register(irq, "ipc_int", ipc_int); |
119 | } |
118 | } |
120 | 119 |