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1 | /* |
1 | /* |
2 | * Copyright (C) 2003-2004 Jakub Jermar |
2 | * Copyright (C) 2003-2004 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | #include <arch/exception.h> |
29 | #include <arch/exception.h> |
30 | #include <arch/interrupt.h> |
30 | #include <arch/interrupt.h> |
31 | #include <panic.h> |
31 | #include <panic.h> |
32 | #include <arch/cp0.h> |
32 | #include <arch/cp0.h> |
33 | #include <arch/types.h> |
33 | #include <arch/types.h> |
34 | #include <arch.h> |
34 | #include <arch.h> |
35 | #include <debug.h> |
35 | #include <debug.h> |
36 | 36 | ||
37 | void exception(struct exception_regdump *pstate) |
37 | void exception(struct exception_regdump *pstate) |
38 | { |
38 | { |
39 | int excno; |
39 | int excno; |
40 | __u32 epc_shift = 0; |
40 | __u32 epc_shift = 0; |
41 | 41 | ||
42 | ASSERT(CPU != NULL); |
42 | ASSERT(CPU != NULL); |
43 | 43 | ||
44 | /* |
44 | /* |
45 | * NOTE ON OPERATION ORDERING |
45 | * NOTE ON OPERATION ORDERING |
46 | * |
46 | * |
47 | * On entry, cpu_priority_high() must be called before |
47 | * On entry, cpu_priority_high() must be called before |
48 | * exception bit is cleared. |
48 | * exception bit is cleared. |
49 | */ |
49 | */ |
50 | 50 | ||
51 | cpu_priority_high(); |
51 | cpu_priority_high(); |
52 | cp0_status_write(cp0_status_read() & ~ (cp0_status_exl_exception_bit | |
52 | cp0_status_write(cp0_status_read() & ~ (cp0_status_exl_exception_bit | |
53 | cp0_status_um_bit)); |
53 | cp0_status_um_bit)); |
- | 54 | ||
54 | /* Save pstate so that the threads can access it */ |
55 | /* Save pstate so that the threads can access it */ |
- | 56 | /* If THREAD->pstate is set, this is nested exception, |
|
- | 57 | * do not rewrite it |
|
- | 58 | */ |
|
55 | if (THREAD) |
59 | if (THREAD && !THREAD->pstate) |
56 | THREAD->pstate = pstate; |
60 | THREAD->pstate = pstate; |
57 | 61 | ||
58 | /* decode exception number and process the exception */ |
62 | /* decode exception number and process the exception */ |
59 | switch (excno = (cp0_cause_read() >> 2) & 0x1f) { |
63 | switch (excno = (cp0_cause_read() >> 2) & 0x1f) { |
60 | case EXC_Int: |
64 | case EXC_Int: |
61 | interrupt(); |
65 | interrupt(); |
62 | break; |
66 | break; |
63 | case EXC_TLBL: |
67 | case EXC_TLBL: |
64 | case EXC_TLBS: |
68 | case EXC_TLBS: |
65 | tlb_invalid(pstate); |
69 | tlb_invalid(pstate); |
66 | break; |
70 | break; |
- | 71 | case EXC_CpU: |
|
- | 72 | #ifdef FPU_LAZY |
|
- | 73 | scheduler_fpu_lazy_request(); |
|
- | 74 | #else |
|
- | 75 | panic("unhandled Coprocessor Unusable Exception\n"); |
|
- | 76 | #endif |
|
- | 77 | break; |
|
67 | case EXC_Mod: |
78 | case EXC_Mod: |
68 | panic("unhandled TLB Modification Exception\n"); |
79 | panic("unhandled TLB Modification Exception\n"); |
69 | break; |
80 | break; |
70 | case EXC_AdEL: |
81 | case EXC_AdEL: |
71 | panic("unhandled Address Error Exception - load or instruction fetch\n"); |
82 | panic("unhandled Address Error Exception - load or instruction fetch\n"); |
72 | break; |
83 | break; |
73 | case EXC_AdES: |
84 | case EXC_AdES: |
74 | panic("unhandled Address Error Exception - store\n"); |
85 | panic("unhandled Address Error Exception - store\n"); |
75 | break; |
86 | break; |
76 | case EXC_IBE: |
87 | case EXC_IBE: |
77 | panic("unhandled Bus Error Exception - fetch instruction\n"); |
88 | panic("unhandled Bus Error Exception - fetch instruction\n"); |
78 | break; |
89 | break; |
79 | case EXC_DBE: |
90 | case EXC_DBE: |
80 | panic("unhandled Bus Error Exception - data reference: load or store\n"); |
91 | panic("unhandled Bus Error Exception - data reference: load or store\n"); |
81 | break; |
92 | break; |
82 | case EXC_Bp: |
93 | case EXC_Bp: |
83 | /* it is necessary to not re-execute BREAK instruction after returning from Exception handler |
94 | /* it is necessary to not re-execute BREAK instruction after returning from Exception handler |
84 | (see page 138 in R4000 Manual for more information) */ |
95 | (see page 138 in R4000 Manual for more information) */ |
85 | epc_shift = 4; |
96 | epc_shift = 4; |
86 | break; |
97 | break; |
87 | case EXC_RI: |
98 | case EXC_RI: |
88 | panic("unhandled Reserved Instruction Exception\n"); |
99 | panic("unhandled Reserved Instruction Exception\n"); |
89 | break; |
100 | break; |
90 | case EXC_CpU: |
- | |
91 | #ifdef FPU_LAZY |
- | |
92 | scheduler_fpu_lazy_request(); |
- | |
93 | #else |
- | |
94 | panic("unhandled Coprocessor Unusable Exception\n"); |
- | |
95 | #endif |
- | |
96 | break; |
- | |
97 | case EXC_Ov: |
101 | case EXC_Ov: |
98 | panic("unhandled Arithmetic Overflow Exception\n"); |
102 | panic("unhandled Arithmetic Overflow Exception\n"); |
99 | break; |
103 | break; |
100 | case EXC_Tr: |
104 | case EXC_Tr: |
101 | panic("unhandled Trap Exception\n"); |
105 | panic("unhandled Trap Exception\n"); |
102 | break; |
106 | break; |
103 | case EXC_VCEI: |
107 | case EXC_VCEI: |
104 | panic("unhandled Virtual Coherency Exception - instruction\n"); |
108 | panic("unhandled Virtual Coherency Exception - instruction\n"); |
105 | break; |
109 | break; |
106 | case EXC_FPE: |
110 | case EXC_FPE: |
107 | panic("unhandled Floating-Point Exception\n"); |
111 | panic("unhandled Floating-Point Exception\n"); |
108 | break; |
112 | break; |
109 | case EXC_WATCH: |
113 | case EXC_WATCH: |
110 | panic("unhandled reference to WatchHi/WatchLo address\n"); |
114 | panic("unhandled reference to WatchHi/WatchLo address\n"); |
111 | break; |
115 | break; |
112 | case EXC_VCED: |
116 | case EXC_VCED: |
113 | panic("unhandled Virtual Coherency Exception - data\n"); |
117 | panic("unhandled Virtual Coherency Exception - data\n"); |
114 | break; |
118 | break; |
115 | default: |
119 | default: |
116 | panic("unhandled exception %d\n", excno); |
120 | panic("unhandled exception %d\n", excno); |
117 | } |
121 | } |
118 | 122 | ||
119 | pstate->epc += epc_shift; |
123 | pstate->epc += epc_shift; |
- | 124 | /* Set to NULL, so that we can still support nested |
|
- | 125 | * exceptions |
|
120 | /* Probable not needed, but just for sure that nobody |
126 | * TODO: We should probably set EXL bit before this command, |
121 | * will continue accessing it */ |
127 | * nesting. On the other hand, if some exception occurs between |
- | 128 | * here and ERET, it won't set anything on the pstate anyway. |
|
- | 129 | */ |
|
122 | if (THREAD) |
130 | if (THREAD) |
123 | THREAD->pstate = NULL; |
131 | THREAD->pstate = NULL; |
124 | } |
132 | } |
125 | 133 |