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1 | /* |
1 | /* |
2 | * Copyright (C) 2005 Ondrej Palkovsky |
2 | * Copyright (C) 2005 Ondrej Palkovsky |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | #include <interrupt.h> |
29 | #include <interrupt.h> |
30 | #include <console/chardev.h> |
30 | #include <console/chardev.h> |
31 | #include <arch/drivers/msim.h> |
31 | #include <arch/drivers/msim.h> |
32 | #include <arch/cp0.h> |
32 | #include <arch/cp0.h> |
33 | #include <console/console.h> |
33 | #include <console/console.h> |
34 | 34 | ||
35 | static chardev_t console; |
35 | static chardev_t console; |
36 | 36 | ||
37 | static void msim_write(chardev_t *dev, const char ch); |
37 | static void msim_write(chardev_t *dev, const char ch); |
38 | static void msim_enable(chardev_t *dev); |
38 | static void msim_enable(chardev_t *dev); |
39 | static void msim_disable(chardev_t *dev); |
39 | static void msim_disable(chardev_t *dev); |
40 | static char msim_do_read(chardev_t *dev); |
40 | static char msim_do_read(chardev_t *dev); |
41 | 41 | ||
42 | static chardev_operations_t msim_ops = { |
42 | static chardev_operations_t msim_ops = { |
43 | .resume = msim_enable, |
43 | .resume = msim_enable, |
44 | .suspend = msim_disable, |
44 | .suspend = msim_disable, |
45 | .write = msim_write, |
45 | .write = msim_write, |
46 | .read = msim_do_read, |
46 | .read = msim_do_read, |
47 | }; |
47 | }; |
48 | 48 | ||
49 | /** Putchar that works with MSIM & gxemul */ |
49 | /** Putchar that works with MSIM & gxemul */ |
50 | void msim_write(chardev_t *dev, const char ch) |
50 | void msim_write(chardev_t *dev, const char ch) |
51 | { |
51 | { |
52 | *((char *) MSIM_VIDEORAM) = ch; |
52 | *((char *) MSIM_VIDEORAM) = ch; |
53 | } |
53 | } |
54 | 54 | ||
55 | /* Called from getc(). */ |
55 | /* Called from getc(). */ |
56 | void msim_enable(chardev_t *dev) |
56 | void msim_enable(chardev_t *dev) |
57 | { |
57 | { |
58 | cp0_unmask_int(MSIM_KBD_IRQ); |
58 | cp0_unmask_int(MSIM_KBD_IRQ); |
59 | } |
59 | } |
60 | 60 | ||
61 | /* Called from getc(). */ |
61 | /* Called from getc(). */ |
62 | void msim_disable(chardev_t *dev) |
62 | void msim_disable(chardev_t *dev) |
63 | { |
63 | { |
64 | cp0_mask_int(MSIM_KBD_IRQ); |
64 | cp0_mask_int(MSIM_KBD_IRQ); |
65 | } |
65 | } |
66 | 66 | ||
67 | #include <print.h> |
67 | #include <print.h> |
68 | /** Read character using polling, assume interrupts disabled */ |
68 | /** Read character using polling, assume interrupts disabled */ |
69 | static char msim_do_read(chardev_t *dev) |
69 | static char msim_do_read(chardev_t *dev) |
70 | { |
70 | { |
71 | char ch; |
71 | char ch; |
72 | 72 | ||
73 | while (1) { |
73 | while (1) { |
74 | ch = *((volatile char *) MSIM_KBD_ADDRESS); |
74 | ch = *((volatile char *) MSIM_KBD_ADDRESS); |
75 | if (ch) { |
75 | if (ch) { |
76 | if (ch == '\r') |
76 | if (ch == '\r') |
77 | return '\n'; |
77 | return '\n'; |
78 | if (ch == 0x7f) |
78 | if (ch == 0x7f) |
79 | return '\b'; |
79 | return '\b'; |
80 | return ch; |
80 | return ch; |
81 | } |
81 | } |
82 | } |
82 | } |
83 | } |
83 | } |
84 | 84 | ||
85 | /** Process keyboard interrupt. */ |
85 | /** Process keyboard interrupt. */ |
86 | static void msim_interrupt(int n, void *stack) |
86 | static void msim_interrupt(int n, istate_t *istate) |
87 | { |
87 | { |
88 | char ch = 0; |
88 | char ch = 0; |
89 | 89 | ||
90 | ch = *((char *) MSIM_KBD_ADDRESS); |
90 | ch = *((char *) MSIM_KBD_ADDRESS); |
91 | if (ch =='\r') |
91 | if (ch =='\r') |
92 | ch = '\n'; |
92 | ch = '\n'; |
93 | if (ch == 0x7f) |
93 | if (ch == 0x7f) |
94 | ch = '\b'; |
94 | ch = '\b'; |
95 | chardev_push_character(&console, ch); |
95 | chardev_push_character(&console, ch); |
96 | } |
96 | } |
97 | 97 | ||
98 | 98 | ||
99 | /* Return console object representing msim console */ |
99 | /* Return console object representing msim console */ |
100 | void msim_console(void) |
100 | void msim_console(void) |
101 | { |
101 | { |
102 | chardev_initialize("msim_console", &console, &msim_ops); |
102 | chardev_initialize("msim_console", &console, &msim_ops); |
103 | 103 | ||
104 | int_register(MSIM_KBD_IRQ, "msim_kbd", msim_interrupt); |
104 | int_register(MSIM_KBD_IRQ, "msim_kbd", msim_interrupt); |
105 | 105 | ||
106 | cp0_unmask_int(MSIM_KBD_IRQ); |
106 | cp0_unmask_int(MSIM_KBD_IRQ); |
107 | 107 | ||
108 | stdin = &console; |
108 | stdin = &console; |
109 | stdout = &console; |
109 | stdout = &console; |
110 | } |
110 | } |
111 | 111 |