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1 | /* |
1 | /* |
2 | * Copyright (C) 2005 Jakub Jermar |
2 | * Copyright (C) 2005 Jakub Jermar |
3 | * Copyright (C) 2005 Jakub Vana |
3 | * Copyright (C) 2005 Jakub Vana |
4 | * All rights reserved. |
4 | * All rights reserved. |
5 | * |
5 | * |
6 | * Redistribution and use in source and binary forms, with or without |
6 | * Redistribution and use in source and binary forms, with or without |
7 | * modification, are permitted provided that the following conditions |
7 | * modification, are permitted provided that the following conditions |
8 | * are met: |
8 | * are met: |
9 | * |
9 | * |
10 | * - Redistributions of source code must retain the above copyright |
10 | * - Redistributions of source code must retain the above copyright |
11 | * notice, this list of conditions and the following disclaimer. |
11 | * notice, this list of conditions and the following disclaimer. |
12 | * - Redistributions in binary form must reproduce the above copyright |
12 | * - Redistributions in binary form must reproduce the above copyright |
13 | * notice, this list of conditions and the following disclaimer in the |
13 | * notice, this list of conditions and the following disclaimer in the |
14 | * documentation and/or other materials provided with the distribution. |
14 | * documentation and/or other materials provided with the distribution. |
15 | * - The name of the author may not be used to endorse or promote products |
15 | * - The name of the author may not be used to endorse or promote products |
16 | * derived from this software without specific prior written permission. |
16 | * derived from this software without specific prior written permission. |
17 | * |
17 | * |
18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
21 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
23 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
27 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
28 | * |
28 | * |
29 | */ |
29 | */ |
30 | 30 | ||
31 | #include <arch/interrupt.h> |
31 | #include <arch/interrupt.h> |
32 | #include <panic.h> |
32 | #include <panic.h> |
33 | #include <print.h> |
33 | #include <print.h> |
34 | #include <console/console.h> |
34 | #include <console/console.h> |
35 | #include <arch/types.h> |
35 | #include <arch/types.h> |
36 | #include <arch/asm.h> |
36 | #include <arch/asm.h> |
37 | #include <arch/barrier.h> |
37 | #include <arch/barrier.h> |
38 | #include <arch/register.h> |
38 | #include <arch/register.h> |
39 | #include <arch/drivers/it.h> |
39 | #include <arch/drivers/it.h> |
40 | #include <arch.h> |
40 | #include <arch.h> |
41 | #include <symtab.h> |
41 | #include <symtab.h> |
42 | #include <debug.h> |
42 | #include <debug.h> |
43 | #include <syscall/syscall.h> |
43 | #include <syscall/syscall.h> |
44 | #include <print.h> |
44 | #include <print.h> |
45 | #include <proc/scheduler.h> |
45 | #include <proc/scheduler.h> |
46 | 46 | ||
47 | #define VECTORS_64_BUNDLE 20 |
47 | #define VECTORS_64_BUNDLE 20 |
48 | #define VECTORS_16_BUNDLE 48 |
48 | #define VECTORS_16_BUNDLE 48 |
49 | #define VECTORS_16_BUNDLE_START 0x5000 |
49 | #define VECTORS_16_BUNDLE_START 0x5000 |
50 | #define VECTOR_MAX 0x7f00 |
50 | #define VECTOR_MAX 0x7f00 |
51 | 51 | ||
52 | #define BUNDLE_SIZE 16 |
52 | #define BUNDLE_SIZE 16 |
53 | 53 | ||
54 | char *vector_names_64_bundle[VECTORS_64_BUNDLE] = { |
54 | char *vector_names_64_bundle[VECTORS_64_BUNDLE] = { |
55 | "VHPT Translation vector", |
55 | "VHPT Translation vector", |
56 | "Instruction TLB vector", |
56 | "Instruction TLB vector", |
57 | "Data TLB vector", |
57 | "Data TLB vector", |
58 | "Alternate Instruction TLB vector", |
58 | "Alternate Instruction TLB vector", |
59 | "Alternate Data TLB vector", |
59 | "Alternate Data TLB vector", |
60 | "Data Nested TLB vector", |
60 | "Data Nested TLB vector", |
61 | "Instruction Key Miss vector", |
61 | "Instruction Key Miss vector", |
62 | "Data Key Miss vector", |
62 | "Data Key Miss vector", |
63 | "Dirty-Bit vector", |
63 | "Dirty-Bit vector", |
64 | "Instruction Access-Bit vector", |
64 | "Instruction Access-Bit vector", |
65 | "Data Access-Bit vector" |
65 | "Data Access-Bit vector" |
66 | "Break Instruction vector", |
66 | "Break Instruction vector", |
67 | "External Interrupt vector" |
67 | "External Interrupt vector" |
68 | "Reserved", |
68 | "Reserved", |
69 | "Reserved", |
69 | "Reserved", |
70 | "Reserved", |
70 | "Reserved", |
71 | "Reserved", |
71 | "Reserved", |
72 | "Reserved", |
72 | "Reserved", |
73 | "Reserved", |
73 | "Reserved", |
74 | "Reserved" |
74 | "Reserved" |
75 | }; |
75 | }; |
76 | 76 | ||
77 | char *vector_names_16_bundle[VECTORS_16_BUNDLE] = { |
77 | char *vector_names_16_bundle[VECTORS_16_BUNDLE] = { |
78 | "Page Not Present vector", |
78 | "Page Not Present vector", |
79 | "Key Permission vector", |
79 | "Key Permission vector", |
80 | "Instruction Access rights vector", |
80 | "Instruction Access rights vector", |
81 | "Data Access Rights vector", |
81 | "Data Access Rights vector", |
82 | "General Exception vector", |
82 | "General Exception vector", |
83 | "Disabled FP-Register vector", |
83 | "Disabled FP-Register vector", |
84 | "NaT Consumption vector", |
84 | "NaT Consumption vector", |
85 | "Speculation vector", |
85 | "Speculation vector", |
86 | "Reserved", |
86 | "Reserved", |
87 | "Debug vector", |
87 | "Debug vector", |
88 | "Unaligned Reference vector", |
88 | "Unaligned Reference vector", |
89 | "Unsupported Data Reference vector", |
89 | "Unsupported Data Reference vector", |
90 | "Floating-point Fault vector", |
90 | "Floating-point Fault vector", |
91 | "Floating-point Trap vector", |
91 | "Floating-point Trap vector", |
92 | "Lower-Privilege Transfer Trap vector", |
92 | "Lower-Privilege Transfer Trap vector", |
93 | "Taken Branch Trap vector", |
93 | "Taken Branch Trap vector", |
94 | "Single STep Trap vector", |
94 | "Single STep Trap vector", |
95 | "Reserved", |
95 | "Reserved", |
96 | "Reserved", |
96 | "Reserved", |
97 | "Reserved", |
97 | "Reserved", |
98 | "Reserved", |
98 | "Reserved", |
99 | "Reserved", |
99 | "Reserved", |
100 | "Reserved", |
100 | "Reserved", |
101 | "Reserved", |
101 | "Reserved", |
102 | "Reserved", |
102 | "Reserved", |
103 | "IA-32 Exception vector", |
103 | "IA-32 Exception vector", |
104 | "IA-32 Intercept vector", |
104 | "IA-32 Intercept vector", |
105 | "IA-32 Interrupt vector", |
105 | "IA-32 Interrupt vector", |
106 | "Reserved", |
106 | "Reserved", |
107 | "Reserved", |
107 | "Reserved", |
108 | "Reserved" |
108 | "Reserved" |
109 | }; |
109 | }; |
110 | 110 | ||
111 | static char *vector_to_string(__u16 vector); |
111 | static char *vector_to_string(__u16 vector); |
112 | static void dump_interrupted_context(istate_t *istate); |
112 | static void dump_interrupted_context(istate_t *istate); |
113 | 113 | ||
114 | char *vector_to_string(__u16 vector) |
114 | char *vector_to_string(__u16 vector) |
115 | { |
115 | { |
116 | ASSERT(vector <= VECTOR_MAX); |
116 | ASSERT(vector <= VECTOR_MAX); |
117 | 117 | ||
118 | if (vector >= VECTORS_16_BUNDLE_START) |
118 | if (vector >= VECTORS_16_BUNDLE_START) |
119 | return vector_names_16_bundle[(vector-VECTORS_16_BUNDLE_START)/(16*BUNDLE_SIZE)]; |
119 | return vector_names_16_bundle[(vector-VECTORS_16_BUNDLE_START)/(16*BUNDLE_SIZE)]; |
120 | else |
120 | else |
121 | return vector_names_64_bundle[vector/(64*BUNDLE_SIZE)]; |
121 | return vector_names_64_bundle[vector/(64*BUNDLE_SIZE)]; |
122 | } |
122 | } |
123 | 123 | ||
124 | void dump_interrupted_context(istate_t *istate) |
124 | void dump_interrupted_context(istate_t *istate) |
125 | { |
125 | { |
126 | char *ifa, *iipa, *iip; |
126 | char *ifa, *iipa, *iip; |
127 | 127 | ||
128 | ifa = get_symtab_entry(istate->cr_ifa); |
128 | ifa = get_symtab_entry(istate->cr_ifa); |
129 | iipa = get_symtab_entry(istate->cr_iipa); |
129 | iipa = get_symtab_entry(istate->cr_iipa); |
130 | iip = get_symtab_entry(istate->cr_iip); |
130 | iip = get_symtab_entry(istate->cr_iip); |
131 | 131 | ||
132 | putchar('\n'); |
132 | putchar('\n'); |
133 | printf("Interrupted context dump:\n"); |
133 | printf("Interrupted context dump:\n"); |
134 | printf("ar.bsp=%P\tar.bspstore=%P\n", istate->ar_bsp, istate->ar_bspstore); |
134 | printf("ar.bsp=%P\tar.bspstore=%P\n", istate->ar_bsp, istate->ar_bspstore); |
135 | printf("ar.rnat=%Q\tar.rsc=%Q\n", istate->ar_rnat, istate->ar_rsc); |
135 | printf("ar.rnat=%Q\tar.rsc=%Q\n", istate->ar_rnat, istate->ar_rsc); |
136 | printf("ar.ifs=%Q\tar.pfs=%Q\n", istate->ar_ifs, istate->ar_pfs); |
136 | printf("ar.ifs=%Q\tar.pfs=%Q\n", istate->ar_ifs, istate->ar_pfs); |
137 | printf("cr.isr=%Q\tcr.ipsr=%Q\t\n", istate->cr_isr.value, istate->cr_ipsr); |
137 | printf("cr.isr=%Q\tcr.ipsr=%Q\t\n", istate->cr_isr.value, istate->cr_ipsr); |
138 | 138 | ||
139 | printf("cr.iip=%Q, #%d\t(%s)\n", istate->cr_iip, istate->cr_isr.ei ,iip ? iip : "?"); |
139 | printf("cr.iip=%Q, #%d\t(%s)\n", istate->cr_iip, istate->cr_isr.ei ,iip ? iip : "?"); |
140 | printf("cr.iipa=%Q\t(%s)\n", istate->cr_iipa, iipa ? iipa : "?"); |
140 | printf("cr.iipa=%Q\t(%s)\n", istate->cr_iipa, iipa ? iipa : "?"); |
141 | printf("cr.ifa=%Q\t(%s)\n", istate->cr_ifa, ifa ? ifa : "?"); |
141 | printf("cr.ifa=%Q\t(%s)\n", istate->cr_ifa, ifa ? ifa : "?"); |
142 | } |
142 | } |
143 | 143 | ||
144 | void general_exception(__u64 vector, istate_t *istate) |
144 | void general_exception(__u64 vector, istate_t *istate) |
145 | { |
145 | { |
146 | char *desc = ""; |
146 | char *desc = ""; |
147 | 147 | ||
148 | dump_interrupted_context(istate); |
148 | dump_interrupted_context(istate); |
149 | 149 | ||
150 | switch (istate->cr_isr.ge_code) { |
150 | switch (istate->cr_isr.ge_code) { |
151 | case GE_ILLEGALOP: |
151 | case GE_ILLEGALOP: |
152 | desc = "Illegal Operation fault"; |
152 | desc = "Illegal Operation fault"; |
153 | break; |
153 | break; |
154 | case GE_PRIVOP: |
154 | case GE_PRIVOP: |
155 | desc = "Privileged Operation fault"; |
155 | desc = "Privileged Operation fault"; |
156 | break; |
156 | break; |
157 | case GE_PRIVREG: |
157 | case GE_PRIVREG: |
158 | desc = "Privileged Register fault"; |
158 | desc = "Privileged Register fault"; |
159 | break; |
159 | break; |
160 | case GE_RESREGFLD: |
160 | case GE_RESREGFLD: |
161 | desc = "Reserved Register/Field fault"; |
161 | desc = "Reserved Register/Field fault"; |
162 | break; |
162 | break; |
163 | case GE_DISBLDISTRAN: |
163 | case GE_DISBLDISTRAN: |
164 | desc = "Disabled Instruction Set Transition fault"; |
164 | desc = "Disabled Instruction Set Transition fault"; |
165 | break; |
165 | break; |
166 | case GE_ILLEGALDEP: |
166 | case GE_ILLEGALDEP: |
167 | desc = "Illegal Dependency fault"; |
167 | desc = "Illegal Dependency fault"; |
168 | break; |
168 | break; |
169 | default: |
169 | default: |
170 | desc = "unknown"; |
170 | desc = "unknown"; |
171 | break; |
171 | break; |
172 | } |
172 | } |
173 | 173 | ||
174 | panic("General Exception (%s)\n", desc); |
174 | panic("General Exception (%s)\n", desc); |
175 | } |
175 | } |
176 | 176 | ||
- | 177 | void fpu_enable(void); |
|
177 | 178 | ||
178 | void disabled_fp_register(__u64 vector, istate_t *istate) |
179 | void disabled_fp_register(__u64 vector, istate_t *istate) |
179 | { |
180 | { |
180 | #ifdef CONFIG_CPU_LAZY |
181 | #ifdef CONFIG_FPU_LAZY |
181 | scheduler_fpu_lazy_request(); |
182 | scheduler_fpu_lazy_request(); |
- | 183 | #else |
|
- | 184 | dump_interrupted_context(istate); |
|
- | 185 | panic("Interruption: %W (%s)\n", (__u16) vector, vector_to_string(vector)); |
|
182 | #endif |
186 | #endif |
183 | } |
187 | } |
184 | 188 | ||
185 | 189 | ||
186 | void nop_handler(__u64 vector, istate_t *istate) |
190 | void nop_handler(__u64 vector, istate_t *istate) |
187 | { |
191 | { |
188 | } |
192 | } |
189 | 193 | ||
190 | 194 | ||
191 | 195 | ||
192 | /** Handle syscall. */ |
196 | /** Handle syscall. */ |
193 | int break_instruction(__u64 vector, istate_t *istate) |
197 | int break_instruction(__u64 vector, istate_t *istate) |
194 | { |
198 | { |
195 | /* |
199 | /* |
196 | * Move to next instruction after BREAK. |
200 | * Move to next instruction after BREAK. |
197 | */ |
201 | */ |
198 | if (istate->cr_ipsr.ri == 2) { |
202 | if (istate->cr_ipsr.ri == 2) { |
199 | istate->cr_ipsr.ri = 0; |
203 | istate->cr_ipsr.ri = 0; |
200 | istate->cr_iip += 16; |
204 | istate->cr_iip += 16; |
201 | } else { |
205 | } else { |
202 | istate->cr_ipsr.ri++; |
206 | istate->cr_ipsr.ri++; |
203 | } |
207 | } |
204 | 208 | ||
205 | if (istate->in4 < SYSCALL_END) |
209 | if (istate->in4 < SYSCALL_END) |
206 | return syscall_table[istate->in4](istate->in0, istate->in1, istate->in2, istate->in3); |
210 | return syscall_table[istate->in4](istate->in0, istate->in1, istate->in2, istate->in3); |
207 | else |
211 | else |
208 | panic("Undefined syscall %d", istate->in4); |
212 | panic("Undefined syscall %d", istate->in4); |
209 | 213 | ||
210 | return -1; |
214 | return -1; |
211 | } |
215 | } |
212 | 216 | ||
213 | void universal_handler(__u64 vector, istate_t *istate) |
217 | void universal_handler(__u64 vector, istate_t *istate) |
214 | { |
218 | { |
215 | dump_interrupted_context(istate); |
219 | dump_interrupted_context(istate); |
216 | panic("Interruption: %W (%s)\n", (__u16) vector, vector_to_string(vector)); |
220 | panic("Interruption: %W (%s)\n", (__u16) vector, vector_to_string(vector)); |
217 | } |
221 | } |
218 | 222 | ||
219 | void external_interrupt(__u64 vector, istate_t *istate) |
223 | void external_interrupt(__u64 vector, istate_t *istate) |
220 | { |
224 | { |
221 | cr_ivr_t ivr; |
225 | cr_ivr_t ivr; |
222 | 226 | ||
223 | ivr.value = ivr_read(); |
227 | ivr.value = ivr_read(); |
224 | srlz_d(); |
228 | srlz_d(); |
225 | 229 | ||
226 | switch(ivr.vector) { |
230 | switch(ivr.vector) { |
227 | case INTERRUPT_TIMER: |
231 | case INTERRUPT_TIMER: |
228 | it_interrupt(); |
232 | it_interrupt(); |
229 | break; |
233 | break; |
230 | case INTERRUPT_SPURIOUS: |
234 | case INTERRUPT_SPURIOUS: |
231 | printf("cpu%d: spurious interrupt\n", CPU->id); |
235 | printf("cpu%d: spurious interrupt\n", CPU->id); |
232 | break; |
236 | break; |
233 | default: |
237 | default: |
234 | panic("\nUnhandled External Interrupt Vector %d\n", ivr.vector); |
238 | panic("\nUnhandled External Interrupt Vector %d\n", ivr.vector); |
235 | break; |
239 | break; |
236 | } |
240 | } |
237 | } |
241 | } |
238 | 242 |