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1 | /* |
1 | /* |
2 | * Copyright (c) 2007 Petr Stepan |
2 | * Copyright (c) 2007 Petr Stepan |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup arm32 |
29 | /** @addtogroup arm32 |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | * @brief Exception handlers and exception initialization routines. |
33 | * @brief Exception handlers and exception initialization routines. |
34 | */ |
34 | */ |
35 | 35 | ||
36 | #include <arch/exception.h> |
36 | #include <arch/exception.h> |
37 | #include <arch/debug/print.h> |
- | |
38 | #include <arch/memstr.h> |
37 | #include <arch/memstr.h> |
39 | #include <arch/regutils.h> |
38 | #include <arch/regutils.h> |
40 | #include <interrupt.h> |
39 | #include <interrupt.h> |
41 | #include <arch/machine.h> |
- | |
42 | #include <arch/mm/page_fault.h> |
40 | #include <arch/mm/page_fault.h> |
43 | #include <arch/barrier.h> |
41 | #include <arch/barrier.h> |
- | 42 | #include <arch/drivers/gxemul.h> |
|
44 | #include <print.h> |
43 | #include <print.h> |
45 | #include <syscall/syscall.h> |
44 | #include <syscall/syscall.h> |
46 | #include <udebug/udebug.h> |
45 | #include <udebug/udebug.h> |
47 | 46 | ||
48 | /** Offset used in calculation of exception handler's relative address. |
47 | /** Offset used in calculation of exception handler's relative address. |
49 | * |
48 | * |
50 | * @see install_handler() |
49 | * @see install_handler() |
51 | */ |
50 | */ |
52 | #define PREFETCH_OFFSET 0x8 |
51 | #define PREFETCH_OFFSET 0x8 |
53 | 52 | ||
54 | /** LDR instruction's code */ |
53 | /** LDR instruction's code */ |
55 | #define LDR_OPCODE 0xe59ff000 |
54 | #define LDR_OPCODE 0xe59ff000 |
56 | 55 | ||
57 | /** Number of exception vectors. */ |
56 | /** Number of exception vectors. */ |
58 | #define EXC_VECTORS 8 |
57 | #define EXC_VECTORS 8 |
59 | 58 | ||
60 | /** Size of memory block occupied by exception vectors. */ |
59 | /** Size of memory block occupied by exception vectors. */ |
61 | #define EXC_VECTORS_SIZE (EXC_VECTORS * 4) |
60 | #define EXC_VECTORS_SIZE (EXC_VECTORS * 4) |
62 | 61 | ||
63 | /** Switches to kernel stack and saves all registers there. |
62 | /** Switches to kernel stack and saves all registers there. |
64 | * |
63 | * |
65 | * Temporary exception stack is used to save a few registers |
64 | * Temporary exception stack is used to save a few registers |
66 | * before stack switch takes place. |
65 | * before stack switch takes place. |
- | 66 | * |
|
67 | */ |
67 | */ |
68 | inline static void setup_stack_and_save_regs() |
68 | inline static void setup_stack_and_save_regs() |
69 | { |
69 | { |
70 | asm volatile( |
70 | asm volatile ( |
71 | "ldr r13, =exc_stack \n" |
71 | "ldr r13, =exc_stack\n" |
72 | "stmfd r13!, {r0} \n" |
72 | "stmfd r13!, {r0}\n" |
73 | "mrs r0, spsr \n" |
73 | "mrs r0, spsr\n" |
74 | "and r0, r0, #0x1f \n" |
74 | "and r0, r0, #0x1f\n" |
75 | "cmp r0, #0x10 \n" |
75 | "cmp r0, #0x10\n" |
76 | "bne 1f \n" |
76 | "bne 1f\n" |
77 | 77 | ||
78 | /* prev mode was usermode */ |
78 | /* prev mode was usermode */ |
79 | "ldmfd r13!, {r0} \n" |
79 | "ldmfd r13!, {r0}\n" |
80 | "ldr r13, =supervisor_sp \n" |
80 | "ldr r13, =supervisor_sp\n" |
81 | "ldr r13, [r13] \n" |
81 | "ldr r13, [r13]\n" |
82 | "stmfd r13!, {lr} \n" |
82 | "stmfd r13!, {lr}\n" |
83 | "stmfd r13!, {r0-r12} \n" |
83 | "stmfd r13!, {r0-r12}\n" |
84 | "stmfd r13!, {r13, lr}^ \n" |
84 | "stmfd r13!, {r13, lr}^\n" |
85 | "mrs r0, spsr \n" |
85 | "mrs r0, spsr\n" |
86 | "stmfd r13!, {r0} \n" |
86 | "stmfd r13!, {r0}\n" |
87 | "b 2f \n" |
87 | "b 2f\n" |
88 | 88 | ||
89 | /* mode was not usermode */ |
89 | /* mode was not usermode */ |
90 | "1:\n" |
90 | "1:\n" |
91 | "stmfd r13!, {r1, r2, r3} \n" |
91 | "stmfd r13!, {r1, r2, r3}\n" |
92 | "mrs r1, cpsr \n" |
92 | "mrs r1, cpsr\n" |
93 | "mov r2, lr \n" |
93 | "mov r2, lr\n" |
94 | "bic r1, r1, #0x1f \n" |
94 | "bic r1, r1, #0x1f\n" |
95 | "orr r1, r1, r0 \n" |
95 | "orr r1, r1, r0\n" |
96 | "mrs r0, cpsr \n" |
96 | "mrs r0, cpsr\n" |
97 | "msr cpsr_c, r1 \n" |
97 | "msr cpsr_c, r1\n" |
98 | 98 | ||
99 | "mov r3, r13 \n" |
99 | "mov r3, r13\n" |
100 | "stmfd r13!, {r2} \n" |
100 | "stmfd r13!, {r2}\n" |
101 | "mov r2, lr \n" |
101 | "mov r2, lr\n" |
102 | "stmfd r13!, {r4-r12} \n" |
102 | "stmfd r13!, {r4-r12}\n" |
103 | "mov r1, r13 \n" |
103 | "mov r1, r13\n" |
- | 104 | ||
104 | /* the following two lines are for debugging */ |
105 | /* the following two lines are for debugging */ |
105 | "mov sp, #0 \n" |
106 | "mov sp, #0\n" |
106 | "mov lr, #0 \n" |
107 | "mov lr, #0\n" |
107 | "msr cpsr_c, r0 \n" |
108 | "msr cpsr_c, r0\n" |
108 | 109 | ||
109 | "ldmfd r13!, {r4, r5, r6, r7} \n" |
110 | "ldmfd r13!, {r4, r5, r6, r7}\n" |
110 | "stmfd r1!, {r4, r5, r6} \n" |
111 | "stmfd r1!, {r4, r5, r6}\n" |
111 | "stmfd r1!, {r7} \n" |
112 | "stmfd r1!, {r7}\n" |
112 | "stmfd r1!, {r2} \n" |
113 | "stmfd r1!, {r2}\n" |
113 | "stmfd r1!, {r3} \n" |
114 | "stmfd r1!, {r3}\n" |
114 | "mrs r0, spsr \n" |
115 | "mrs r0, spsr\n" |
115 | "stmfd r1!, {r0} \n" |
116 | "stmfd r1!, {r0}\n" |
116 | "mov r13, r1 \n" |
117 | "mov r13, r1\n" |
- | 118 | ||
117 | "2:\n" |
119 | "2:\n" |
118 | ); |
120 | ); |
119 | } |
121 | } |
120 | 122 | ||
121 | /** Returns from exception mode. |
123 | /** Returns from exception mode. |
122 | * |
124 | * |
123 | * Previously saved state of registers (including control register) |
125 | * Previously saved state of registers (including control register) |
124 | * is restored from the stack. |
126 | * is restored from the stack. |
125 | */ |
127 | */ |
126 | inline static void load_regs() |
128 | inline static void load_regs() |
127 | { |
129 | { |
128 | asm volatile( |
130 | asm volatile( |
129 | "ldmfd r13!, {r0} \n" |
131 | "ldmfd r13!, {r0} \n" |
130 | "msr spsr, r0 \n" |
132 | "msr spsr, r0 \n" |
131 | "and r0, r0, #0x1f \n" |
133 | "and r0, r0, #0x1f \n" |
132 | "cmp r0, #0x10 \n" |
134 | "cmp r0, #0x10 \n" |
133 | "bne 1f \n" |
135 | "bne 1f \n" |
134 | 136 | ||
135 | /* return to user mode */ |
137 | /* return to user mode */ |
136 | "ldmfd r13!, {r13, lr}^ \n" |
138 | "ldmfd r13!, {r13, lr}^ \n" |
137 | "b 2f \n" |
139 | "b 2f \n" |
138 | 140 | ||
139 | /* return to non-user mode */ |
141 | /* return to non-user mode */ |
140 | "1:\n" |
142 | "1:\n" |
141 | "ldmfd r13!, {r1, r2} \n" |
143 | "ldmfd r13!, {r1, r2} \n" |
142 | "mrs r3, cpsr \n" |
144 | "mrs r3, cpsr \n" |
143 | "bic r3, r3, #0x1f \n" |
145 | "bic r3, r3, #0x1f \n" |
144 | "orr r3, r3, r0 \n" |
146 | "orr r3, r3, r0 \n" |
145 | "mrs r0, cpsr \n" |
147 | "mrs r0, cpsr \n" |
146 | "msr cpsr_c, r3 \n" |
148 | "msr cpsr_c, r3 \n" |
147 | 149 | ||
148 | "mov r13, r1 \n" |
150 | "mov r13, r1 \n" |
149 | "mov lr, r2 \n" |
151 | "mov lr, r2 \n" |
150 | "msr cpsr_c, r0 \n" |
152 | "msr cpsr_c, r0 \n" |
151 | 153 | ||
152 | /* actual return */ |
154 | /* actual return */ |
153 | "2:\n" |
155 | "2:\n" |
154 | "ldmfd r13, {r0-r12, pc}^\n" |
156 | "ldmfd r13, {r0-r12, pc}^\n" |
155 | ); |
157 | ); |
156 | } |
158 | } |
157 | 159 | ||
158 | 160 | ||
159 | /** Switch CPU to mode in which interrupts are serviced (currently it |
161 | /** Switch CPU to mode in which interrupts are serviced (currently it |
160 | * is Undefined mode). |
162 | * is Undefined mode). |
161 | * |
163 | * |
162 | * The default mode for interrupt servicing (Interrupt Mode) |
164 | * The default mode for interrupt servicing (Interrupt Mode) |
163 | * can not be used because of nested interrupts (which can occur |
165 | * can not be used because of nested interrupts (which can occur |
164 | * because interrupts are enabled in higher levels of interrupt handler). |
166 | * because interrupts are enabled in higher levels of interrupt handler). |
165 | */ |
167 | */ |
166 | inline static void switch_to_irq_servicing_mode() |
168 | inline static void switch_to_irq_servicing_mode() |
167 | { |
169 | { |
168 | /* switch to Undefined mode */ |
170 | /* switch to Undefined mode */ |
169 | asm volatile( |
171 | asm volatile( |
170 | /* save regs used during switching */ |
172 | /* save regs used during switching */ |
171 | "stmfd sp!, {r0-r3} \n" |
173 | "stmfd sp!, {r0-r3} \n" |
172 | 174 | ||
173 | /* save stack pointer and link register to r1, r2 */ |
175 | /* save stack pointer and link register to r1, r2 */ |
174 | "mov r1, sp \n" |
176 | "mov r1, sp \n" |
175 | "mov r2, lr \n" |
177 | "mov r2, lr \n" |
176 | 178 | ||
177 | /* mode switch */ |
179 | /* mode switch */ |
178 | "mrs r0, cpsr \n" |
180 | "mrs r0, cpsr \n" |
179 | "bic r0, r0, #0x1f \n" |
181 | "bic r0, r0, #0x1f \n" |
180 | "orr r0, r0, #0x1b \n" |
182 | "orr r0, r0, #0x1b \n" |
181 | "msr cpsr_c, r0 \n" |
183 | "msr cpsr_c, r0 \n" |
182 | 184 | ||
183 | /* restore saved sp and lr */ |
185 | /* restore saved sp and lr */ |
184 | "mov sp, r1 \n" |
186 | "mov sp, r1 \n" |
185 | "mov lr, r2 \n" |
187 | "mov lr, r2 \n" |
186 | 188 | ||
187 | /* restore original regs */ |
189 | /* restore original regs */ |
188 | "ldmfd sp!, {r0-r3} \n" |
190 | "ldmfd sp!, {r0-r3} \n" |
189 | ); |
191 | ); |
190 | } |
192 | } |
191 | 193 | ||
192 | /** Calls exception dispatch routine. */ |
194 | /** Calls exception dispatch routine. */ |
193 | #define CALL_EXC_DISPATCH(exception) \ |
195 | #define CALL_EXC_DISPATCH(exception) \ |
- | 196 | asm volatile ( \ |
|
194 | asm("mov r0, %0" : : "i" (exception)); \ |
197 | "mov r0, %[exc]\n" \ |
195 | asm("mov r1, r13"); \ |
198 | "mov r1, r13\n" \ |
196 | asm("bl exc_dispatch"); |
199 | "bl exc_dispatch\n" \ |
- | 200 | :: [exc] "i" (exception) \ |
|
- | 201 | );\ |
|
197 | 202 | ||
198 | /** General exception handler. |
203 | /** General exception handler. |
199 | * |
204 | * |
200 | * Stores registers, dispatches the exception, |
205 | * Stores registers, dispatches the exception, |
201 | * and finally restores registers and returns from exception processing. |
206 | * and finally restores registers and returns from exception processing. |
202 | * |
207 | * |
203 | * @param exception Exception number. |
208 | * @param exception Exception number. |
204 | */ |
209 | */ |
205 | #define PROCESS_EXCEPTION(exception) \ |
210 | #define PROCESS_EXCEPTION(exception) \ |
206 | setup_stack_and_save_regs(); \ |
211 | setup_stack_and_save_regs(); \ |
207 | CALL_EXC_DISPATCH(exception) \ |
212 | CALL_EXC_DISPATCH(exception) \ |
208 | load_regs(); |
213 | load_regs(); |
209 | 214 | ||
210 | /** Updates specified exception vector to jump to given handler. |
215 | /** Updates specified exception vector to jump to given handler. |
211 | * |
216 | * |
212 | * Addresses of handlers are stored in memory following exception vectors. |
217 | * Addresses of handlers are stored in memory following exception vectors. |
213 | */ |
218 | */ |
214 | static void install_handler(unsigned handler_addr, unsigned *vector) |
219 | static void install_handler(unsigned handler_addr, unsigned *vector) |
215 | { |
220 | { |
216 | /* relative address (related to exc. vector) of the word |
221 | /* relative address (related to exc. vector) of the word |
217 | * where handler's address is stored |
222 | * where handler's address is stored |
218 | */ |
223 | */ |
219 | volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE - |
224 | volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE - |
220 | PREFETCH_OFFSET; |
225 | PREFETCH_OFFSET; |
221 | 226 | ||
222 | /* make it LDR instruction and store at exception vector */ |
227 | /* make it LDR instruction and store at exception vector */ |
223 | *vector = handler_address_ptr | LDR_OPCODE; |
228 | *vector = handler_address_ptr | LDR_OPCODE; |
224 | smc_coherence(*vector); |
229 | smc_coherence(*vector); |
225 | 230 | ||
226 | /* store handler's address */ |
231 | /* store handler's address */ |
227 | *(vector + EXC_VECTORS) = handler_addr; |
232 | *(vector + EXC_VECTORS) = handler_addr; |
228 | 233 | ||
229 | } |
234 | } |
230 | 235 | ||
231 | /** Low-level Reset Exception handler. */ |
236 | /** Low-level Reset Exception handler. */ |
232 | static void reset_exception_entry(void) |
237 | static void reset_exception_entry(void) |
233 | { |
238 | { |
234 | PROCESS_EXCEPTION(EXC_RESET); |
239 | PROCESS_EXCEPTION(EXC_RESET); |
235 | } |
240 | } |
236 | 241 | ||
237 | /** Low-level Software Interrupt Exception handler. */ |
242 | /** Low-level Software Interrupt Exception handler. */ |
238 | static void swi_exception_entry(void) |
243 | static void swi_exception_entry(void) |
239 | { |
244 | { |
240 | PROCESS_EXCEPTION(EXC_SWI); |
245 | PROCESS_EXCEPTION(EXC_SWI); |
241 | } |
246 | } |
242 | 247 | ||
243 | /** Low-level Undefined Instruction Exception handler. */ |
248 | /** Low-level Undefined Instruction Exception handler. */ |
244 | static void undef_instr_exception_entry(void) |
249 | static void undef_instr_exception_entry(void) |
245 | { |
250 | { |
246 | PROCESS_EXCEPTION(EXC_UNDEF_INSTR); |
251 | PROCESS_EXCEPTION(EXC_UNDEF_INSTR); |
247 | } |
252 | } |
248 | 253 | ||
249 | /** Low-level Fast Interrupt Exception handler. */ |
254 | /** Low-level Fast Interrupt Exception handler. */ |
250 | static void fiq_exception_entry(void) |
255 | static void fiq_exception_entry(void) |
251 | { |
256 | { |
252 | PROCESS_EXCEPTION(EXC_FIQ); |
257 | PROCESS_EXCEPTION(EXC_FIQ); |
253 | } |
258 | } |
254 | 259 | ||
255 | /** Low-level Prefetch Abort Exception handler. */ |
260 | /** Low-level Prefetch Abort Exception handler. */ |
256 | static void prefetch_abort_exception_entry(void) |
261 | static void prefetch_abort_exception_entry(void) |
257 | { |
262 | { |
- | 263 | asm volatile ( |
|
258 | asm("sub lr, lr, #4"); |
264 | "sub lr, lr, #4" |
- | 265 | ); |
|
- | 266 | ||
259 | PROCESS_EXCEPTION(EXC_PREFETCH_ABORT); |
267 | PROCESS_EXCEPTION(EXC_PREFETCH_ABORT); |
260 | } |
268 | } |
261 | 269 | ||
262 | /** Low-level Data Abort Exception handler. */ |
270 | /** Low-level Data Abort Exception handler. */ |
263 | static void data_abort_exception_entry(void) |
271 | static void data_abort_exception_entry(void) |
264 | { |
272 | { |
- | 273 | asm volatile ( |
|
265 | asm("sub lr, lr, #8"); |
274 | "sub lr, lr, #8" |
- | 275 | ); |
|
- | 276 | ||
266 | PROCESS_EXCEPTION(EXC_DATA_ABORT); |
277 | PROCESS_EXCEPTION(EXC_DATA_ABORT); |
267 | } |
278 | } |
268 | 279 | ||
269 | /** Low-level Interrupt Exception handler. |
280 | /** Low-level Interrupt Exception handler. |
270 | * |
281 | * |
271 | * CPU is switched to Undefined mode before further interrupt processing |
282 | * CPU is switched to Undefined mode before further interrupt processing |
272 | * because of possible occurence of nested interrupt exception, which |
283 | * because of possible occurence of nested interrupt exception, which |
273 | * would overwrite (and thus spoil) stack pointer. |
284 | * would overwrite (and thus spoil) stack pointer. |
274 | */ |
285 | */ |
275 | static void irq_exception_entry(void) |
286 | static void irq_exception_entry(void) |
276 | { |
287 | { |
- | 288 | asm volatile ( |
|
277 | asm("sub lr, lr, #4"); |
289 | "sub lr, lr, #4" |
- | 290 | ); |
|
- | 291 | ||
278 | setup_stack_and_save_regs(); |
292 | setup_stack_and_save_regs(); |
279 | 293 | ||
280 | switch_to_irq_servicing_mode(); |
294 | switch_to_irq_servicing_mode(); |
281 | 295 | ||
282 | CALL_EXC_DISPATCH(EXC_IRQ) |
296 | CALL_EXC_DISPATCH(EXC_IRQ) |
283 | 297 | ||
284 | load_regs(); |
298 | load_regs(); |
285 | } |
299 | } |
286 | 300 | ||
287 | /** Software Interrupt handler. |
301 | /** Software Interrupt handler. |
288 | * |
302 | * |
289 | * Dispatches the syscall. |
303 | * Dispatches the syscall. |
290 | */ |
304 | */ |
291 | static void swi_exception(int exc_no, istate_t *istate) |
305 | static void swi_exception(int exc_no, istate_t *istate) |
292 | { |
306 | { |
293 | istate->r0 = syscall_handler(istate->r0, istate->r1, istate->r2, |
307 | istate->r0 = syscall_handler(istate->r0, istate->r1, istate->r2, |
294 | istate->r3, istate->r4, istate->r5, istate->r6); |
308 | istate->r3, istate->r4, istate->r5, istate->r6); |
295 | } |
309 | } |
296 | 310 | ||
- | 311 | /** Returns the mask of active interrupts. */ |
|
- | 312 | static inline uint32_t gxemul_irqc_get_sources(void) |
|
- | 313 | { |
|
- | 314 | return *((uint32_t *) gxemul_irqc); |
|
- | 315 | } |
|
- | 316 | ||
297 | /** Interrupt Exception handler. |
317 | /** Interrupt Exception handler. |
298 | * |
318 | * |
299 | * Determines the sources of interrupt and calls their handlers. |
319 | * Determines the sources of interrupt and calls their handlers. |
300 | */ |
320 | */ |
301 | static void irq_exception(int exc_no, istate_t *istate) |
321 | static void irq_exception(int exc_no, istate_t *istate) |
302 | { |
322 | { |
- | 323 | uint32_t sources = gxemul_irqc_get_sources(); |
|
- | 324 | unsigned int i; |
|
- | 325 | ||
- | 326 | for (i = 0; i < GXEMUL_IRQC_MAX_IRQ; i++) { |
|
- | 327 | if (sources & (1 << i)) { |
|
303 | machine_irq_exception(exc_no, istate); |
328 | irq_t *irq = irq_dispatch_and_lock(i); |
- | 329 | if (irq) { |
|
- | 330 | /* The IRQ handler was found. */ |
|
- | 331 | irq->handler(irq); |
|
- | 332 | spinlock_unlock(&irq->lock); |
|
- | 333 | } else { |
|
- | 334 | /* Spurious interrupt.*/ |
|
- | 335 | printf("cpu%d: spurious interrupt (inum=%d)\n", |
|
- | 336 | CPU->id, i); |
|
- | 337 | } |
|
- | 338 | } |
|
- | 339 | } |
|
304 | } |
340 | } |
305 | 341 | ||
306 | /** Fills exception vectors with appropriate exception handlers. */ |
342 | /** Fills exception vectors with appropriate exception handlers. */ |
307 | void install_exception_handlers(void) |
343 | void install_exception_handlers(void) |
308 | { |
344 | { |
309 | install_handler((unsigned) reset_exception_entry, |
345 | install_handler((unsigned) reset_exception_entry, |
310 | (unsigned *) EXC_RESET_VEC); |
346 | (unsigned *) EXC_RESET_VEC); |
311 | 347 | ||
312 | install_handler((unsigned) undef_instr_exception_entry, |
348 | install_handler((unsigned) undef_instr_exception_entry, |
313 | (unsigned *) EXC_UNDEF_INSTR_VEC); |
349 | (unsigned *) EXC_UNDEF_INSTR_VEC); |
314 | 350 | ||
315 | install_handler((unsigned) swi_exception_entry, |
351 | install_handler((unsigned) swi_exception_entry, |
316 | (unsigned *) EXC_SWI_VEC); |
352 | (unsigned *) EXC_SWI_VEC); |
317 | 353 | ||
318 | install_handler((unsigned) prefetch_abort_exception_entry, |
354 | install_handler((unsigned) prefetch_abort_exception_entry, |
319 | (unsigned *) EXC_PREFETCH_ABORT_VEC); |
355 | (unsigned *) EXC_PREFETCH_ABORT_VEC); |
320 | 356 | ||
321 | install_handler((unsigned) data_abort_exception_entry, |
357 | install_handler((unsigned) data_abort_exception_entry, |
322 | (unsigned *) EXC_DATA_ABORT_VEC); |
358 | (unsigned *) EXC_DATA_ABORT_VEC); |
323 | 359 | ||
324 | install_handler((unsigned) irq_exception_entry, |
360 | install_handler((unsigned) irq_exception_entry, |
325 | (unsigned *) EXC_IRQ_VEC); |
361 | (unsigned *) EXC_IRQ_VEC); |
326 | 362 | ||
327 | install_handler((unsigned)fiq_exception_entry, |
363 | install_handler((unsigned) fiq_exception_entry, |
328 | (unsigned *) EXC_FIQ_VEC); |
364 | (unsigned *) EXC_FIQ_VEC); |
329 | } |
365 | } |
330 | 366 | ||
331 | #ifdef HIGH_EXCEPTION_VECTORS |
367 | #ifdef HIGH_EXCEPTION_VECTORS |
332 | /** Activates use of high exception vectors addresses. */ |
368 | /** Activates use of high exception vectors addresses. */ |
333 | static void high_vectors(void) |
369 | static void high_vectors(void) |
334 | { |
370 | { |
335 | uint32_t control_reg; |
371 | uint32_t control_reg; |
336 | 372 | ||
- | 373 | asm volatile ( |
|
- | 374 | "mrc p15, 0, %[control_reg], c1, c1" |
|
337 | asm volatile("mrc p15, 0, %0, c1, c1" : "=r" (control_reg)); |
375 | : [control_reg] "=r" (control_reg) |
- | 376 | ); |
|
338 | 377 | ||
339 | /* switch on the high vectors bit */ |
378 | /* switch on the high vectors bit */ |
340 | control_reg |= CP15_R1_HIGH_VECTORS_BIT; |
379 | control_reg |= CP15_R1_HIGH_VECTORS_BIT; |
341 | 380 | ||
- | 381 | asm volatile ( |
|
- | 382 | "mcr p15, 0, %[control_reg], c1, c1" |
|
342 | asm volatile("mcr p15, 0, %0, c1, c1" : : "r" (control_reg)); |
383 | :: [control_reg] "r" (control_reg) |
- | 384 | ); |
|
343 | } |
385 | } |
344 | #endif |
386 | #endif |
345 | 387 | ||
346 | /** Initializes exception handling. |
388 | /** Initializes exception handling. |
347 | * |
389 | * |
348 | * Installs low-level exception handlers and then registers |
390 | * Installs low-level exception handlers and then registers |
349 | * exceptions and their handlers to kernel exception dispatcher. |
391 | * exceptions and their handlers to kernel exception dispatcher. |
350 | */ |
392 | */ |
351 | void exception_init(void) |
393 | void exception_init(void) |
352 | { |
394 | { |
353 | #ifdef HIGH_EXCEPTION_VECTORS |
395 | #ifdef HIGH_EXCEPTION_VECTORS |
354 | high_vectors(); |
396 | high_vectors(); |
355 | #endif |
397 | #endif |
356 | install_exception_handlers(); |
398 | install_exception_handlers(); |
357 | 399 | ||
358 | exc_register(EXC_IRQ, "interrupt", (iroutine) irq_exception); |
400 | exc_register(EXC_IRQ, "interrupt", (iroutine) irq_exception); |
359 | exc_register(EXC_PREFETCH_ABORT, "prefetch abort", |
401 | exc_register(EXC_PREFETCH_ABORT, "prefetch abort", |
360 | (iroutine) prefetch_abort); |
402 | (iroutine) prefetch_abort); |
361 | exc_register(EXC_DATA_ABORT, "data abort", (iroutine) data_abort); |
403 | exc_register(EXC_DATA_ABORT, "data abort", (iroutine) data_abort); |
362 | exc_register(EXC_SWI, "software interrupt", (iroutine) swi_exception); |
404 | exc_register(EXC_SWI, "software interrupt", (iroutine) swi_exception); |
363 | } |
405 | } |
364 | 406 | ||
365 | /** Prints #istate_t structure content. |
407 | /** Prints #istate_t structure content. |
366 | * |
408 | * |
367 | * @param istate Structure to be printed. |
409 | * @param istate Structure to be printed. |
368 | */ |
410 | */ |
369 | void print_istate(istate_t *istate) |
411 | void print_istate(istate_t *istate) |
370 | { |
412 | { |
371 | dprintf("istate dump:\n"); |
413 | printf("istate dump:\n"); |
372 | 414 | ||
373 | dprintf(" r0: %x r1: %x r2: %x r3: %x\n", |
415 | printf(" r0: %x r1: %x r2: %x r3: %x\n", |
374 | istate->r0, istate->r1, istate->r2, istate->r3); |
416 | istate->r0, istate->r1, istate->r2, istate->r3); |
375 | dprintf(" r4: %x r5: %x r6: %x r7: %x\n", |
417 | printf(" r4: %x r5: %x r6: %x r7: %x\n", |
376 | istate->r4, istate->r5, istate->r6, istate->r7); |
418 | istate->r4, istate->r5, istate->r6, istate->r7); |
377 | dprintf(" r8: %x r8: %x r10: %x r11: %x\n", |
419 | printf(" r8: %x r8: %x r10: %x r11: %x\n", |
378 | istate->r8, istate->r9, istate->r10, istate->r11); |
420 | istate->r8, istate->r9, istate->r10, istate->r11); |
379 | dprintf(" r12: %x sp: %x lr: %x spsr: %x\n", |
421 | printf(" r12: %x sp: %x lr: %x spsr: %x\n", |
380 | istate->r12, istate->sp, istate->lr, istate->spsr); |
422 | istate->r12, istate->sp, istate->lr, istate->spsr); |
381 | 423 | ||
382 | dprintf(" pc: %x\n", istate->pc); |
424 | printf(" pc: %x\n", istate->pc); |
383 | } |
425 | } |
384 | 426 | ||
385 | /** @} |
427 | /** @} |
386 | */ |
428 | */ |
387 | 429 |