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Rev 4669 Rev 4692
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#
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#
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# Copyright (c) 2009 Vineeth Pillai
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# Copyright (c) 2009 Vineeth Pillai
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# All rights reserved.
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# All rights reserved.
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#
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#
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# Redistribution and use in source and binary forms, with or without
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions
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# modification, are permitted provided that the following conditions
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# are met:
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# are met:
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#
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#
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# - Redistributions of source code must retain the above copyright
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# - Redistributions of source code must retain the above copyright
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#   notice, this list of conditions and the following disclaimer.
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#   notice, this list of conditions and the following disclaimer.
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# - Redistributions in binary form must reproduce the above copyright
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# - Redistributions in binary form must reproduce the above copyright
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#   notice, this list of conditions and the following disclaimer in the
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#   notice, this list of conditions and the following disclaimer in the
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#   documentation and/or other materials provided with the distribution.
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#   documentation and/or other materials provided with the distribution.
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# - The name of the author may not be used to endorse or promote products
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# - The name of the author may not be used to endorse or promote products
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#   derived from this software without specific prior written permission.
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#   derived from this software without specific prior written permission.
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#
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#
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# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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#
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.text
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.text
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.global irq_exception_entry
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.global irq_exception_entry
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.global fiq_exception_entry
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.global fiq_exception_entry
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.global data_abort_exception_entry
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.global data_abort_exception_entry
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.global prefetch_abort_exception_entry
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.global prefetch_abort_exception_entry
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.global undef_instr_exception_entry
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.global undef_instr_exception_entry
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.global swi_exception_entry
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.global swi_exception_entry
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.global reset_exception_entry
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.global reset_exception_entry
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# Switches to kernel stack and saves all registers there.
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# Switches to kernel stack and saves all registers there.
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#
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#
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#  The stack frame created by the function looks like:
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#  The stack frame created by the function looks like:
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#
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#
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#              |_________________|
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#              |_________________|
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#              |                 |
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#              |                 |
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#              |     SPSR        |
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#              |     SPSR        |
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#              |                 |
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#              |                 |
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#              |_________________|
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#              |_________________|
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#              | Stack Pointer   |
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#              | Stack Pointer   |
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#              |      of         |
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#              |      of         |
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#              | Previous Mode   |
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#              | Previous Mode   |
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#              |_________________|
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#              |_________________|
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#              | Return address  |
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#              | Return address  |
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#              |      of         |
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#              |      of         |
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#              | Previous Mode   |
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#              | Previous Mode   |
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#              |_________________|
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#              |_________________|
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#              |   R0  - R12     |
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#              |   R0  - R12     |
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#              |      of         |
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#              |      of         |
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#              | Previous Mode   |
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#              | Previous Mode   |
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#              |_________________|
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#              |_________________|
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#              | Return address  |
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#              | Return address  |
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#              |     from        |
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#              |     from        |
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#              |Exception Handler|
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#              |Exception Handler|
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#              |_________________|
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#              |_________________|
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#              |                 |
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#              |                 |
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#
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#
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#
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#
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.macro SAVE_REGS_TO_STACK
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.macro SAVE_REGS_TO_STACK
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	stmfd r13!, {r0-r3}
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	stmfd r13!, {r0-r3}
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	mov r3, sp
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	mov r3, sp
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	add sp, sp, #16
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	add sp, sp, #16
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	mrs r1, cpsr
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	mrs r1, cpsr
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	bic r1, r1, #0x1f
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	bic r1, r1, #0x1f
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	mrs r2, spsr
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	mrs r2, spsr
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	and r0, r2, #0x1f
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	and r0, r2, #0x1f
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	cmp r0, #0x10
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	cmp r0, #0x10
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	bne 1f
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	bne 1f
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	# prev mode was usermode
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	# prev mode was usermode
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	mov r0, lr
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	mov r0, lr
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	# Switch to supervisor mode
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	# Switch to supervisor mode
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	orr r1, r1, #0x13
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	orr r1, r1, #0x13
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	msr cpsr_c, r1
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	msr cpsr_c, r1
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	# Load sp with [supervisor_sp]
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	# Load sp with [supervisor_sp]
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	ldr r13, =supervisor_sp
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	ldr r13, =supervisor_sp
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	ldr r13, [r13]
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	ldr r13, [r13]
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	# Populate the stack frame
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	# Populate the stack frame
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	msr spsr, r2
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	msr spsr, r2
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	mov lr, r0
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	mov lr, r0
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	stmfd r13!, {lr}
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	stmfd r13!, {lr}
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	stmfd r13!, {r4-r12}
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	stmfd r13!, {r4-r12}
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	ldmfd r3!, {r4-r7}
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	ldmfd r3!, {r4-r7}
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	stmfd r13!, {r4-r7}
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	stmfd r13!, {r4-r7}
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	stmfd r13!, {r13, lr}^
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	stmfd r13!, {r13, lr}^
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	stmfd r13!, {r2}
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	stmfd r13!, {r2}
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	b 2f
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	b 2f
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	# mode was not usermode
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	# mode was not usermode
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1:
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1:
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	# Switch to previous mode which is undoubtedly the supervisor mode
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	# Switch to previous mode which is undoubtedly the supervisor mode
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	orr r1, r1, r0
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	orr r1, r1, r0
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	mov r0, lr
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	mov r0, lr
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	msr cpsr_c, r1
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	msr cpsr_c, r1
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	# Populate the stack frame
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	# Populate the stack frame
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	mov r1, sp
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	mov r1, sp
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	stmfd r13!, {r0}
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	stmfd r13!, {r0}
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	stmfd r13!, {r4-r12}
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	stmfd r13!, {r4-r12}
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	# Store r0-r3 in r4-r7 and then push it on to stack
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	# Store r0-r3 in r4-r7 and then push it on to stack
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	ldmfd r3!, {r4-r7}
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	ldmfd r3!, {r4-r7}
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	stmfd r13!, {r4-r7}
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	stmfd r13!, {r4-r7}
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	# Push return address and stack pointer on to stack
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	# Push return address and stack pointer on to stack
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	stmfd r13!, {lr}
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	stmfd r13!, {lr}
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	stmfd r13!, {r1}
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	stmfd r13!, {r1}
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	mov lr, r0
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	mov lr, r0
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	msr spsr, r2
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	msr spsr, r2
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	stmfd r13!, {r2}
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	stmfd r13!, {r2}
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2:
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2:
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.endm
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.endm
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.macro LOAD_REGS_FROM_STACK
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.macro LOAD_REGS_FROM_STACK
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	ldmfd r13!, {r0}
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	ldmfd r13!, {r0}
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	msr spsr, r0
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	msr spsr, r0
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	and r0, r0, #0x1f
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	and r0, r0, #0x1f
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	cmp r0, #0x10
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	cmp r0, #0x10
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	bne 1f
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	bne 1f
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	# return to user mode
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	# return to user mode
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	ldmfd r13!, {r13, lr}^
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	ldmfd r13!, {r13, lr}^
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	b 2f
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	b 2f
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	# return to non-user mode
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	# return to non-user mode
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1:
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1:
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	ldmfd r13!, {r1, lr}
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	ldmfd r13!, {r1, lr}
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2:
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2:
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	ldmfd r13!, {r0-r12, pc}^
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	ldmfd r13!, {r0-r12, pc}^
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.endm
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.endm
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reset_exception_entry:
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reset_exception_entry:
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	SAVE_REGS_TO_STACK
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	SAVE_REGS_TO_STACK
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	mov r0, #0
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	mov r0, #0
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	mov r1, r13
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	mov r1, r13
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	bl exc_dispatch
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	bl exc_dispatch
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	LOAD_REGS_FROM_STACK
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	LOAD_REGS_FROM_STACK
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irq_exception_entry:
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irq_exception_entry:
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	sub lr, lr, #4
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	sub lr, lr, #4
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	SAVE_REGS_TO_STACK
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	SAVE_REGS_TO_STACK
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	mov r0, #5
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	mov r0, #5
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	mov r1, r13
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	mov r1, r13
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	bl exc_dispatch
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	bl exc_dispatch
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	LOAD_REGS_FROM_STACK
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	LOAD_REGS_FROM_STACK
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fiq_exception_entry:
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fiq_exception_entry:
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	sub lr, lr, #4
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	sub lr, lr, #4
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	SAVE_REGS_TO_STACK
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	SAVE_REGS_TO_STACK
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	mov r0, #6
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	mov r0, #6
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	mov r1, r13
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	mov r1, r13
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	bl exc_dispatch
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	bl exc_dispatch
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	LOAD_REGS_FROM_STACK
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	LOAD_REGS_FROM_STACK
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undef_instr_exception_entry:
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undef_instr_exception_entry:
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	SAVE_REGS_TO_STACK
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	SAVE_REGS_TO_STACK
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	mov r0, #1
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	mov r0, #1
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	mov r1, r13
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	mov r1, r13
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	bl exc_dispatch
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	bl exc_dispatch
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	LOAD_REGS_FROM_STACK
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	LOAD_REGS_FROM_STACK
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prefetch_abort_exception_entry:
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prefetch_abort_exception_entry:
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	sub lr, lr, #4
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	sub lr, lr, #4
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	SAVE_REGS_TO_STACK
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	SAVE_REGS_TO_STACK
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	mov r0, #3
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	mov r0, #3
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	mov r1, r13
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	mov r1, r13
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	bl exc_dispatch
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	bl exc_dispatch
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	LOAD_REGS_FROM_STACK
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	LOAD_REGS_FROM_STACK
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data_abort_exception_entry:
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data_abort_exception_entry:
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	sub lr, lr, #8
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	sub lr, lr, #8
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	SAVE_REGS_TO_STACK
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	SAVE_REGS_TO_STACK
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	mov r0, #4
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	mov r0, #4
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	mov r1, r13
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	mov r1, r13
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	bl exc_dispatch
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	bl exc_dispatch
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	LOAD_REGS_FROM_STACK
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	LOAD_REGS_FROM_STACK
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swi_exception_entry:
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swi_exception_entry:
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	ldr r13, =exc_stack
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	ldr r13, =exc_stack
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	SAVE_REGS_TO_STACK
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	SAVE_REGS_TO_STACK
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	mov r0, #2
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	mov r0, #2
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	mov r1, r13
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	mov r1, r13
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	bl exc_dispatch
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	bl exc_dispatch
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	LOAD_REGS_FROM_STACK
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	LOAD_REGS_FROM_STACK
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