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1 | # |
1 | # |
2 | # Copyright (c) 2005 Jakub Jermar |
2 | # Copyright (c) 2005 Jakub Jermar |
3 | # All rights reserved. |
3 | # All rights reserved. |
4 | # |
4 | # |
5 | # Redistribution and use in source and binary forms, with or without |
5 | # Redistribution and use in source and binary forms, with or without |
6 | # modification, are permitted provided that the following conditions |
6 | # modification, are permitted provided that the following conditions |
7 | # are met: |
7 | # are met: |
8 | # |
8 | # |
9 | # - Redistributions of source code must retain the above copyright |
9 | # - Redistributions of source code must retain the above copyright |
10 | # notice, this list of conditions and the following disclaimer. |
10 | # notice, this list of conditions and the following disclaimer. |
11 | # - Redistributions in binary form must reproduce the above copyright |
11 | # - Redistributions in binary form must reproduce the above copyright |
12 | # notice, this list of conditions and the following disclaimer in the |
12 | # notice, this list of conditions and the following disclaimer in the |
13 | # documentation and/or other materials provided with the distribution. |
13 | # documentation and/or other materials provided with the distribution. |
14 | # - The name of the author may not be used to endorse or promote products |
14 | # - The name of the author may not be used to endorse or promote products |
15 | # derived from this software without specific prior written permission. |
15 | # derived from this software without specific prior written permission. |
16 | # |
16 | # |
17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | # |
27 | # |
28 | 28 | ||
29 | #include <arch/arch.h> |
29 | #include <arch/arch.h> |
30 | #include <arch/regdef.h> |
30 | #include <arch/regdef.h> |
31 | #include <arch/boot/boot.h> |
31 | #include <arch/boot/boot.h> |
32 | #include <arch/stack.h> |
32 | #include <arch/stack.h> |
33 | 33 | ||
34 | #include <arch/mm/mmu.h> |
34 | #include <arch/mm/mmu.h> |
35 | #include <arch/mm/tlb.h> |
35 | #include <arch/mm/tlb.h> |
36 | #include <arch/mm/tte.h> |
36 | #include <arch/mm/tte.h> |
37 | 37 | ||
38 | #ifdef CONFIG_SMP |
38 | #ifdef CONFIG_SMP |
39 | #include <arch/context_offset.h> |
39 | #include <arch/context_offset.h> |
40 | #endif |
40 | #endif |
41 | 41 | ||
42 | .register %g2, #scratch |
42 | .register %g2, #scratch |
43 | .register %g3, #scratch |
43 | .register %g3, #scratch |
44 | 44 | ||
45 | .section K_TEXT_START, "ax" |
45 | .section K_TEXT_START, "ax" |
46 | 46 | ||
47 | #define BSP_FLAG 1 |
47 | #define BSP_FLAG 1 |
48 | 48 | ||
49 | /* |
49 | /* |
50 | * 2^PHYSMEM_ADDR_SIZE is the size of the physical address space on |
50 | * 2^PHYSMEM_ADDR_SIZE is the size of the physical address space on |
51 | * a given processor. |
51 | * a given processor. |
52 | */ |
52 | */ |
53 | #if defined (US) |
53 | #if defined (US) |
54 | #define PHYSMEM_ADDR_SIZE 41 |
54 | #define PHYSMEM_ADDR_SIZE 41 |
55 | #elif defined (US3) |
55 | #elif defined (US3) |
56 | #define PHYSMEM_ADDR_SIZE 43 |
56 | #define PHYSMEM_ADDR_SIZE 43 |
57 | #endif |
57 | #endif |
58 | 58 | ||
59 | /* |
59 | /* |
60 | * Here is where the kernel is passed control from the boot loader. |
60 | * Here is where the kernel is passed control from the boot loader. |
61 | * |
61 | * |
62 | * The registers are expected to be in this state: |
62 | * The registers are expected to be in this state: |
63 | * - %o0 starting address of physical memory + bootstrap processor flag |
63 | * - %o0 starting address of physical memory + bootstrap processor flag |
64 | * bits 63...1: physical memory starting address / 2 |
64 | * bits 63...1: physical memory starting address / 2 |
65 | * bit 0: non-zero on BSP processor, zero on AP processors |
65 | * bit 0: non-zero on BSP processor, zero on AP processors |
66 | * - %o1 bootinfo structure address (BSP only) |
66 | * - %o1 bootinfo structure address (BSP only) |
67 | * - %o2 bootinfo structure size (BSP only) |
67 | * - %o2 bootinfo structure size (BSP only) |
68 | * |
68 | * |
69 | * Moreover, we depend on boot having established the following environment: |
69 | * Moreover, we depend on boot having established the following environment: |
70 | * - TLBs are on |
70 | * - TLBs are on |
71 | * - identity mapping for the kernel image |
71 | * - identity mapping for the kernel image |
72 | */ |
72 | */ |
73 | 73 | ||
74 | .global kernel_image_start |
74 | .global kernel_image_start |
75 | kernel_image_start: |
75 | kernel_image_start: |
76 | mov BSP_FLAG, %l0 |
76 | mov BSP_FLAG, %l0 |
77 | and %o0, %l0, %l7 ! l7 <= bootstrap processor? |
77 | and %o0, %l0, %l7 ! l7 <= bootstrap processor? |
78 | andn %o0, %l0, %l6 ! l6 <= start of physical memory |
78 | andn %o0, %l0, %l6 ! l6 <= start of physical memory |
79 | 79 | ||
80 | ! Get bits (PHYSMEM_ADDR_SIZE - 1):13 of physmem_base. |
80 | ! Get bits (PHYSMEM_ADDR_SIZE - 1):13 of physmem_base. |
81 | srlx %l6, 13, %l5 |
81 | srlx %l6, 13, %l5 |
82 | 82 | ||
83 | ! l5 <= physmem_base[(PHYSMEM_ADDR_SIZE - 1):13] |
83 | ! l5 <= physmem_base[(PHYSMEM_ADDR_SIZE - 1):13] |
84 | sllx %l5, 13 + (63 - (PHYSMEM_ADDR_SIZE - 1)), %l5 |
84 | sllx %l5, 13 + (63 - (PHYSMEM_ADDR_SIZE - 1)), %l5 |
85 | srlx %l5, 63 - (PHYSMEM_ADDR_SIZE - 1), %l5 |
85 | srlx %l5, 63 - (PHYSMEM_ADDR_SIZE - 1), %l5 |
86 | 86 | ||
87 | /* |
87 | /* |
88 | * Setup basic runtime environment. |
88 | * Setup basic runtime environment. |
89 | */ |
89 | */ |
90 | 90 | ||
91 | wrpr %g0, NWINDOWS - 2, %cansave ! set maximum saveable windows |
91 | wrpr %g0, NWINDOWS - 2, %cansave ! set maximum saveable windows |
92 | wrpr %g0, 0, %canrestore ! get rid of windows we will |
92 | wrpr %g0, 0, %canrestore ! get rid of windows we will |
93 | ! never need again |
93 | ! never need again |
94 | wrpr %g0, 0, %otherwin ! make sure the window state is |
94 | wrpr %g0, 0, %otherwin ! make sure the window state is |
95 | ! consistent |
95 | ! consistent |
96 | wrpr %g0, NWINDOWS - 1, %cleanwin ! prevent needless clean_window |
96 | wrpr %g0, NWINDOWS - 1, %cleanwin ! prevent needless clean_window |
97 | ! traps for kernel |
97 | ! traps for kernel |
98 | 98 | ||
99 | wrpr %g0, 0, %wstate ! use the default spill/fill trap |
99 | wrpr %g0, 0, %wstate ! use default spill/fill trap |
100 | 100 | ||
101 | wrpr %g0, 0, %tl ! TL = 0, primary context |
101 | wrpr %g0, 0, %tl ! TL = 0, primary context |
102 | ! register is used |
102 | ! register is used |
103 | 103 | ||
104 | wrpr %g0, PSTATE_PRIV_BIT, %pstate ! disable interrupts and disable |
104 | wrpr %g0, PSTATE_PRIV_BIT, %pstate ! disable interrupts and disable |
105 | ! 32-bit address masking |
105 | ! 32-bit address masking |
106 | 106 | ||
107 | wrpr %g0, 0, %pil ! intialize %pil |
107 | wrpr %g0, 0, %pil ! intialize %pil |
108 | 108 | ||
109 | /* |
109 | /* |
110 | * Switch to kernel trap table. |
110 | * Switch to kernel trap table. |
111 | */ |
111 | */ |
112 | sethi %hi(trap_table), %g1 |
112 | sethi %hi(trap_table), %g1 |
113 | wrpr %g1, %lo(trap_table), %tba |
113 | wrpr %g1, %lo(trap_table), %tba |
114 | 114 | ||
115 | /* |
115 | /* |
116 | * Take over the DMMU by installing locked TTE entry identically |
116 | * Take over the DMMU by installing locked TTE entry identically |
117 | * mapping the first 4M of memory. |
117 | * mapping the first 4M of memory. |
118 | * |
118 | * |
119 | * In case of DMMU, no FLUSH instructions need to be issued. Because of |
119 | * In case of DMMU, no FLUSH instructions need to be issued. Because of |
120 | * that, the old DTLB contents can be demapped pretty straightforwardly |
120 | * that, the old DTLB contents can be demapped pretty straightforwardly |
121 | * and without causing any traps. |
121 | * and without causing any traps. |
122 | */ |
122 | */ |
123 | 123 | ||
124 | wr %g0, ASI_DMMU, %asi |
124 | wr %g0, ASI_DMMU, %asi |
125 | 125 | ||
126 | #define SET_TLB_DEMAP_CMD(r1, context_id) \ |
126 | #define SET_TLB_DEMAP_CMD(r1, context_id) \ |
127 | set (TLB_DEMAP_CONTEXT << TLB_DEMAP_TYPE_SHIFT) | (context_id << \ |
127 | set (TLB_DEMAP_CONTEXT << TLB_DEMAP_TYPE_SHIFT) | (context_id << \ |
128 | TLB_DEMAP_CONTEXT_SHIFT), %r1 |
128 | TLB_DEMAP_CONTEXT_SHIFT), %r1 |
129 | 129 | ||
130 | ! demap context 0 |
130 | ! demap context 0 |
131 | SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS) |
131 | SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS) |
132 | stxa %g0, [%g1] ASI_DMMU_DEMAP |
132 | stxa %g0, [%g1] ASI_DMMU_DEMAP |
133 | membar #Sync |
133 | membar #Sync |
134 | 134 | ||
135 | #define SET_TLB_TAG(r1, context) \ |
135 | #define SET_TLB_TAG(r1, context) \ |
136 | set VMA | (context << TLB_TAG_ACCESS_CONTEXT_SHIFT), %r1 |
136 | set VMA | (context << TLB_TAG_ACCESS_CONTEXT_SHIFT), %r1 |
137 | 137 | ||
138 | ! write DTLB tag |
138 | ! write DTLB tag |
139 | SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL) |
139 | SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL) |
140 | stxa %g1, [VA_DMMU_TAG_ACCESS] %asi |
140 | stxa %g1, [VA_DMMU_TAG_ACCESS] %asi |
141 | membar #Sync |
141 | membar #Sync |
142 | 142 | ||
143 | #ifdef CONFIG_VIRT_IDX_DCACHE |
143 | #ifdef CONFIG_VIRT_IDX_DCACHE |
144 | #define TTE_LOW_DATA(imm) (TTE_CP | TTE_CV | TTE_P | LMA | (imm)) |
144 | #define TTE_LOW_DATA(imm) (TTE_CP | TTE_CV | TTE_P | LMA | (imm)) |
145 | #else /* CONFIG_VIRT_IDX_DCACHE */ |
145 | #else /* CONFIG_VIRT_IDX_DCACHE */ |
146 | #define TTE_LOW_DATA(imm) (TTE_CP | TTE_P | LMA | (imm)) |
146 | #define TTE_LOW_DATA(imm) (TTE_CP | TTE_P | LMA | (imm)) |
147 | #endif /* CONFIG_VIRT_IDX_DCACHE */ |
147 | #endif /* CONFIG_VIRT_IDX_DCACHE */ |
148 | 148 | ||
149 | #define SET_TLB_DATA(r1, r2, imm) \ |
149 | #define SET_TLB_DATA(r1, r2, imm) \ |
150 | set TTE_LOW_DATA(imm), %r1; \ |
150 | set TTE_LOW_DATA(imm), %r1; \ |
151 | or %r1, %l5, %r1; \ |
151 | or %r1, %l5, %r1; \ |
152 | mov PAGESIZE_4M, %r2; \ |
152 | mov PAGESIZE_4M, %r2; \ |
153 | sllx %r2, TTE_SIZE_SHIFT, %r2; \ |
153 | sllx %r2, TTE_SIZE_SHIFT, %r2; \ |
154 | or %r1, %r2, %r1; \ |
154 | or %r1, %r2, %r1; \ |
155 | mov 1, %r2; \ |
155 | mov 1, %r2; \ |
156 | sllx %r2, TTE_V_SHIFT, %r2; \ |
156 | sllx %r2, TTE_V_SHIFT, %r2; \ |
157 | or %r1, %r2, %r1; |
157 | or %r1, %r2, %r1; |
158 | 158 | ||
159 | ! write DTLB data and install the kernel mapping |
159 | ! write DTLB data and install the kernel mapping |
160 | SET_TLB_DATA(g1, g2, TTE_L | TTE_W) ! use non-global mapping |
160 | SET_TLB_DATA(g1, g2, TTE_L | TTE_W) ! use non-global mapping |
161 | stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG |
161 | stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG |
162 | membar #Sync |
162 | membar #Sync |
163 | 163 | ||
164 | /* |
164 | /* |
165 | * Because we cannot use global mappings (because we want to have |
165 | * Because we cannot use global mappings (because we want to have |
166 | * separate 64-bit address spaces for both the kernel and the |
166 | * separate 64-bit address spaces for both the kernel and the |
167 | * userspace), we prepare the identity mapping also in context 1. This |
167 | * userspace), we prepare the identity mapping also in context 1. This |
168 | * step is required by the code installing the ITLB mapping. |
168 | * step is required by the code installing the ITLB mapping. |
169 | */ |
169 | */ |
170 | ! write DTLB tag of context 1 (i.e. MEM_CONTEXT_TEMP) |
170 | ! write DTLB tag of context 1 (i.e. MEM_CONTEXT_TEMP) |
171 | SET_TLB_TAG(g1, MEM_CONTEXT_TEMP) |
171 | SET_TLB_TAG(g1, MEM_CONTEXT_TEMP) |
172 | stxa %g1, [VA_DMMU_TAG_ACCESS] %asi |
172 | stxa %g1, [VA_DMMU_TAG_ACCESS] %asi |
173 | membar #Sync |
173 | membar #Sync |
174 | 174 | ||
175 | ! write DTLB data and install the kernel mapping in context 1 |
175 | ! write DTLB data and install the kernel mapping in context 1 |
176 | SET_TLB_DATA(g1, g2, TTE_W) ! use non-global mapping |
176 | SET_TLB_DATA(g1, g2, TTE_W) ! use non-global mapping |
177 | stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG |
177 | stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG |
178 | membar #Sync |
178 | membar #Sync |
179 | 179 | ||
180 | /* |
180 | /* |
181 | * Now is time to take over the IMMU. Unfortunatelly, it cannot be done |
181 | * Now is time to take over the IMMU. Unfortunatelly, it cannot be done |
182 | * as easily as the DMMU, because the IMMU is mapping the code it |
182 | * as easily as the DMMU, because the IMMU is mapping the code it |
183 | * executes. |
183 | * executes. |
184 | * |
184 | * |
185 | * [ Note that brave experiments with disabling the IMMU and using the |
185 | * [ Note that brave experiments with disabling the IMMU and using the |
186 | * DMMU approach failed after a dozen of desparate days with only little |
186 | * DMMU approach failed after a dozen of desparate days with only little |
187 | * success. ] |
187 | * success. ] |
188 | * |
188 | * |
189 | * The approach used here is inspired from OpenBSD. First, the kernel |
189 | * The approach used here is inspired from OpenBSD. First, the kernel |
190 | * creates IMMU mapping for itself in context 1 (MEM_CONTEXT_TEMP) and |
190 | * creates IMMU mapping for itself in context 1 (MEM_CONTEXT_TEMP) and |
191 | * switches to it. Context 0 (MEM_CONTEXT_KERNEL) can be demapped |
191 | * switches to it. Context 0 (MEM_CONTEXT_KERNEL) can be demapped |
192 | * afterwards and replaced with the kernel permanent mapping. Finally, |
192 | * afterwards and replaced with the kernel permanent mapping. Finally, |
193 | * the kernel switches back to context 0 and demaps context 1. |
193 | * the kernel switches back to context 0 and demaps context 1. |
194 | * |
194 | * |
195 | * Moreover, the IMMU requires use of the FLUSH instructions. But that |
195 | * Moreover, the IMMU requires use of the FLUSH instructions. But that |
196 | * is OK because we always use operands with addresses already mapped by |
196 | * is OK because we always use operands with addresses already mapped by |
197 | * the taken over DTLB. |
197 | * the taken over DTLB. |
198 | */ |
198 | */ |
199 | 199 | ||
200 | set kernel_image_start, %g5 |
200 | set kernel_image_start, %g5 |
201 | 201 | ||
202 | ! write ITLB tag of context 1 |
202 | ! write ITLB tag of context 1 |
203 | SET_TLB_TAG(g1, MEM_CONTEXT_TEMP) |
203 | SET_TLB_TAG(g1, MEM_CONTEXT_TEMP) |
204 | mov VA_DMMU_TAG_ACCESS, %g2 |
204 | mov VA_DMMU_TAG_ACCESS, %g2 |
205 | stxa %g1, [%g2] ASI_IMMU |
205 | stxa %g1, [%g2] ASI_IMMU |
206 | flush %g5 |
206 | flush %g5 |
207 | 207 | ||
208 | ! write ITLB data and install the temporary mapping in context 1 |
208 | ! write ITLB data and install the temporary mapping in context 1 |
209 | SET_TLB_DATA(g1, g2, 0) ! use non-global mapping |
209 | SET_TLB_DATA(g1, g2, 0) ! use non-global mapping |
210 | stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG |
210 | stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG |
211 | flush %g5 |
211 | flush %g5 |
212 | 212 | ||
213 | ! switch to context 1 |
213 | ! switch to context 1 |
214 | mov MEM_CONTEXT_TEMP, %g1 |
214 | mov MEM_CONTEXT_TEMP, %g1 |
215 | stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!! |
215 | stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!! |
216 | flush %g5 |
216 | flush %g5 |
217 | 217 | ||
218 | ! demap context 0 |
218 | ! demap context 0 |
219 | SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS) |
219 | SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS) |
220 | stxa %g0, [%g1] ASI_IMMU_DEMAP |
220 | stxa %g0, [%g1] ASI_IMMU_DEMAP |
221 | flush %g5 |
221 | flush %g5 |
222 | 222 | ||
223 | ! write ITLB tag of context 0 |
223 | ! write ITLB tag of context 0 |
224 | SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL) |
224 | SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL) |
225 | mov VA_DMMU_TAG_ACCESS, %g2 |
225 | mov VA_DMMU_TAG_ACCESS, %g2 |
226 | stxa %g1, [%g2] ASI_IMMU |
226 | stxa %g1, [%g2] ASI_IMMU |
227 | flush %g5 |
227 | flush %g5 |
228 | 228 | ||
229 | ! write ITLB data and install the permanent kernel mapping in context 0 |
229 | ! write ITLB data and install the permanent kernel mapping in context 0 |
230 | SET_TLB_DATA(g1, g2, TTE_L) ! use non-global mapping |
230 | SET_TLB_DATA(g1, g2, TTE_L) ! use non-global mapping |
231 | stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG |
231 | stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG |
232 | flush %g5 |
232 | flush %g5 |
233 | 233 | ||
234 | ! enter nucleus - using context 0 |
234 | ! enter nucleus - using context 0 |
235 | wrpr %g0, 1, %tl |
235 | wrpr %g0, 1, %tl |
236 | 236 | ||
237 | ! demap context 1 |
237 | ! demap context 1 |
238 | SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_PRIMARY) |
238 | SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_PRIMARY) |
239 | stxa %g0, [%g1] ASI_IMMU_DEMAP |
239 | stxa %g0, [%g1] ASI_IMMU_DEMAP |
240 | flush %g5 |
240 | flush %g5 |
241 | 241 | ||
242 | ! set context 0 in the primary context register |
242 | ! set context 0 in the primary context register |
243 | stxa %g0, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!! |
243 | stxa %g0, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!! |
244 | flush %g5 |
244 | flush %g5 |
245 | 245 | ||
246 | ! leave nucleus - using primary context, i.e. context 0 |
246 | ! leave nucleus - using primary context, i.e. context 0 |
247 | wrpr %g0, 0, %tl |
247 | wrpr %g0, 0, %tl |
248 | 248 | ||
249 | brz %l7, 1f ! skip if you are not the bootstrap CPU |
249 | brz %l7, 1f ! skip if you are not the bootstrap CPU |
250 | nop |
250 | nop |
251 | 251 | ||
252 | /* |
252 | /* |
253 | * Save physmem_base for use by the mm subsystem. |
253 | * Save physmem_base for use by the mm subsystem. |
254 | * %l6 contains starting physical address |
254 | * %l6 contains starting physical address |
255 | */ |
255 | */ |
256 | sethi %hi(physmem_base), %l4 |
256 | sethi %hi(physmem_base), %l4 |
257 | stx %l6, [%l4 + %lo(physmem_base)] |
257 | stx %l6, [%l4 + %lo(physmem_base)] |
258 | 258 | ||
259 | /* |
259 | /* |
260 | * Precompute kernel 8K TLB data template. |
260 | * Precompute kernel 8K TLB data template. |
261 | * %l5 contains starting physical address |
261 | * %l5 contains starting physical address |
262 | * bits [(PHYSMEM_ADDR_SIZE - 1):13] |
262 | * bits [(PHYSMEM_ADDR_SIZE - 1):13] |
263 | */ |
263 | */ |
264 | sethi %hi(kernel_8k_tlb_data_template), %l4 |
264 | sethi %hi(kernel_8k_tlb_data_template), %l4 |
265 | ldx [%l4 + %lo(kernel_8k_tlb_data_template)], %l3 |
265 | ldx [%l4 + %lo(kernel_8k_tlb_data_template)], %l3 |
266 | or %l3, %l5, %l3 |
266 | or %l3, %l5, %l3 |
267 | stx %l3, [%l4 + %lo(kernel_8k_tlb_data_template)] |
267 | stx %l3, [%l4 + %lo(kernel_8k_tlb_data_template)] |
268 | 268 | ||
269 | /* |
269 | /* |
270 | * Flush D-Cache. |
270 | * Flush D-Cache. |
271 | */ |
271 | */ |
272 | call dcache_flush |
272 | call dcache_flush |
273 | nop |
273 | nop |
274 | 274 | ||
275 | /* |
275 | /* |
276 | * So far, we have not touched the stack. |
276 | * So far, we have not touched the stack. |
277 | * It is a good idea to set the kernel stack to a known state now. |
277 | * It is a good idea to set the kernel stack to a known state now. |
278 | */ |
278 | */ |
279 | sethi %hi(temporary_boot_stack), %sp |
279 | sethi %hi(temporary_boot_stack), %sp |
280 | or %sp, %lo(temporary_boot_stack), %sp |
280 | or %sp, %lo(temporary_boot_stack), %sp |
281 | sub %sp, STACK_BIAS, %sp |
281 | sub %sp, STACK_BIAS, %sp |
282 | 282 | ||
283 | sethi %hi(bootinfo), %o0 |
283 | sethi %hi(bootinfo), %o0 |
284 | call memcpy ! copy bootinfo |
284 | call memcpy ! copy bootinfo |
285 | or %o0, %lo(bootinfo), %o0 |
285 | or %o0, %lo(bootinfo), %o0 |
286 | 286 | ||
287 | call arch_pre_main |
287 | call arch_pre_main |
288 | nop |
288 | nop |
289 | 289 | ||
290 | call main_bsp |
290 | call main_bsp |
291 | nop |
291 | nop |
292 | 292 | ||
293 | /* Not reached. */ |
293 | /* Not reached. */ |
294 | 294 | ||
295 | 0: |
295 | 0: |
296 | ba 0b |
296 | ba 0b |
297 | nop |
297 | nop |
298 | 298 | ||
299 | 299 | ||
300 | /* |
300 | /* |
301 | * Read MID from the processor. |
301 | * Read MID from the processor. |
302 | */ |
302 | */ |
303 | 1: |
303 | 1: |
304 | ldxa [%g0] ASI_ICBUS_CONFIG, %g1 |
304 | ldxa [%g0] ASI_ICBUS_CONFIG, %g1 |
305 | srlx %g1, ICBUS_CONFIG_MID_SHIFT, %g1 |
305 | srlx %g1, ICBUS_CONFIG_MID_SHIFT, %g1 |
306 | and %g1, ICBUS_CONFIG_MID_MASK, %g1 |
306 | and %g1, ICBUS_CONFIG_MID_MASK, %g1 |
307 | 307 | ||
308 | #ifdef CONFIG_SMP |
308 | #ifdef CONFIG_SMP |
309 | /* |
309 | /* |
310 | * Active loop for APs until the BSP picks them up. A processor cannot |
310 | * Active loop for APs until the BSP picks them up. A processor cannot |
311 | * leave the loop until the global variable 'waking_up_mid' equals its |
311 | * leave the loop until the global variable 'waking_up_mid' equals its |
312 | * MID. |
312 | * MID. |
313 | */ |
313 | */ |
314 | set waking_up_mid, %g2 |
314 | set waking_up_mid, %g2 |
315 | 2: |
315 | 2: |
316 | ldx [%g2], %g3 |
316 | ldx [%g2], %g3 |
317 | cmp %g3, %g1 |
317 | cmp %g3, %g1 |
318 | bne 2b |
318 | bne 2b |
319 | nop |
319 | nop |
320 | 320 | ||
321 | /* |
321 | /* |
322 | * Configure stack for the AP. |
322 | * Configure stack for the AP. |
323 | * The AP is expected to use the stack saved |
323 | * The AP is expected to use the stack saved |
324 | * in the ctx global variable. |
324 | * in the ctx global variable. |
325 | */ |
325 | */ |
326 | set ctx, %g1 |
326 | set ctx, %g1 |
327 | add %g1, OFFSET_SP, %g1 |
327 | add %g1, OFFSET_SP, %g1 |
328 | ldx [%g1], %o6 |
328 | ldx [%g1], %o6 |
329 | 329 | ||
330 | call main_ap |
330 | call main_ap |
331 | nop |
331 | nop |
332 | 332 | ||
333 | /* Not reached. */ |
333 | /* Not reached. */ |
334 | #endif |
334 | #endif |
335 | 335 | ||
336 | 0: |
336 | 0: |
337 | ba 0b |
337 | ba 0b |
338 | nop |
338 | nop |
339 | 339 | ||
340 | 340 | ||
341 | .section K_DATA_START, "aw", @progbits |
341 | .section K_DATA_START, "aw", @progbits |
342 | 342 | ||
343 | /* |
343 | /* |
344 | * Create small stack to be used by the bootstrap processor. It is going to be |
344 | * Create small stack to be used by the bootstrap processor. It is going to be |
345 | * used only for a very limited period of time, but we switch to it anyway, |
345 | * used only for a very limited period of time, but we switch to it anyway, |
346 | * just to be sure we are properly initialized. |
346 | * just to be sure we are properly initialized. |
347 | */ |
347 | */ |
348 | 348 | ||
349 | #define INITIAL_STACK_SIZE 1024 |
349 | #define INITIAL_STACK_SIZE 1024 |
350 | 350 | ||
351 | .align STACK_ALIGNMENT |
351 | .align STACK_ALIGNMENT |
352 | .space INITIAL_STACK_SIZE |
352 | .space INITIAL_STACK_SIZE |
353 | .align STACK_ALIGNMENT |
353 | .align STACK_ALIGNMENT |
354 | temporary_boot_stack: |
354 | temporary_boot_stack: |
355 | .space STACK_WINDOW_SAVE_AREA_SIZE |
355 | .space STACK_WINDOW_SAVE_AREA_SIZE |
356 | 356 | ||
357 | 357 | ||
358 | .data |
358 | .data |
359 | 359 | ||
360 | .align 8 |
360 | .align 8 |
361 | .global physmem_base ! copy of the physical memory base address |
361 | .global physmem_base ! copy of the physical memory base address |
362 | physmem_base: |
362 | physmem_base: |
363 | .quad 0 |
363 | .quad 0 |
364 | 364 | ||
365 | /* |
365 | /* |
366 | * This variable is used by the fast_data_MMU_miss trap handler. In runtime, it |
366 | * This variable is used by the fast_data_MMU_miss trap handler. In runtime, it |
367 | * is further modified to reflect the starting address of physical memory. |
367 | * is further modified to reflect the starting address of physical memory. |
368 | */ |
368 | */ |
369 | .global kernel_8k_tlb_data_template |
369 | .global kernel_8k_tlb_data_template |
370 | kernel_8k_tlb_data_template: |
370 | kernel_8k_tlb_data_template: |
371 | #ifdef CONFIG_VIRT_IDX_DCACHE |
371 | #ifdef CONFIG_VIRT_IDX_DCACHE |
372 | .quad ((1 << TTE_V_SHIFT) | (PAGESIZE_8K << TTE_SIZE_SHIFT) | TTE_CP | \ |
372 | .quad ((1 << TTE_V_SHIFT) | (PAGESIZE_8K << TTE_SIZE_SHIFT) | TTE_CP | \ |
373 | TTE_CV | TTE_P | TTE_W) |
373 | TTE_CV | TTE_P | TTE_W) |
374 | #else /* CONFIG_VIRT_IDX_DCACHE */ |
374 | #else /* CONFIG_VIRT_IDX_DCACHE */ |
375 | .quad ((1 << TTE_V_SHIFT) | (PAGESIZE_8K << TTE_SIZE_SHIFT) | TTE_CP | \ |
375 | .quad ((1 << TTE_V_SHIFT) | (PAGESIZE_8K << TTE_SIZE_SHIFT) | TTE_CP | \ |
376 | TTE_P | TTE_W) |
376 | TTE_P | TTE_W) |
377 | #endif /* CONFIG_VIRT_IDX_DCACHE */ |
377 | #endif /* CONFIG_VIRT_IDX_DCACHE */ |
378 | 378 | ||
379 | 379 |