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1 | /* |
1 | /* |
2 | * Copyright (c) 2005 Jakub Jermar |
2 | * Copyright (c) 2005 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup sparc64mm |
29 | /** @addtogroup sparc64mm |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | */ |
33 | */ |
34 | 34 | ||
35 | #include <arch/mm/tlb.h> |
35 | #include <arch/mm/tlb.h> |
36 | #include <mm/tlb.h> |
36 | #include <mm/tlb.h> |
37 | #include <mm/as.h> |
37 | #include <mm/as.h> |
38 | #include <mm/asid.h> |
38 | #include <mm/asid.h> |
39 | #include <arch/mm/frame.h> |
39 | #include <arch/mm/frame.h> |
40 | #include <arch/mm/page.h> |
40 | #include <arch/mm/page.h> |
41 | #include <arch/mm/mmu.h> |
41 | #include <arch/mm/mmu.h> |
42 | #include <arch/interrupt.h> |
42 | #include <arch/interrupt.h> |
43 | #include <interrupt.h> |
43 | #include <interrupt.h> |
44 | #include <arch.h> |
44 | #include <arch.h> |
45 | #include <print.h> |
45 | #include <print.h> |
46 | #include <arch/types.h> |
46 | #include <arch/types.h> |
47 | #include <config.h> |
47 | #include <config.h> |
48 | #include <arch/trap/trap.h> |
48 | #include <arch/trap/trap.h> |
49 | #include <arch/trap/exception.h> |
49 | #include <arch/trap/exception.h> |
50 | #include <panic.h> |
50 | #include <panic.h> |
51 | #include <arch/asm.h> |
51 | #include <arch/asm.h> |
52 | 52 | ||
53 | #ifdef CONFIG_TSB |
53 | #ifdef CONFIG_TSB |
54 | #include <arch/mm/tsb.h> |
54 | #include <arch/mm/tsb.h> |
55 | #endif |
55 | #endif |
56 | 56 | ||
57 | static void dtlb_pte_copy(pte_t *t, index_t index, bool ro); |
57 | static void dtlb_pte_copy(pte_t *t, index_t index, bool ro); |
58 | static void itlb_pte_copy(pte_t *t, index_t index); |
58 | static void itlb_pte_copy(pte_t *t, index_t index); |
59 | static void do_fast_instruction_access_mmu_miss_fault(istate_t *istate, |
59 | static void do_fast_instruction_access_mmu_miss_fault(istate_t *istate, |
60 | const char *str); |
60 | const char *str); |
61 | static void do_fast_data_access_mmu_miss_fault(istate_t *istate, |
61 | static void do_fast_data_access_mmu_miss_fault(istate_t *istate, |
62 | tlb_tag_access_reg_t tag, const char *str); |
62 | tlb_tag_access_reg_t tag, const char *str); |
63 | static void do_fast_data_access_protection_fault(istate_t *istate, |
63 | static void do_fast_data_access_protection_fault(istate_t *istate, |
64 | tlb_tag_access_reg_t tag, const char *str); |
64 | tlb_tag_access_reg_t tag, const char *str); |
65 | 65 | ||
66 | char *context_encoding[] = { |
66 | char *context_encoding[] = { |
67 | "Primary", |
67 | "Primary", |
68 | "Secondary", |
68 | "Secondary", |
69 | "Nucleus", |
69 | "Nucleus", |
70 | "Reserved" |
70 | "Reserved" |
71 | }; |
71 | }; |
72 | 72 | ||
73 | void tlb_arch_init(void) |
73 | void tlb_arch_init(void) |
74 | { |
74 | { |
75 | /* |
75 | /* |
76 | * Invalidate all non-locked DTLB and ITLB entries. |
76 | * Invalidate all non-locked DTLB and ITLB entries. |
77 | */ |
77 | */ |
78 | tlb_invalidate_all(); |
78 | tlb_invalidate_all(); |
79 | 79 | ||
80 | /* |
80 | /* |
81 | * Clear both SFSRs. |
81 | * Clear both SFSRs. |
82 | */ |
82 | */ |
83 | dtlb_sfsr_write(0); |
83 | dtlb_sfsr_write(0); |
84 | itlb_sfsr_write(0); |
84 | itlb_sfsr_write(0); |
85 | } |
85 | } |
86 | 86 | ||
87 | /** Insert privileged mapping into DMMU TLB. |
87 | /** Insert privileged mapping into DMMU TLB. |
88 | * |
88 | * |
89 | * @param page Virtual page address. |
89 | * @param page Virtual page address. |
90 | * @param frame Physical frame address. |
90 | * @param frame Physical frame address. |
91 | * @param pagesize Page size. |
91 | * @param pagesize Page size. |
92 | * @param locked True for permanent mappings, false otherwise. |
92 | * @param locked True for permanent mappings, false otherwise. |
93 | * @param cacheable True if the mapping is cacheable, false otherwise. |
93 | * @param cacheable True if the mapping is cacheable, false otherwise. |
94 | */ |
94 | */ |
95 | void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, |
95 | void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, |
96 | bool locked, bool cacheable) |
96 | bool locked, bool cacheable) |
97 | { |
97 | { |
98 | tlb_tag_access_reg_t tag; |
98 | tlb_tag_access_reg_t tag; |
99 | tlb_data_t data; |
99 | tlb_data_t data; |
100 | page_address_t pg; |
100 | page_address_t pg; |
101 | frame_address_t fr; |
101 | frame_address_t fr; |
102 | 102 | ||
103 | pg.address = page; |
103 | pg.address = page; |
104 | fr.address = frame; |
104 | fr.address = frame; |
105 | 105 | ||
106 | tag.context = ASID_KERNEL; |
106 | tag.context = ASID_KERNEL; |
107 | tag.vpn = pg.vpn; |
107 | tag.vpn = pg.vpn; |
108 | 108 | ||
109 | dtlb_tag_access_write(tag.value); |
109 | dtlb_tag_access_write(tag.value); |
110 | 110 | ||
111 | data.value = 0; |
111 | data.value = 0; |
112 | data.v = true; |
112 | data.v = true; |
113 | data.size = pagesize; |
113 | data.size = pagesize; |
114 | data.pfn = fr.pfn; |
114 | data.pfn = fr.pfn; |
115 | data.l = locked; |
115 | data.l = locked; |
116 | data.cp = cacheable; |
116 | data.cp = cacheable; |
117 | #ifdef CONFIG_VIRT_IDX_DCACHE |
117 | #ifdef CONFIG_VIRT_IDX_DCACHE |
118 | data.cv = cacheable; |
118 | data.cv = cacheable; |
119 | #endif /* CONFIG_VIRT_IDX_DCACHE */ |
119 | #endif /* CONFIG_VIRT_IDX_DCACHE */ |
120 | data.p = true; |
120 | data.p = true; |
121 | data.w = true; |
121 | data.w = true; |
122 | data.g = false; |
122 | data.g = false; |
123 | 123 | ||
124 | dtlb_data_in_write(data.value); |
124 | dtlb_data_in_write(data.value); |
125 | } |
125 | } |
126 | 126 | ||
127 | /** Copy PTE to TLB. |
127 | /** Copy PTE to TLB. |
128 | * |
128 | * |
129 | * @param t Page Table Entry to be copied. |
129 | * @param t Page Table Entry to be copied. |
130 | * @param index Zero if lower 8K-subpage, one if higher 8K-subpage. |
130 | * @param index Zero if lower 8K-subpage, one if higher 8K-subpage. |
131 | * @param ro If true, the entry will be created read-only, regardless of its |
131 | * @param ro If true, the entry will be created read-only, regardless of its |
132 | * w field. |
132 | * w field. |
133 | */ |
133 | */ |
134 | void dtlb_pte_copy(pte_t *t, index_t index, bool ro) |
134 | void dtlb_pte_copy(pte_t *t, index_t index, bool ro) |
135 | { |
135 | { |
136 | tlb_tag_access_reg_t tag; |
136 | tlb_tag_access_reg_t tag; |
137 | tlb_data_t data; |
137 | tlb_data_t data; |
138 | page_address_t pg; |
138 | page_address_t pg; |
139 | frame_address_t fr; |
139 | frame_address_t fr; |
140 | 140 | ||
141 | pg.address = t->page + (index << MMU_PAGE_WIDTH); |
141 | pg.address = t->page + (index << MMU_PAGE_WIDTH); |
142 | fr.address = t->frame + (index << MMU_PAGE_WIDTH); |
142 | fr.address = t->frame + (index << MMU_PAGE_WIDTH); |
143 | 143 | ||
144 | tag.value = 0; |
144 | tag.value = 0; |
145 | tag.context = t->as->asid; |
145 | tag.context = t->as->asid; |
146 | tag.vpn = pg.vpn; |
146 | tag.vpn = pg.vpn; |
147 | 147 | ||
148 | dtlb_tag_access_write(tag.value); |
148 | dtlb_tag_access_write(tag.value); |
149 | 149 | ||
150 | data.value = 0; |
150 | data.value = 0; |
151 | data.v = true; |
151 | data.v = true; |
152 | data.size = PAGESIZE_8K; |
152 | data.size = PAGESIZE_8K; |
153 | data.pfn = fr.pfn; |
153 | data.pfn = fr.pfn; |
154 | data.l = false; |
154 | data.l = false; |
155 | data.cp = t->c; |
155 | data.cp = t->c; |
156 | #ifdef CONFIG_VIRT_IDX_DCACHE |
156 | #ifdef CONFIG_VIRT_IDX_DCACHE |
157 | data.cv = t->c; |
157 | data.cv = t->c; |
158 | #endif /* CONFIG_VIRT_IDX_DCACHE */ |
158 | #endif /* CONFIG_VIRT_IDX_DCACHE */ |
159 | data.p = t->k; /* p like privileged */ |
159 | data.p = t->k; /* p like privileged */ |
160 | data.w = ro ? false : t->w; |
160 | data.w = ro ? false : t->w; |
161 | data.g = t->g; |
161 | data.g = t->g; |
162 | 162 | ||
163 | dtlb_data_in_write(data.value); |
163 | dtlb_data_in_write(data.value); |
164 | } |
164 | } |
165 | 165 | ||
166 | /** Copy PTE to ITLB. |
166 | /** Copy PTE to ITLB. |
167 | * |
167 | * |
168 | * @param t Page Table Entry to be copied. |
168 | * @param t Page Table Entry to be copied. |
169 | * @param index Zero if lower 8K-subpage, one if higher 8K-subpage. |
169 | * @param index Zero if lower 8K-subpage, one if higher 8K-subpage. |
170 | */ |
170 | */ |
171 | void itlb_pte_copy(pte_t *t, index_t index) |
171 | void itlb_pte_copy(pte_t *t, index_t index) |
172 | { |
172 | { |
173 | tlb_tag_access_reg_t tag; |
173 | tlb_tag_access_reg_t tag; |
174 | tlb_data_t data; |
174 | tlb_data_t data; |
175 | page_address_t pg; |
175 | page_address_t pg; |
176 | frame_address_t fr; |
176 | frame_address_t fr; |
177 | 177 | ||
178 | pg.address = t->page + (index << MMU_PAGE_WIDTH); |
178 | pg.address = t->page + (index << MMU_PAGE_WIDTH); |
179 | fr.address = t->frame + (index << MMU_PAGE_WIDTH); |
179 | fr.address = t->frame + (index << MMU_PAGE_WIDTH); |
180 | 180 | ||
181 | tag.value = 0; |
181 | tag.value = 0; |
182 | tag.context = t->as->asid; |
182 | tag.context = t->as->asid; |
183 | tag.vpn = pg.vpn; |
183 | tag.vpn = pg.vpn; |
184 | 184 | ||
185 | itlb_tag_access_write(tag.value); |
185 | itlb_tag_access_write(tag.value); |
186 | 186 | ||
187 | data.value = 0; |
187 | data.value = 0; |
188 | data.v = true; |
188 | data.v = true; |
189 | data.size = PAGESIZE_8K; |
189 | data.size = PAGESIZE_8K; |
190 | data.pfn = fr.pfn; |
190 | data.pfn = fr.pfn; |
191 | data.l = false; |
191 | data.l = false; |
192 | data.cp = t->c; |
192 | data.cp = t->c; |
193 | data.p = t->k; /* p like privileged */ |
193 | data.p = t->k; /* p like privileged */ |
194 | data.w = false; |
194 | data.w = false; |
195 | data.g = t->g; |
195 | data.g = t->g; |
196 | 196 | ||
197 | itlb_data_in_write(data.value); |
197 | itlb_data_in_write(data.value); |
198 | } |
198 | } |
199 | 199 | ||
200 | /** ITLB miss handler. */ |
200 | /** ITLB miss handler. */ |
201 | void fast_instruction_access_mmu_miss(unative_t unused, istate_t *istate) |
201 | void fast_instruction_access_mmu_miss(unative_t unused, istate_t *istate) |
202 | { |
202 | { |
203 | uintptr_t va = ALIGN_DOWN(istate->tpc, PAGE_SIZE); |
203 | uintptr_t va = ALIGN_DOWN(istate->tpc, PAGE_SIZE); |
204 | index_t index = (istate->tpc >> MMU_PAGE_WIDTH) % MMU_PAGES_PER_PAGE; |
204 | index_t index = (istate->tpc >> MMU_PAGE_WIDTH) % MMU_PAGES_PER_PAGE; |
205 | pte_t *t; |
205 | pte_t *t; |
206 | 206 | ||
207 | page_table_lock(AS, true); |
207 | page_table_lock(AS, true); |
208 | t = page_mapping_find(AS, va); |
208 | t = page_mapping_find(AS, va); |
209 | if (t && PTE_EXECUTABLE(t)) { |
209 | if (t && PTE_EXECUTABLE(t)) { |
210 | /* |
210 | /* |
211 | * The mapping was found in the software page hash table. |
211 | * The mapping was found in the software page hash table. |
212 | * Insert it into ITLB. |
212 | * Insert it into ITLB. |
213 | */ |
213 | */ |
214 | t->a = true; |
214 | t->a = true; |
215 | itlb_pte_copy(t, index); |
215 | itlb_pte_copy(t, index); |
216 | #ifdef CONFIG_TSB |
216 | #ifdef CONFIG_TSB |
217 | itsb_pte_copy(t, index); |
217 | itsb_pte_copy(t, index); |
218 | #endif |
218 | #endif |
219 | page_table_unlock(AS, true); |
219 | page_table_unlock(AS, true); |
220 | } else { |
220 | } else { |
221 | /* |
221 | /* |
222 | * Forward the page fault to the address space page fault |
222 | * Forward the page fault to the address space page fault |
223 | * handler. |
223 | * handler. |
224 | */ |
224 | */ |
225 | page_table_unlock(AS, true); |
225 | page_table_unlock(AS, true); |
226 | if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) { |
226 | if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) { |
227 | do_fast_instruction_access_mmu_miss_fault(istate, |
227 | do_fast_instruction_access_mmu_miss_fault(istate, |
228 | __func__); |
228 | __func__); |
229 | } |
229 | } |
230 | } |
230 | } |
231 | } |
231 | } |
232 | 232 | ||
233 | /** DTLB miss handler. |
233 | /** DTLB miss handler. |
234 | * |
234 | * |
235 | * Note that some faults (e.g. kernel faults) were already resolved by the |
235 | * Note that some faults (e.g. kernel faults) were already resolved by the |
236 | * low-level, assembly language part of the fast_data_access_mmu_miss handler. |
236 | * low-level, assembly language part of the fast_data_access_mmu_miss handler. |
237 | * |
237 | * |
238 | * @param tag Content of the TLB Tag Access register as it existed when the |
238 | * @param tag Content of the TLB Tag Access register as it existed when the |
239 | * trap happened. This is to prevent confusion created by clobbered |
239 | * trap happened. This is to prevent confusion created by clobbered |
240 | * Tag Access register during a nested DTLB miss. |
240 | * Tag Access register during a nested DTLB miss. |
241 | * @param istate Interrupted state saved on the stack. |
241 | * @param istate Interrupted state saved on the stack. |
242 | */ |
242 | */ |
243 | void fast_data_access_mmu_miss(tlb_tag_access_reg_t tag, istate_t *istate) |
243 | void fast_data_access_mmu_miss(tlb_tag_access_reg_t tag, istate_t *istate) |
244 | { |
244 | { |
245 | uintptr_t va; |
245 | uintptr_t va; |
246 | index_t index; |
246 | index_t index; |
247 | pte_t *t; |
247 | pte_t *t; |
248 | 248 | ||
249 | va = ALIGN_DOWN((uint64_t) tag.vpn << MMU_PAGE_WIDTH, PAGE_SIZE); |
249 | va = ALIGN_DOWN((uint64_t) tag.vpn << MMU_PAGE_WIDTH, PAGE_SIZE); |
250 | index = tag.vpn % MMU_PAGES_PER_PAGE; |
250 | index = tag.vpn % MMU_PAGES_PER_PAGE; |
251 | 251 | ||
252 | if (tag.context == ASID_KERNEL) { |
252 | if (tag.context == ASID_KERNEL) { |
253 | if (!tag.vpn) { |
253 | if (!tag.vpn) { |
254 | /* NULL access in kernel */ |
254 | /* NULL access in kernel */ |
255 | do_fast_data_access_mmu_miss_fault(istate, tag, |
255 | do_fast_data_access_mmu_miss_fault(istate, tag, |
256 | __func__); |
256 | __func__); |
257 | } |
257 | } |
258 | do_fast_data_access_mmu_miss_fault(istate, tag, "Unexpected " |
258 | do_fast_data_access_mmu_miss_fault(istate, tag, "Unexpected " |
259 | "kernel page fault."); |
259 | "kernel page fault."); |
260 | } |
260 | } |
261 | 261 | ||
262 | page_table_lock(AS, true); |
262 | page_table_lock(AS, true); |
263 | t = page_mapping_find(AS, va); |
263 | t = page_mapping_find(AS, va); |
264 | if (t) { |
264 | if (t) { |
265 | /* |
265 | /* |
266 | * The mapping was found in the software page hash table. |
266 | * The mapping was found in the software page hash table. |
267 | * Insert it into DTLB. |
267 | * Insert it into DTLB. |
268 | */ |
268 | */ |
269 | t->a = true; |
269 | t->a = true; |
270 | dtlb_pte_copy(t, index, true); |
270 | dtlb_pte_copy(t, index, true); |
271 | #ifdef CONFIG_TSB |
271 | #ifdef CONFIG_TSB |
272 | dtsb_pte_copy(t, index, true); |
272 | dtsb_pte_copy(t, index, true); |
273 | #endif |
273 | #endif |
274 | page_table_unlock(AS, true); |
274 | page_table_unlock(AS, true); |
275 | } else { |
275 | } else { |
276 | /* |
276 | /* |
277 | * Forward the page fault to the address space page fault |
277 | * Forward the page fault to the address space page fault |
278 | * handler. |
278 | * handler. |
279 | */ |
279 | */ |
280 | page_table_unlock(AS, true); |
280 | page_table_unlock(AS, true); |
281 | if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) { |
281 | if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) { |
282 | do_fast_data_access_mmu_miss_fault(istate, tag, |
282 | do_fast_data_access_mmu_miss_fault(istate, tag, |
283 | __func__); |
283 | __func__); |
284 | } |
284 | } |
285 | } |
285 | } |
286 | } |
286 | } |
287 | 287 | ||
288 | /** DTLB protection fault handler. |
288 | /** DTLB protection fault handler. |
289 | * |
289 | * |
290 | * @param tag Content of the TLB Tag Access register as it existed when the |
290 | * @param tag Content of the TLB Tag Access register as it existed when the |
291 | * trap happened. This is to prevent confusion created by clobbered |
291 | * trap happened. This is to prevent confusion created by clobbered |
292 | * Tag Access register during a nested DTLB miss. |
292 | * Tag Access register during a nested DTLB miss. |
293 | * @param istate Interrupted state saved on the stack. |
293 | * @param istate Interrupted state saved on the stack. |
294 | */ |
294 | */ |
295 | void fast_data_access_protection(tlb_tag_access_reg_t tag, istate_t *istate) |
295 | void fast_data_access_protection(tlb_tag_access_reg_t tag, istate_t *istate) |
296 | { |
296 | { |
297 | uintptr_t va; |
297 | uintptr_t va; |
298 | index_t index; |
298 | index_t index; |
299 | pte_t *t; |
299 | pte_t *t; |
300 | 300 | ||
301 | va = ALIGN_DOWN((uint64_t) tag.vpn << MMU_PAGE_WIDTH, PAGE_SIZE); |
301 | va = ALIGN_DOWN((uint64_t) tag.vpn << MMU_PAGE_WIDTH, PAGE_SIZE); |
302 | index = tag.vpn % MMU_PAGES_PER_PAGE; /* 16K-page emulation */ |
302 | index = tag.vpn % MMU_PAGES_PER_PAGE; /* 16K-page emulation */ |
303 | 303 | ||
304 | page_table_lock(AS, true); |
304 | page_table_lock(AS, true); |
305 | t = page_mapping_find(AS, va); |
305 | t = page_mapping_find(AS, va); |
306 | if (t && PTE_WRITABLE(t)) { |
306 | if (t && PTE_WRITABLE(t)) { |
307 | /* |
307 | /* |
308 | * The mapping was found in the software page hash table and is |
308 | * The mapping was found in the software page hash table and is |
309 | * writable. Demap the old mapping and insert an updated mapping |
309 | * writable. Demap the old mapping and insert an updated mapping |
310 | * into DTLB. |
310 | * into DTLB. |
311 | */ |
311 | */ |
312 | t->a = true; |
312 | t->a = true; |
313 | t->d = true; |
313 | t->d = true; |
314 | dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_SECONDARY, |
314 | dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_SECONDARY, |
315 | va + index * MMU_PAGE_SIZE); |
315 | va + index * MMU_PAGE_SIZE); |
316 | dtlb_pte_copy(t, index, false); |
316 | dtlb_pte_copy(t, index, false); |
317 | #ifdef CONFIG_TSB |
317 | #ifdef CONFIG_TSB |
318 | dtsb_pte_copy(t, index, false); |
318 | dtsb_pte_copy(t, index, false); |
319 | #endif |
319 | #endif |
320 | page_table_unlock(AS, true); |
320 | page_table_unlock(AS, true); |
321 | } else { |
321 | } else { |
322 | /* |
322 | /* |
323 | * Forward the page fault to the address space page fault |
323 | * Forward the page fault to the address space page fault |
324 | * handler. |
324 | * handler. |
325 | */ |
325 | */ |
326 | page_table_unlock(AS, true); |
326 | page_table_unlock(AS, true); |
327 | if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) { |
327 | if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) { |
328 | do_fast_data_access_protection_fault(istate, tag, |
328 | do_fast_data_access_protection_fault(istate, tag, |
329 | __func__); |
329 | __func__); |
330 | } |
330 | } |
331 | } |
331 | } |
332 | } |
332 | } |
333 | 333 | ||
334 | /** Print TLB entry (for debugging purposes). |
334 | /** Print TLB entry (for debugging purposes). |
335 | * |
335 | * |
336 | * The diag field has been left out in order to make this function more generic |
336 | * The diag field has been left out in order to make this function more generic |
337 | * (there is no diag field in US3 architeture). |
337 | * (there is no diag field in US3 architeture). |
338 | * |
338 | * |
339 | * @param i TLB entry number |
339 | * @param i TLB entry number |
340 | * @param t TLB entry tag |
340 | * @param t TLB entry tag |
341 | * @param d TLB entry data |
341 | * @param d TLB entry data |
342 | */ |
342 | */ |
343 | static void print_tlb_entry(int i, tlb_tag_read_reg_t t, tlb_data_t d) |
343 | static void print_tlb_entry(int i, tlb_tag_read_reg_t t, tlb_data_t d) |
344 | { |
344 | { |
345 | printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, " |
345 | printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, " |
346 | "ie=%d, soft2=%#x, pfn=%#x, soft=%#x, l=%d, " |
346 | "ie=%d, soft2=%#x, pfn=%#x, soft=%#x, l=%d, " |
347 | "cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", i, t.vpn, |
347 | "cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", i, t.vpn, |
348 | t.context, d.v, d.size, d.nfo, d.ie, d.soft2, |
348 | t.context, d.v, d.size, d.nfo, d.ie, d.soft2, |
349 | d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g); |
349 | d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g); |
350 | } |
350 | } |
351 | 351 | ||
352 | #if defined (US) |
352 | #if defined (US) |
353 | 353 | ||
354 | /** Print contents of both TLBs. */ |
354 | /** Print contents of both TLBs. */ |
355 | void tlb_print(void) |
355 | void tlb_print(void) |
356 | { |
356 | { |
357 | int i; |
357 | int i; |
358 | tlb_data_t d; |
358 | tlb_data_t d; |
359 | tlb_tag_read_reg_t t; |
359 | tlb_tag_read_reg_t t; |
360 | 360 | ||
361 | printf("I-TLB contents:\n"); |
361 | printf("I-TLB contents:\n"); |
362 | for (i = 0; i < ITLB_ENTRY_COUNT; i++) { |
362 | for (i = 0; i < ITLB_ENTRY_COUNT; i++) { |
363 | d.value = itlb_data_access_read(i); |
363 | d.value = itlb_data_access_read(i); |
364 | t.value = itlb_tag_read_read(i); |
364 | t.value = itlb_tag_read_read(i); |
365 | print_tlb_entry(i, t, d); |
365 | print_tlb_entry(i, t, d); |
366 | } |
366 | } |
367 | 367 | ||
368 | printf("D-TLB contents:\n"); |
368 | printf("D-TLB contents:\n"); |
369 | for (i = 0; i < DTLB_ENTRY_COUNT; i++) { |
369 | for (i = 0; i < DTLB_ENTRY_COUNT; i++) { |
370 | d.value = dtlb_data_access_read(i); |
370 | d.value = dtlb_data_access_read(i); |
371 | t.value = dtlb_tag_read_read(i); |
371 | t.value = dtlb_tag_read_read(i); |
372 | print_tlb_entry(i, t, d); |
372 | print_tlb_entry(i, t, d); |
373 | } |
373 | } |
374 | } |
374 | } |
375 | 375 | ||
376 | #elif defined (US3) |
376 | #elif defined (US3) |
377 | 377 | ||
378 | /** Print contents of all TLBs. */ |
378 | /** Print contents of all TLBs. */ |
379 | void tlb_print(void) |
379 | void tlb_print(void) |
380 | { |
380 | { |
381 | int i; |
381 | int i; |
382 | tlb_data_t d; |
382 | tlb_data_t d; |
383 | tlb_tag_read_reg_t t; |
383 | tlb_tag_read_reg_t t; |
384 | 384 | ||
385 | printf("IT16 contents:\n"); |
385 | printf("TLB_ISMALL contents:\n"); |
386 | for (i = 0; i < 16; i++) { |
386 | for (i = 0; i < tlb_ismall_size(); i++) { |
387 | d.value = dtlb_data_access_read(TLB_IT16, i); |
387 | d.value = dtlb_data_access_read(TLB_ISMALL, i); |
388 | t.value = dtlb_tag_read_read(TLB_IT16, i); |
388 | t.value = dtlb_tag_read_read(TLB_ISMALL, i); |
389 | print_tlb_entry(i, t, d); |
389 | print_tlb_entry(i, t, d); |
390 | } |
390 | } |
391 | 391 | ||
392 | printf("IT128 contents:\n"); |
392 | printf("TLB_IBIG contents:\n"); |
393 | for (i = 0; i < 128; i++) { |
393 | for (i = 0; i < tlb_ibig_size(); i++) { |
394 | d.value = dtlb_data_access_read(TLB_IT128, i); |
394 | d.value = dtlb_data_access_read(TLB_IBIG, i); |
395 | t.value = dtlb_tag_read_read(TLB_IT128, i); |
395 | t.value = dtlb_tag_read_read(TLB_IBIG, i); |
396 | print_tlb_entry(i, t, d); |
396 | print_tlb_entry(i, t, d); |
397 | } |
397 | } |
398 | 398 | ||
399 | printf("DT16 contents:\n"); |
399 | printf("TLB_DSMALL contents:\n"); |
400 | for (i = 0; i < 16; i++) { |
400 | for (i = 0; i < tlb_dsmall_size(); i++) { |
401 | d.value = dtlb_data_access_read(TLB_DT16, i); |
401 | d.value = dtlb_data_access_read(TLB_DSMALL, i); |
402 | t.value = dtlb_tag_read_read(TLB_DT16, i); |
402 | t.value = dtlb_tag_read_read(TLB_DSMALL, i); |
403 | print_tlb_entry(i, t, d); |
403 | print_tlb_entry(i, t, d); |
404 | } |
404 | } |
405 | 405 | ||
406 | printf("DT512_1 contents:\n"); |
406 | printf("TLB_DBIG_1 contents:\n"); |
407 | for (i = 0; i < 512; i++) { |
407 | for (i = 0; i < tlb_dbig_size(); i++) { |
408 | d.value = dtlb_data_access_read(TLB_DT512_0, i); |
408 | d.value = dtlb_data_access_read(TLB_DBIG_0, i); |
409 | t.value = dtlb_tag_read_read(TLB_DT512_0, i); |
409 | t.value = dtlb_tag_read_read(TLB_DBIG_0, i); |
410 | print_tlb_entry(i, t, d); |
410 | print_tlb_entry(i, t, d); |
411 | } |
411 | } |
412 | 412 | ||
413 | printf("DT512_2 contents:\n"); |
413 | printf("TLB_DBIG_2 contents:\n"); |
414 | for (i = 0; i < 512; i++) { |
414 | for (i = 0; i < tlb_dbig_size(); i++) { |
415 | d.value = dtlb_data_access_read(TLB_DT512_1, i); |
415 | d.value = dtlb_data_access_read(TLB_DBIG_1, i); |
416 | t.value = dtlb_tag_read_read(TLB_DT512_1, i); |
416 | t.value = dtlb_tag_read_read(TLB_DBIG_1, i); |
417 | print_tlb_entry(i, t, d); |
417 | print_tlb_entry(i, t, d); |
418 | } |
418 | } |
419 | } |
419 | } |
420 | 420 | ||
421 | #endif |
421 | #endif |
422 | 422 | ||
423 | void do_fast_instruction_access_mmu_miss_fault(istate_t *istate, |
423 | void do_fast_instruction_access_mmu_miss_fault(istate_t *istate, |
424 | const char *str) |
424 | const char *str) |
425 | { |
425 | { |
426 | fault_if_from_uspace(istate, "%s\n", str); |
426 | fault_if_from_uspace(istate, "%s\n", str); |
427 | dump_istate(istate); |
427 | dump_istate(istate); |
428 | panic("%s\n", str); |
428 | panic("%s\n", str); |
429 | } |
429 | } |
430 | 430 | ||
431 | void do_fast_data_access_mmu_miss_fault(istate_t *istate, |
431 | void do_fast_data_access_mmu_miss_fault(istate_t *istate, |
432 | tlb_tag_access_reg_t tag, const char *str) |
432 | tlb_tag_access_reg_t tag, const char *str) |
433 | { |
433 | { |
434 | uintptr_t va; |
434 | uintptr_t va; |
435 | 435 | ||
436 | va = tag.vpn << MMU_PAGE_WIDTH; |
436 | va = tag.vpn << MMU_PAGE_WIDTH; |
437 | if (tag.context) { |
437 | if (tag.context) { |
438 | fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va, |
438 | fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va, |
439 | tag.context); |
439 | tag.context); |
440 | } |
440 | } |
441 | dump_istate(istate); |
441 | dump_istate(istate); |
442 | printf("Faulting page: %p, ASID=%d\n", va, tag.context); |
442 | printf("Faulting page: %p, ASID=%d\n", va, tag.context); |
443 | panic("%s\n", str); |
443 | panic("%s\n", str); |
444 | } |
444 | } |
445 | 445 | ||
446 | void do_fast_data_access_protection_fault(istate_t *istate, |
446 | void do_fast_data_access_protection_fault(istate_t *istate, |
447 | tlb_tag_access_reg_t tag, const char *str) |
447 | tlb_tag_access_reg_t tag, const char *str) |
448 | { |
448 | { |
449 | uintptr_t va; |
449 | uintptr_t va; |
450 | 450 | ||
451 | va = tag.vpn << MMU_PAGE_WIDTH; |
451 | va = tag.vpn << MMU_PAGE_WIDTH; |
452 | 452 | ||
453 | if (tag.context) { |
453 | if (tag.context) { |
454 | fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va, |
454 | fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va, |
455 | tag.context); |
455 | tag.context); |
456 | } |
456 | } |
457 | printf("Faulting page: %p, ASID=%d\n", va, tag.context); |
457 | printf("Faulting page: %p, ASID=%d\n", va, tag.context); |
458 | dump_istate(istate); |
458 | dump_istate(istate); |
459 | panic("%s\n", str); |
459 | panic("%s\n", str); |
460 | } |
460 | } |
461 | 461 | ||
462 | void dump_sfsr_and_sfar(void) |
462 | void dump_sfsr_and_sfar(void) |
463 | { |
463 | { |
464 | tlb_sfsr_reg_t sfsr; |
464 | tlb_sfsr_reg_t sfsr; |
465 | uintptr_t sfar; |
465 | uintptr_t sfar; |
466 | 466 | ||
467 | sfsr.value = dtlb_sfsr_read(); |
467 | sfsr.value = dtlb_sfsr_read(); |
468 | sfar = dtlb_sfar_read(); |
468 | sfar = dtlb_sfar_read(); |
469 | 469 | ||
470 | #if defined (US) |
470 | #if defined (US) |
471 | printf("DTLB SFSR: asi=%#x, ft=%#x, e=%d, ct=%d, pr=%d, w=%d, ow=%d, " |
471 | printf("DTLB SFSR: asi=%#x, ft=%#x, e=%d, ct=%d, pr=%d, w=%d, ow=%d, " |
472 | "fv=%d\n", sfsr.asi, sfsr.ft, sfsr.e, sfsr.ct, sfsr.pr, sfsr.w, |
472 | "fv=%d\n", sfsr.asi, sfsr.ft, sfsr.e, sfsr.ct, sfsr.pr, sfsr.w, |
473 | sfsr.ow, sfsr.fv); |
473 | sfsr.ow, sfsr.fv); |
474 | #elif defined (US3) |
474 | #elif defined (US3) |
475 | printf("DTLB SFSR: nf=%d, asi=%#x, tm=%d, ft=%#x, e=%d, ct=%d, pr=%d, w=%d, ow=%d, " |
475 | printf("DTLB SFSR: nf=%d, asi=%#x, tm=%d, ft=%#x, e=%d, ct=%d, pr=%d, w=%d, ow=%d, " |
476 | "fv=%d\n", sfsr.nf, sfsr.asi, sfsr.tm, sfsr.ft, sfsr.e, sfsr.ct, sfsr.pr, sfsr.w, |
476 | "fv=%d\n", sfsr.nf, sfsr.asi, sfsr.tm, sfsr.ft, sfsr.e, sfsr.ct, sfsr.pr, sfsr.w, |
477 | sfsr.ow, sfsr.fv); |
477 | sfsr.ow, sfsr.fv); |
478 | #endif |
478 | #endif |
479 | 479 | ||
480 | printf("DTLB SFAR: address=%p\n", sfar); |
480 | printf("DTLB SFAR: address=%p\n", sfar); |
481 | 481 | ||
482 | dtlb_sfsr_write(0); |
482 | dtlb_sfsr_write(0); |
483 | } |
483 | } |
484 | 484 | ||
485 | #if defined (US3) |
485 | #if defined (US3) |
486 | /** Invalidates given TLB entry if and only if it is non-locked or global. |
486 | /** Invalidates given TLB entry if and only if it is non-locked or global. |
487 | * |
487 | * |
488 | * @param tlb |
488 | * @param tlb |
489 | * TLB number (one of TLB_DT16, TLB_DT512_0, TLB_DT512_1, |
489 | * TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1, |
490 | * TLB_IT16, TLB_IT128) |
490 | * TLB_ISMALL, TLB_IBIG) |
491 | * @param entry entry index within the given TLB |
491 | * @param entry entry index within the given TLB |
492 | */ |
492 | */ |
493 | static void tlb_invalidate_entry(int tlb, index_t entry) |
493 | static void tlb_invalidate_entry(int tlb, index_t entry) |
494 | { |
494 | { |
495 | tlb_data_t d; |
495 | tlb_data_t d; |
496 | tlb_tag_read_reg_t t; |
496 | tlb_tag_read_reg_t t; |
497 | 497 | ||
498 | if (tlb == TLB_DT16 || tlb == TLB_DT512_0 || tlb == TLB_DT512_1) { |
498 | if (tlb == TLB_DSMALL || tlb == TLB_DBIG_0 || tlb == TLB_DBIG_1) { |
499 | d.value = dtlb_data_access_read(tlb, entry); |
499 | d.value = dtlb_data_access_read(tlb, entry); |
500 | if (!d.l || d.g) { |
500 | if (!d.l || d.g) { |
501 | t.value = dtlb_tag_read_read(tlb, entry); |
501 | t.value = dtlb_tag_read_read(tlb, entry); |
502 | d.v = false; |
502 | d.v = false; |
503 | dtlb_tag_access_write(t.value); |
503 | dtlb_tag_access_write(t.value); |
504 | dtlb_data_access_write(tlb, entry, d.value); |
504 | dtlb_data_access_write(tlb, entry, d.value); |
505 | } |
505 | } |
506 | } else if (tlb == TLB_IT16 || tlb == TLB_IT128) { |
506 | } else if (tlb == TLB_ISMALL || tlb == TLB_IBIG) { |
507 | d.value = itlb_data_access_read(tlb, entry); |
507 | d.value = itlb_data_access_read(tlb, entry); |
508 | if (!d.l || d.g) { |
508 | if (!d.l || d.g) { |
509 | t.value = itlb_tag_read_read(tlb, entry); |
509 | t.value = itlb_tag_read_read(tlb, entry); |
510 | d.v = false; |
510 | d.v = false; |
511 | itlb_tag_access_write(t.value); |
511 | itlb_tag_access_write(t.value); |
512 | itlb_data_access_write(tlb, entry, d.value); |
512 | itlb_data_access_write(tlb, entry, d.value); |
513 | } |
513 | } |
514 | } |
514 | } |
515 | } |
515 | } |
516 | #endif |
516 | #endif |
517 | 517 | ||
518 | /** Invalidate all unlocked ITLB and DTLB entries. */ |
518 | /** Invalidate all unlocked ITLB and DTLB entries. */ |
519 | void tlb_invalidate_all(void) |
519 | void tlb_invalidate_all(void) |
520 | { |
520 | { |
521 | int i; |
521 | int i; |
522 | 522 | ||
523 | /* |
523 | /* |
524 | * Walk all ITLB and DTLB entries and remove all unlocked mappings. |
524 | * Walk all ITLB and DTLB entries and remove all unlocked mappings. |
525 | * |
525 | * |
526 | * The kernel doesn't use global mappings so any locked global mappings |
526 | * The kernel doesn't use global mappings so any locked global mappings |
527 | * found must have been created by someone else. Their only purpose now |
527 | * found must have been created by someone else. Their only purpose now |
528 | * is to collide with proper mappings. Invalidate immediately. It should |
528 | * is to collide with proper mappings. Invalidate immediately. It should |
529 | * be safe to invalidate them as late as now. |
529 | * be safe to invalidate them as late as now. |
530 | */ |
530 | */ |
531 | 531 | ||
532 | #if defined (US) |
532 | #if defined (US) |
533 | tlb_data_t d; |
533 | tlb_data_t d; |
534 | tlb_tag_read_reg_t t; |
534 | tlb_tag_read_reg_t t; |
535 | 535 | ||
536 | for (i = 0; i < ITLB_ENTRY_COUNT; i++) { |
536 | for (i = 0; i < ITLB_ENTRY_COUNT; i++) { |
537 | d.value = itlb_data_access_read(i); |
537 | d.value = itlb_data_access_read(i); |
538 | if (!d.l || d.g) { |
538 | if (!d.l || d.g) { |
539 | t.value = itlb_tag_read_read(i); |
539 | t.value = itlb_tag_read_read(i); |
540 | d.v = false; |
540 | d.v = false; |
541 | itlb_tag_access_write(t.value); |
541 | itlb_tag_access_write(t.value); |
542 | itlb_data_access_write(i, d.value); |
542 | itlb_data_access_write(i, d.value); |
543 | } |
543 | } |
544 | } |
544 | } |
545 | 545 | ||
546 | for (i = 0; i < DTLB_ENTRY_COUNT; i++) { |
546 | for (i = 0; i < DTLB_ENTRY_COUNT; i++) { |
547 | d.value = dtlb_data_access_read(i); |
547 | d.value = dtlb_data_access_read(i); |
548 | if (!d.l || d.g) { |
548 | if (!d.l || d.g) { |
549 | t.value = dtlb_tag_read_read(i); |
549 | t.value = dtlb_tag_read_read(i); |
550 | d.v = false; |
550 | d.v = false; |
551 | dtlb_tag_access_write(t.value); |
551 | dtlb_tag_access_write(t.value); |
552 | dtlb_data_access_write(i, d.value); |
552 | dtlb_data_access_write(i, d.value); |
553 | } |
553 | } |
554 | } |
554 | } |
555 | 555 | ||
556 | #elif defined (US3) |
556 | #elif defined (US3) |
557 | 557 | ||
558 | for (i = 0; i < 16; i++) |
558 | for (i = 0; i < tlb_ismall_size(); i++) |
559 | tlb_invalidate_entry(TLB_IT16, i); |
559 | tlb_invalidate_entry(TLB_ISMALL, i); |
560 | for (i = 0; i < 128; i++) |
560 | for (i = 0; i < tlb_ibig_size(); i++) |
561 | tlb_invalidate_entry(TLB_IT128, i); |
561 | tlb_invalidate_entry(TLB_IBIG, i); |
562 | for (i = 0; i < 16; i++) |
562 | for (i = 0; i < tlb_dsmall_size(); i++) |
563 | tlb_invalidate_entry(TLB_DT16, i); |
563 | tlb_invalidate_entry(TLB_DSMALL, i); |
564 | for (i = 0; i < 512; i++) |
564 | for (i = 0; i < tlb_dbig_size(); i++) |
565 | tlb_invalidate_entry(TLB_DT512_0, i); |
565 | tlb_invalidate_entry(TLB_DBIG_0, i); |
566 | for (i = 0; i < 512; i++) |
566 | for (i = 0; i < tlb_dbig_size(); i++) |
567 | tlb_invalidate_entry(TLB_DT512_1, i); |
567 | tlb_invalidate_entry(TLB_DBIG_1, i); |
568 | #endif |
568 | #endif |
569 | 569 | ||
570 | } |
570 | } |
571 | 571 | ||
572 | /** Invalidate all ITLB and DTLB entries that belong to specified ASID |
572 | /** Invalidate all ITLB and DTLB entries that belong to specified ASID |
573 | * (Context). |
573 | * (Context). |
574 | * |
574 | * |
575 | * @param asid Address Space ID. |
575 | * @param asid Address Space ID. |
576 | */ |
576 | */ |
577 | void tlb_invalidate_asid(asid_t asid) |
577 | void tlb_invalidate_asid(asid_t asid) |
578 | { |
578 | { |
579 | tlb_context_reg_t pc_save, ctx; |
579 | tlb_context_reg_t pc_save, ctx; |
580 | 580 | ||
581 | /* switch to nucleus because we are mapped by the primary context */ |
581 | /* switch to nucleus because we are mapped by the primary context */ |
582 | nucleus_enter(); |
582 | nucleus_enter(); |
583 | 583 | ||
584 | ctx.v = pc_save.v = mmu_primary_context_read(); |
584 | ctx.v = pc_save.v = mmu_primary_context_read(); |
585 | ctx.context = asid; |
585 | ctx.context = asid; |
586 | mmu_primary_context_write(ctx.v); |
586 | mmu_primary_context_write(ctx.v); |
587 | 587 | ||
588 | itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0); |
588 | itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0); |
589 | dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0); |
589 | dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0); |
590 | 590 | ||
591 | mmu_primary_context_write(pc_save.v); |
591 | mmu_primary_context_write(pc_save.v); |
592 | 592 | ||
593 | nucleus_leave(); |
593 | nucleus_leave(); |
594 | } |
594 | } |
595 | 595 | ||
596 | /** Invalidate all ITLB and DTLB entries for specified page range in specified |
596 | /** Invalidate all ITLB and DTLB entries for specified page range in specified |
597 | * address space. |
597 | * address space. |
598 | * |
598 | * |
599 | * @param asid Address Space ID. |
599 | * @param asid Address Space ID. |
600 | * @param page First page which to sweep out from ITLB and DTLB. |
600 | * @param page First page which to sweep out from ITLB and DTLB. |
601 | * @param cnt Number of ITLB and DTLB entries to invalidate. |
601 | * @param cnt Number of ITLB and DTLB entries to invalidate. |
602 | */ |
602 | */ |
603 | void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt) |
603 | void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt) |
604 | { |
604 | { |
605 | unsigned int i; |
605 | unsigned int i; |
606 | tlb_context_reg_t pc_save, ctx; |
606 | tlb_context_reg_t pc_save, ctx; |
607 | 607 | ||
608 | /* switch to nucleus because we are mapped by the primary context */ |
608 | /* switch to nucleus because we are mapped by the primary context */ |
609 | nucleus_enter(); |
609 | nucleus_enter(); |
610 | 610 | ||
611 | ctx.v = pc_save.v = mmu_primary_context_read(); |
611 | ctx.v = pc_save.v = mmu_primary_context_read(); |
612 | ctx.context = asid; |
612 | ctx.context = asid; |
613 | mmu_primary_context_write(ctx.v); |
613 | mmu_primary_context_write(ctx.v); |
614 | 614 | ||
615 | for (i = 0; i < cnt * MMU_PAGES_PER_PAGE; i++) { |
615 | for (i = 0; i < cnt * MMU_PAGES_PER_PAGE; i++) { |
616 | itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY, |
616 | itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY, |
617 | page + i * MMU_PAGE_SIZE); |
617 | page + i * MMU_PAGE_SIZE); |
618 | dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY, |
618 | dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY, |
619 | page + i * MMU_PAGE_SIZE); |
619 | page + i * MMU_PAGE_SIZE); |
620 | } |
620 | } |
621 | 621 | ||
622 | mmu_primary_context_write(pc_save.v); |
622 | mmu_primary_context_write(pc_save.v); |
623 | 623 | ||
624 | nucleus_leave(); |
624 | nucleus_leave(); |
625 | } |
625 | } |
626 | 626 | ||
627 | /** @} |
627 | /** @} |
628 | */ |
628 | */ |
629 | 629 |