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1 | /* |
1 | /* |
2 | * Copyright (c) 2005 Jakub Jermar |
2 | * Copyright (c) 2005 Jakub Jermar |
3 | * Copyright (c) 2008 Pavel Rimsky |
3 | * Copyright (c) 2008 Pavel Rimsky |
4 | * All rights reserved. |
4 | * All rights reserved. |
5 | * |
5 | * |
6 | * Redistribution and use in source and binary forms, with or without |
6 | * Redistribution and use in source and binary forms, with or without |
7 | * modification, are permitted provided that the following conditions |
7 | * modification, are permitted provided that the following conditions |
8 | * are met: |
8 | * are met: |
9 | * |
9 | * |
10 | * - Redistributions of source code must retain the above copyright |
10 | * - Redistributions of source code must retain the above copyright |
11 | * notice, this list of conditions and the following disclaimer. |
11 | * notice, this list of conditions and the following disclaimer. |
12 | * - Redistributions in binary form must reproduce the above copyright |
12 | * - Redistributions in binary form must reproduce the above copyright |
13 | * notice, this list of conditions and the following disclaimer in the |
13 | * notice, this list of conditions and the following disclaimer in the |
14 | * documentation and/or other materials provided with the distribution. |
14 | * documentation and/or other materials provided with the distribution. |
15 | * - The name of the author may not be used to endorse or promote products |
15 | * - The name of the author may not be used to endorse or promote products |
16 | * derived from this software without specific prior written permission. |
16 | * derived from this software without specific prior written permission. |
17 | * |
17 | * |
18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
21 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
23 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
27 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
28 | */ |
28 | */ |
29 | 29 | ||
30 | /** @addtogroup sparc64mm |
30 | /** @addtogroup sparc64mm |
31 | * @{ |
31 | * @{ |
32 | */ |
32 | */ |
33 | /** @file |
33 | /** @file |
34 | */ |
34 | */ |
35 | 35 | ||
36 | #include <mm/tlb.h> |
36 | #include <mm/tlb.h> |
37 | #include <mm/as.h> |
37 | #include <mm/as.h> |
38 | #include <mm/asid.h> |
38 | #include <mm/asid.h> |
39 | #include <arch/sun4v/hypercall.h> |
39 | #include <arch/sun4v/hypercall.h> |
40 | #include <arch/mm/frame.h> |
40 | #include <arch/mm/frame.h> |
41 | #include <arch/mm/page.h> |
41 | #include <arch/mm/page.h> |
42 | #include <arch/mm/sun4v/tte.h> |
42 | #include <arch/mm/sun4v/tte.h> |
43 | #include <arch/mm/sun4v/tlb.h> |
43 | #include <arch/mm/sun4v/tlb.h> |
44 | #include <arch/interrupt.h> |
44 | #include <arch/interrupt.h> |
45 | #include <interrupt.h> |
45 | #include <interrupt.h> |
46 | #include <arch.h> |
46 | #include <arch.h> |
47 | #include <print.h> |
47 | #include <print.h> |
48 | #include <arch/types.h> |
48 | #include <arch/types.h> |
49 | #include <config.h> |
49 | #include <config.h> |
50 | #include <arch/trap/trap.h> |
50 | #include <arch/trap/trap.h> |
51 | #include <arch/trap/exception.h> |
51 | #include <arch/trap/exception.h> |
52 | #include <panic.h> |
52 | #include <panic.h> |
53 | #include <arch/asm.h> |
53 | #include <arch/asm.h> |
54 | #include <arch/sun4v/cpu.h> |
54 | #include <arch/sun4v/cpu.h> |
55 | 55 | ||
56 | #ifdef CONFIG_TSB |
56 | #ifdef CONFIG_TSB |
57 | #include <arch/mm/tsb.h> |
57 | #include <arch/mm/tsb.h> |
58 | #endif |
58 | #endif |
59 | 59 | ||
60 | #if 0 |
60 | #if 0 |
61 | static void dtlb_pte_copy(pte_t *, index_t, bool); |
61 | static void dtlb_pte_copy(pte_t *, index_t, bool); |
62 | static void itlb_pte_copy(pte_t *, index_t); |
62 | static void itlb_pte_copy(pte_t *, index_t); |
63 | static void do_fast_instruction_access_mmu_miss_fault(istate_t *, const char *); |
63 | static void do_fast_instruction_access_mmu_miss_fault(istate_t *, const char *); |
64 | static void do_fast_data_access_mmu_miss_fault(istate_t *, tlb_tag_access_reg_t, |
64 | static void do_fast_data_access_mmu_miss_fault(istate_t *, tlb_tag_access_reg_t, |
65 | const char *); |
65 | const char *); |
66 | static void do_fast_data_access_protection_fault(istate_t *, |
66 | static void do_fast_data_access_protection_fault(istate_t *, |
67 | tlb_tag_access_reg_t, const char *); |
67 | tlb_tag_access_reg_t, const char *); |
68 | 68 | ||
69 | char *context_encoding[] = { |
69 | char *context_encoding[] = { |
70 | "Primary", |
70 | "Primary", |
71 | "Secondary", |
71 | "Secondary", |
72 | "Nucleus", |
72 | "Nucleus", |
73 | "Reserved" |
73 | "Reserved" |
74 | }; |
74 | }; |
75 | #endif |
75 | #endif |
76 | 76 | ||
77 | mmu_fault_status_area_t mmu_fault_status_areas[MAX_NUM_STRANDS] |
- | |
78 | __attribute__ ((aligned (64))); |
- | |
79 | - | ||
80 | void tlb_arch_init(void) |
- | |
81 | { |
- | |
82 | uint64_t errno; |
- | |
83 | /* |
77 | /* |
84 | * Invalidate all non-locked DTLB and ITLB entries. |
78 | * Invalidate all non-locked DTLB and ITLB entries. |
85 | */ |
79 | */ |
- | 80 | void tlb_arch_init(void) |
|
86 | 81 | { |
|
87 | tlb_invalidate_all(); |
82 | tlb_invalidate_all(); |
88 | - | ||
89 | /* |
- | |
90 | * Set the MMU fault status area for the current CPU. |
- | |
91 | */ |
- | |
92 | uint64_t myid; |
- | |
93 | __hypercall_fast_ret1(0, 0, 0, 0, 0, CPU_MYID, &myid); |
- | |
94 | errno = __hypercall_fast1(MMU_FAULT_AREA_CONF, |
- | |
95 | KA2PA(&(mmu_fault_status_areas[myid]))); |
- | |
96 | if (errno != EOK) { |
- | |
97 | panic("Could not set MMU fault area for CPU %d, errno = %d.\n", |
- | |
98 | myid, errno); |
- | |
99 | } |
- | |
100 | printf("Setting MMU fault area for CPU %d at %x.\n", myid, KA2PA(&(mmu_fault_status_areas[myid]))); |
- | |
101 | #if 0 |
- | |
102 | /* |
- | |
103 | * Clear both SFSRs. |
- | |
104 | */ |
- | |
105 | dtlb_sfsr_write(0); |
- | |
106 | itlb_sfsr_write(0); |
- | |
107 | #endif |
- | |
108 | } |
83 | } |
109 | 84 | ||
110 | /** Insert privileged mapping into DMMU TLB. |
85 | /** Insert privileged mapping into DMMU TLB. |
111 | * |
86 | * |
112 | * @param page Virtual page address. |
87 | * @param page Virtual page address. |
113 | * @param frame Physical frame address. |
88 | * @param frame Physical frame address. |
114 | * @param pagesize Page size. |
89 | * @param pagesize Page size. |
115 | * @param locked True for permanent mappings, false otherwise. |
90 | * @param locked True for permanent mappings, false otherwise. |
116 | * @param cacheable True if the mapping is cacheable, false otherwise. |
91 | * @param cacheable True if the mapping is cacheable, false otherwise. |
117 | */ |
92 | */ |
118 | void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, |
93 | void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, |
119 | bool locked, bool cacheable) |
94 | bool locked, bool cacheable) |
120 | { |
95 | { |
121 | #if 0 |
96 | #if 0 |
122 | tlb_tag_access_reg_t tag; |
97 | tlb_tag_access_reg_t tag; |
123 | tlb_data_t data; |
98 | tlb_data_t data; |
124 | page_address_t pg; |
99 | page_address_t pg; |
125 | frame_address_t fr; |
100 | frame_address_t fr; |
126 | 101 | ||
127 | pg.address = page; |
102 | pg.address = page; |
128 | fr.address = frame; |
103 | fr.address = frame; |
129 | 104 | ||
130 | tag.context = ASID_KERNEL; |
105 | tag.context = ASID_KERNEL; |
131 | tag.vpn = pg.vpn; |
106 | tag.vpn = pg.vpn; |
132 | 107 | ||
133 | dtlb_tag_access_write(tag.value); |
108 | dtlb_tag_access_write(tag.value); |
134 | 109 | ||
135 | data.value = 0; |
110 | data.value = 0; |
136 | data.v = true; |
111 | data.v = true; |
137 | data.size = pagesize; |
112 | data.size = pagesize; |
138 | data.pfn = fr.pfn; |
113 | data.pfn = fr.pfn; |
139 | data.l = locked; |
114 | data.l = locked; |
140 | data.cp = cacheable; |
115 | data.cp = cacheable; |
141 | #ifdef CONFIG_VIRT_IDX_DCACHE |
116 | #ifdef CONFIG_VIRT_IDX_DCACHE |
142 | data.cv = cacheable; |
117 | data.cv = cacheable; |
143 | #endif /* CONFIG_VIRT_IDX_DCACHE */ |
118 | #endif /* CONFIG_VIRT_IDX_DCACHE */ |
144 | data.p = true; |
119 | data.p = true; |
145 | data.w = true; |
120 | data.w = true; |
146 | data.g = false; |
121 | data.g = false; |
147 | 122 | ||
148 | dtlb_data_in_write(data.value); |
123 | dtlb_data_in_write(data.value); |
149 | #endif |
124 | #endif |
150 | } |
125 | } |
151 | 126 | ||
152 | /** Copy PTE to TLB. |
127 | /** Copy PTE to TLB. |
153 | * |
128 | * |
154 | * @param t Page Table Entry to be copied. |
129 | * @param t Page Table Entry to be copied. |
155 | * @param index Zero if lower 8K-subpage, one if higher 8K-subpage. |
130 | * @param index Zero if lower 8K-subpage, one if higher 8K-subpage. |
156 | * @param ro If true, the entry will be created read-only, regardless |
131 | * @param ro If true, the entry will be created read-only, regardless |
157 | * of its w field. |
132 | * of its w field. |
158 | */ |
133 | */ |
159 | #if 0 |
134 | #if 0 |
160 | void dtlb_pte_copy(pte_t *t, index_t index, bool ro) |
135 | void dtlb_pte_copy(pte_t *t, index_t index, bool ro) |
161 | { |
136 | { |
162 | tlb_tag_access_reg_t tag; |
137 | tlb_tag_access_reg_t tag; |
163 | tlb_data_t data; |
138 | tlb_data_t data; |
164 | page_address_t pg; |
139 | page_address_t pg; |
165 | frame_address_t fr; |
140 | frame_address_t fr; |
166 | 141 | ||
167 | pg.address = t->page + (index << MMU_PAGE_WIDTH); |
142 | pg.address = t->page + (index << MMU_PAGE_WIDTH); |
168 | fr.address = t->frame + (index << MMU_PAGE_WIDTH); |
143 | fr.address = t->frame + (index << MMU_PAGE_WIDTH); |
169 | 144 | ||
170 | tag.value = 0; |
145 | tag.value = 0; |
171 | tag.context = t->as->asid; |
146 | tag.context = t->as->asid; |
172 | tag.vpn = pg.vpn; |
147 | tag.vpn = pg.vpn; |
173 | 148 | ||
174 | dtlb_tag_access_write(tag.value); |
149 | dtlb_tag_access_write(tag.value); |
175 | 150 | ||
176 | data.value = 0; |
151 | data.value = 0; |
177 | data.v = true; |
152 | data.v = true; |
178 | data.size = PAGESIZE_8K; |
153 | data.size = PAGESIZE_8K; |
179 | data.pfn = fr.pfn; |
154 | data.pfn = fr.pfn; |
180 | data.l = false; |
155 | data.l = false; |
181 | data.cp = t->c; |
156 | data.cp = t->c; |
182 | #ifdef CONFIG_VIRT_IDX_DCACHE |
157 | #ifdef CONFIG_VIRT_IDX_DCACHE |
183 | data.cv = t->c; |
158 | data.cv = t->c; |
184 | #endif /* CONFIG_VIRT_IDX_DCACHE */ |
159 | #endif /* CONFIG_VIRT_IDX_DCACHE */ |
185 | data.p = t->k; /* p like privileged */ |
160 | data.p = t->k; /* p like privileged */ |
186 | data.w = ro ? false : t->w; |
161 | data.w = ro ? false : t->w; |
187 | data.g = t->g; |
162 | data.g = t->g; |
188 | 163 | ||
189 | dtlb_data_in_write(data.value); |
164 | dtlb_data_in_write(data.value); |
190 | } |
165 | } |
191 | #endif |
166 | #endif |
192 | 167 | ||
193 | /** Copy PTE to ITLB. |
168 | /** Copy PTE to ITLB. |
194 | * |
169 | * |
195 | * @param t Page Table Entry to be copied. |
170 | * @param t Page Table Entry to be copied. |
196 | * @param index Zero if lower 8K-subpage, one if higher 8K-subpage. |
171 | * @param index Zero if lower 8K-subpage, one if higher 8K-subpage. |
197 | */ |
172 | */ |
198 | #if 0 |
173 | #if 0 |
199 | void itlb_pte_copy(pte_t *t, index_t index) |
174 | void itlb_pte_copy(pte_t *t, index_t index) |
200 | { |
175 | { |
201 | tlb_tag_access_reg_t tag; |
176 | tlb_tag_access_reg_t tag; |
202 | tlb_data_t data; |
177 | tlb_data_t data; |
203 | page_address_t pg; |
178 | page_address_t pg; |
204 | frame_address_t fr; |
179 | frame_address_t fr; |
205 | 180 | ||
206 | pg.address = t->page + (index << MMU_PAGE_WIDTH); |
181 | pg.address = t->page + (index << MMU_PAGE_WIDTH); |
207 | fr.address = t->frame + (index << MMU_PAGE_WIDTH); |
182 | fr.address = t->frame + (index << MMU_PAGE_WIDTH); |
208 | 183 | ||
209 | tag.value = 0; |
184 | tag.value = 0; |
210 | tag.context = t->as->asid; |
185 | tag.context = t->as->asid; |
211 | tag.vpn = pg.vpn; |
186 | tag.vpn = pg.vpn; |
212 | 187 | ||
213 | itlb_tag_access_write(tag.value); |
188 | itlb_tag_access_write(tag.value); |
214 | 189 | ||
215 | data.value = 0; |
190 | data.value = 0; |
216 | data.v = true; |
191 | data.v = true; |
217 | data.size = PAGESIZE_8K; |
192 | data.size = PAGESIZE_8K; |
218 | data.pfn = fr.pfn; |
193 | data.pfn = fr.pfn; |
219 | data.l = false; |
194 | data.l = false; |
220 | data.cp = t->c; |
195 | data.cp = t->c; |
221 | data.p = t->k; /* p like privileged */ |
196 | data.p = t->k; /* p like privileged */ |
222 | data.w = false; |
197 | data.w = false; |
223 | data.g = t->g; |
198 | data.g = t->g; |
224 | 199 | ||
225 | itlb_data_in_write(data.value); |
200 | itlb_data_in_write(data.value); |
226 | } |
201 | } |
227 | #endif |
202 | #endif |
228 | 203 | ||
229 | /** ITLB miss handler. */ |
204 | /** ITLB miss handler. */ |
230 | void fast_instruction_access_mmu_miss(unative_t unused, istate_t *istate) |
205 | void fast_instruction_access_mmu_miss(unative_t unused, istate_t *istate) |
231 | { |
206 | { |
232 | #if 0 |
207 | #if 0 |
233 | uintptr_t va = ALIGN_DOWN(istate->tpc, PAGE_SIZE); |
208 | uintptr_t va = ALIGN_DOWN(istate->tpc, PAGE_SIZE); |
234 | index_t index = (istate->tpc >> MMU_PAGE_WIDTH) % MMU_PAGES_PER_PAGE; |
209 | index_t index = (istate->tpc >> MMU_PAGE_WIDTH) % MMU_PAGES_PER_PAGE; |
235 | pte_t *t; |
210 | pte_t *t; |
236 | 211 | ||
237 | page_table_lock(AS, true); |
212 | page_table_lock(AS, true); |
238 | t = page_mapping_find(AS, va); |
213 | t = page_mapping_find(AS, va); |
239 | if (t && PTE_EXECUTABLE(t)) { |
214 | if (t && PTE_EXECUTABLE(t)) { |
240 | /* |
215 | /* |
241 | * The mapping was found in the software page hash table. |
216 | * The mapping was found in the software page hash table. |
242 | * Insert it into ITLB. |
217 | * Insert it into ITLB. |
243 | */ |
218 | */ |
244 | t->a = true; |
219 | t->a = true; |
245 | itlb_pte_copy(t, index); |
220 | itlb_pte_copy(t, index); |
246 | #ifdef CONFIG_TSB |
221 | #ifdef CONFIG_TSB |
247 | itsb_pte_copy(t, index); |
222 | itsb_pte_copy(t, index); |
248 | #endif |
223 | #endif |
249 | page_table_unlock(AS, true); |
224 | page_table_unlock(AS, true); |
250 | } else { |
225 | } else { |
251 | /* |
226 | /* |
252 | * Forward the page fault to the address space page fault |
227 | * Forward the page fault to the address space page fault |
253 | * handler. |
228 | * handler. |
254 | */ |
229 | */ |
255 | page_table_unlock(AS, true); |
230 | page_table_unlock(AS, true); |
256 | if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) { |
231 | if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) { |
257 | do_fast_instruction_access_mmu_miss_fault(istate, |
232 | do_fast_instruction_access_mmu_miss_fault(istate, |
258 | __func__); |
233 | __func__); |
259 | } |
234 | } |
260 | } |
235 | } |
261 | #endif |
236 | #endif |
262 | } |
237 | } |
263 | 238 | ||
264 | /** DTLB miss handler. |
239 | /** DTLB miss handler. |
265 | * |
240 | * |
266 | * Note that some faults (e.g. kernel faults) were already resolved by the |
241 | * Note that some faults (e.g. kernel faults) were already resolved by the |
267 | * low-level, assembly language part of the fast_data_access_mmu_miss handler. |
242 | * low-level, assembly language part of the fast_data_access_mmu_miss handler. |
268 | * |
243 | * |
269 | * @param tag Content of the TLB Tag Access register as it existed |
244 | * @param tag Content of the TLB Tag Access register as it existed |
270 | * when the trap happened. This is to prevent confusion |
245 | * when the trap happened. This is to prevent confusion |
271 | * created by clobbered Tag Access register during a nested |
246 | * created by clobbered Tag Access register during a nested |
272 | * DTLB miss. |
247 | * DTLB miss. |
273 | * @param istate Interrupted state saved on the stack. |
248 | * @param istate Interrupted state saved on the stack. |
274 | */ |
249 | */ |
275 | //void fast_data_access_mmu_miss(tlb_tag_access_reg_t tag, istate_t *istate) |
250 | //void fast_data_access_mmu_miss(tlb_tag_access_reg_t tag, istate_t *istate) |
276 | //{ |
251 | //{ |
277 | #if 0 |
252 | #if 0 |
278 | uintptr_t va; |
253 | uintptr_t va; |
279 | index_t index; |
254 | index_t index; |
280 | pte_t *t; |
255 | pte_t *t; |
281 | 256 | ||
282 | va = ALIGN_DOWN((uint64_t) tag.vpn << MMU_PAGE_WIDTH, PAGE_SIZE); |
257 | va = ALIGN_DOWN((uint64_t) tag.vpn << MMU_PAGE_WIDTH, PAGE_SIZE); |
283 | index = tag.vpn % MMU_PAGES_PER_PAGE; |
258 | index = tag.vpn % MMU_PAGES_PER_PAGE; |
284 | 259 | ||
285 | if (tag.context == ASID_KERNEL) { |
260 | if (tag.context == ASID_KERNEL) { |
286 | if (!tag.vpn) { |
261 | if (!tag.vpn) { |
287 | /* NULL access in kernel */ |
262 | /* NULL access in kernel */ |
288 | do_fast_data_access_mmu_miss_fault(istate, tag, |
263 | do_fast_data_access_mmu_miss_fault(istate, tag, |
289 | __func__); |
264 | __func__); |
290 | } |
265 | } |
291 | do_fast_data_access_mmu_miss_fault(istate, tag, "Unexpected " |
266 | do_fast_data_access_mmu_miss_fault(istate, tag, "Unexpected " |
292 | "kernel page fault."); |
267 | "kernel page fault."); |
293 | } |
268 | } |
294 | 269 | ||
295 | page_table_lock(AS, true); |
270 | page_table_lock(AS, true); |
296 | t = page_mapping_find(AS, va); |
271 | t = page_mapping_find(AS, va); |
297 | if (t) { |
272 | if (t) { |
298 | /* |
273 | /* |
299 | * The mapping was found in the software page hash table. |
274 | * The mapping was found in the software page hash table. |
300 | * Insert it into DTLB. |
275 | * Insert it into DTLB. |
301 | */ |
276 | */ |
302 | t->a = true; |
277 | t->a = true; |
303 | dtlb_pte_copy(t, index, true); |
278 | dtlb_pte_copy(t, index, true); |
304 | #ifdef CONFIG_TSB |
279 | #ifdef CONFIG_TSB |
305 | dtsb_pte_copy(t, index, true); |
280 | dtsb_pte_copy(t, index, true); |
306 | #endif |
281 | #endif |
307 | page_table_unlock(AS, true); |
282 | page_table_unlock(AS, true); |
308 | } else { |
283 | } else { |
309 | /* |
284 | /* |
310 | * Forward the page fault to the address space page fault |
285 | * Forward the page fault to the address space page fault |
311 | * handler. |
286 | * handler. |
312 | */ |
287 | */ |
313 | page_table_unlock(AS, true); |
288 | page_table_unlock(AS, true); |
314 | if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) { |
289 | if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) { |
315 | do_fast_data_access_mmu_miss_fault(istate, tag, |
290 | do_fast_data_access_mmu_miss_fault(istate, tag, |
316 | __func__); |
291 | __func__); |
317 | } |
292 | } |
318 | } |
293 | } |
319 | #endif |
294 | #endif |
320 | //} |
295 | //} |
321 | 296 | ||
322 | /** DTLB protection fault handler. |
297 | /** DTLB protection fault handler. |
323 | * |
298 | * |
324 | * @param tag Content of the TLB Tag Access register as it existed |
299 | * @param tag Content of the TLB Tag Access register as it existed |
325 | * when the trap happened. This is to prevent confusion |
300 | * when the trap happened. This is to prevent confusion |
326 | * created by clobbered Tag Access register during a nested |
301 | * created by clobbered Tag Access register during a nested |
327 | * DTLB miss. |
302 | * DTLB miss. |
328 | * @param istate Interrupted state saved on the stack. |
303 | * @param istate Interrupted state saved on the stack. |
329 | */ |
304 | */ |
330 | //void fast_data_access_protection(tlb_tag_access_reg_t tag, istate_t *istate) |
305 | //void fast_data_access_protection(tlb_tag_access_reg_t tag, istate_t *istate) |
331 | //{ |
306 | //{ |
332 | #if 0 |
307 | #if 0 |
333 | uintptr_t va; |
308 | uintptr_t va; |
334 | index_t index; |
309 | index_t index; |
335 | pte_t *t; |
310 | pte_t *t; |
336 | 311 | ||
337 | va = ALIGN_DOWN((uint64_t) tag.vpn << MMU_PAGE_WIDTH, PAGE_SIZE); |
312 | va = ALIGN_DOWN((uint64_t) tag.vpn << MMU_PAGE_WIDTH, PAGE_SIZE); |
338 | index = tag.vpn % MMU_PAGES_PER_PAGE; /* 16K-page emulation */ |
313 | index = tag.vpn % MMU_PAGES_PER_PAGE; /* 16K-page emulation */ |
339 | 314 | ||
340 | page_table_lock(AS, true); |
315 | page_table_lock(AS, true); |
341 | t = page_mapping_find(AS, va); |
316 | t = page_mapping_find(AS, va); |
342 | if (t && PTE_WRITABLE(t)) { |
317 | if (t && PTE_WRITABLE(t)) { |
343 | /* |
318 | /* |
344 | * The mapping was found in the software page hash table and is |
319 | * The mapping was found in the software page hash table and is |
345 | * writable. Demap the old mapping and insert an updated mapping |
320 | * writable. Demap the old mapping and insert an updated mapping |
346 | * into DTLB. |
321 | * into DTLB. |
347 | */ |
322 | */ |
348 | t->a = true; |
323 | t->a = true; |
349 | t->d = true; |
324 | t->d = true; |
350 | dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_SECONDARY, |
325 | dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_SECONDARY, |
351 | va + index * MMU_PAGE_SIZE); |
326 | va + index * MMU_PAGE_SIZE); |
352 | dtlb_pte_copy(t, index, false); |
327 | dtlb_pte_copy(t, index, false); |
353 | #ifdef CONFIG_TSB |
328 | #ifdef CONFIG_TSB |
354 | dtsb_pte_copy(t, index, false); |
329 | dtsb_pte_copy(t, index, false); |
355 | #endif |
330 | #endif |
356 | page_table_unlock(AS, true); |
331 | page_table_unlock(AS, true); |
357 | } else { |
332 | } else { |
358 | /* |
333 | /* |
359 | * Forward the page fault to the address space page fault |
334 | * Forward the page fault to the address space page fault |
360 | * handler. |
335 | * handler. |
361 | */ |
336 | */ |
362 | page_table_unlock(AS, true); |
337 | page_table_unlock(AS, true); |
363 | if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) { |
338 | if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) { |
364 | do_fast_data_access_protection_fault(istate, tag, |
339 | do_fast_data_access_protection_fault(istate, tag, |
365 | __func__); |
340 | __func__); |
366 | } |
341 | } |
367 | } |
342 | } |
368 | #endif |
343 | #endif |
369 | //} |
344 | //} |
370 | 345 | ||
371 | /** Print TLB entry (for debugging purposes). |
346 | /** Print TLB entry (for debugging purposes). |
372 | * |
347 | * |
373 | * The diag field has been left out in order to make this function more generic |
348 | * The diag field has been left out in order to make this function more generic |
374 | * (there is no diag field in US3 architeture). |
349 | * (there is no diag field in US3 architeture). |
375 | * |
350 | * |
376 | * @param i TLB entry number |
351 | * @param i TLB entry number |
377 | * @param t TLB entry tag |
352 | * @param t TLB entry tag |
378 | * @param d TLB entry data |
353 | * @param d TLB entry data |
379 | */ |
354 | */ |
380 | #if 0 |
355 | #if 0 |
381 | static void print_tlb_entry(int i, tlb_tag_read_reg_t t, tlb_data_t d) |
356 | static void print_tlb_entry(int i, tlb_tag_read_reg_t t, tlb_data_t d) |
382 | { |
357 | { |
383 | printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, " |
358 | printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, " |
384 | "ie=%d, soft2=%#x, pfn=%#x, soft=%#x, l=%d, " |
359 | "ie=%d, soft2=%#x, pfn=%#x, soft=%#x, l=%d, " |
385 | "cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", i, t.vpn, |
360 | "cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", i, t.vpn, |
386 | t.context, d.v, d.size, d.nfo, d.ie, d.soft2, |
361 | t.context, d.v, d.size, d.nfo, d.ie, d.soft2, |
387 | d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g); |
362 | d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g); |
388 | } |
363 | } |
389 | #endif |
364 | #endif |
390 | 365 | ||
391 | #if defined (US) |
366 | #if defined (US) |
392 | 367 | ||
393 | /** Print contents of both TLBs. */ |
368 | /** Print contents of both TLBs. */ |
394 | void tlb_print(void) |
369 | void tlb_print(void) |
395 | #if 0 |
370 | #if 0 |
396 | { |
371 | { |
397 | int i; |
372 | int i; |
398 | tlb_data_t d; |
373 | tlb_data_t d; |
399 | tlb_tag_read_reg_t t; |
374 | tlb_tag_read_reg_t t; |
400 | 375 | ||
401 | printf("I-TLB contents:\n"); |
376 | printf("I-TLB contents:\n"); |
402 | for (i = 0; i < ITLB_ENTRY_COUNT; i++) { |
377 | for (i = 0; i < ITLB_ENTRY_COUNT; i++) { |
403 | d.value = itlb_data_access_read(i); |
378 | d.value = itlb_data_access_read(i); |
404 | t.value = itlb_tag_read_read(i); |
379 | t.value = itlb_tag_read_read(i); |
405 | print_tlb_entry(i, t, d); |
380 | print_tlb_entry(i, t, d); |
406 | } |
381 | } |
407 | 382 | ||
408 | printf("D-TLB contents:\n"); |
383 | printf("D-TLB contents:\n"); |
409 | for (i = 0; i < DTLB_ENTRY_COUNT; i++) { |
384 | for (i = 0; i < DTLB_ENTRY_COUNT; i++) { |
410 | d.value = dtlb_data_access_read(i); |
385 | d.value = dtlb_data_access_read(i); |
411 | t.value = dtlb_tag_read_read(i); |
386 | t.value = dtlb_tag_read_read(i); |
412 | print_tlb_entry(i, t, d); |
387 | print_tlb_entry(i, t, d); |
413 | } |
388 | } |
414 | #endif |
389 | #endif |
415 | } |
390 | } |
416 | 391 | ||
417 | #elif defined (US3) |
392 | #elif defined (US3) |
418 | 393 | ||
419 | /** Print contents of all TLBs. */ |
394 | /** Print contents of all TLBs. */ |
420 | void tlb_print(void) |
395 | void tlb_print(void) |
421 | { |
396 | { |
422 | #if 0 |
397 | #if 0 |
423 | int i; |
398 | int i; |
424 | tlb_data_t d; |
399 | tlb_data_t d; |
425 | tlb_tag_read_reg_t t; |
400 | tlb_tag_read_reg_t t; |
426 | 401 | ||
427 | printf("TLB_ISMALL contents:\n"); |
402 | printf("TLB_ISMALL contents:\n"); |
428 | for (i = 0; i < tlb_ismall_size(); i++) { |
403 | for (i = 0; i < tlb_ismall_size(); i++) { |
429 | d.value = dtlb_data_access_read(TLB_ISMALL, i); |
404 | d.value = dtlb_data_access_read(TLB_ISMALL, i); |
430 | t.value = dtlb_tag_read_read(TLB_ISMALL, i); |
405 | t.value = dtlb_tag_read_read(TLB_ISMALL, i); |
431 | print_tlb_entry(i, t, d); |
406 | print_tlb_entry(i, t, d); |
432 | } |
407 | } |
433 | 408 | ||
434 | printf("TLB_IBIG contents:\n"); |
409 | printf("TLB_IBIG contents:\n"); |
435 | for (i = 0; i < tlb_ibig_size(); i++) { |
410 | for (i = 0; i < tlb_ibig_size(); i++) { |
436 | d.value = dtlb_data_access_read(TLB_IBIG, i); |
411 | d.value = dtlb_data_access_read(TLB_IBIG, i); |
437 | t.value = dtlb_tag_read_read(TLB_IBIG, i); |
412 | t.value = dtlb_tag_read_read(TLB_IBIG, i); |
438 | print_tlb_entry(i, t, d); |
413 | print_tlb_entry(i, t, d); |
439 | } |
414 | } |
440 | 415 | ||
441 | printf("TLB_DSMALL contents:\n"); |
416 | printf("TLB_DSMALL contents:\n"); |
442 | for (i = 0; i < tlb_dsmall_size(); i++) { |
417 | for (i = 0; i < tlb_dsmall_size(); i++) { |
443 | d.value = dtlb_data_access_read(TLB_DSMALL, i); |
418 | d.value = dtlb_data_access_read(TLB_DSMALL, i); |
444 | t.value = dtlb_tag_read_read(TLB_DSMALL, i); |
419 | t.value = dtlb_tag_read_read(TLB_DSMALL, i); |
445 | print_tlb_entry(i, t, d); |
420 | print_tlb_entry(i, t, d); |
446 | } |
421 | } |
447 | 422 | ||
448 | printf("TLB_DBIG_1 contents:\n"); |
423 | printf("TLB_DBIG_1 contents:\n"); |
449 | for (i = 0; i < tlb_dbig_size(); i++) { |
424 | for (i = 0; i < tlb_dbig_size(); i++) { |
450 | d.value = dtlb_data_access_read(TLB_DBIG_0, i); |
425 | d.value = dtlb_data_access_read(TLB_DBIG_0, i); |
451 | t.value = dtlb_tag_read_read(TLB_DBIG_0, i); |
426 | t.value = dtlb_tag_read_read(TLB_DBIG_0, i); |
452 | print_tlb_entry(i, t, d); |
427 | print_tlb_entry(i, t, d); |
453 | } |
428 | } |
454 | 429 | ||
455 | printf("TLB_DBIG_2 contents:\n"); |
430 | printf("TLB_DBIG_2 contents:\n"); |
456 | for (i = 0; i < tlb_dbig_size(); i++) { |
431 | for (i = 0; i < tlb_dbig_size(); i++) { |
457 | d.value = dtlb_data_access_read(TLB_DBIG_1, i); |
432 | d.value = dtlb_data_access_read(TLB_DBIG_1, i); |
458 | t.value = dtlb_tag_read_read(TLB_DBIG_1, i); |
433 | t.value = dtlb_tag_read_read(TLB_DBIG_1, i); |
459 | print_tlb_entry(i, t, d); |
434 | print_tlb_entry(i, t, d); |
460 | } |
435 | } |
461 | #endif |
436 | #endif |
462 | } |
437 | } |
463 | 438 | ||
464 | #endif |
439 | #endif |
465 | 440 | ||
466 | #if 0 |
441 | #if 0 |
467 | void do_fast_instruction_access_mmu_miss_fault(istate_t *istate, |
442 | void do_fast_instruction_access_mmu_miss_fault(istate_t *istate, |
468 | const char *str) |
443 | const char *str) |
469 | { |
444 | { |
470 | fault_if_from_uspace(istate, "%s\n", str); |
445 | fault_if_from_uspace(istate, "%s\n", str); |
471 | dump_istate(istate); |
446 | dump_istate(istate); |
472 | panic("%s\n", str); |
447 | panic("%s\n", str); |
473 | } |
448 | } |
474 | #endif |
449 | #endif |
475 | 450 | ||
476 | #if 0 |
451 | #if 0 |
477 | void do_fast_data_access_mmu_miss_fault(istate_t *istate, |
452 | void do_fast_data_access_mmu_miss_fault(istate_t *istate, |
478 | tlb_tag_access_reg_t tag, const char *str) |
453 | tlb_tag_access_reg_t tag, const char *str) |
479 | { |
454 | { |
480 | uintptr_t va; |
455 | uintptr_t va; |
481 | 456 | ||
482 | va = tag.vpn << MMU_PAGE_WIDTH; |
457 | va = tag.vpn << MMU_PAGE_WIDTH; |
483 | if (tag.context) { |
458 | if (tag.context) { |
484 | fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va, |
459 | fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va, |
485 | tag.context); |
460 | tag.context); |
486 | } |
461 | } |
487 | dump_istate(istate); |
462 | dump_istate(istate); |
488 | printf("Faulting page: %p, ASID=%d\n", va, tag.context); |
463 | printf("Faulting page: %p, ASID=%d\n", va, tag.context); |
489 | panic("%s\n", str); |
464 | panic("%s\n", str); |
490 | } |
465 | } |
491 | #endif |
466 | #endif |
492 | 467 | ||
493 | #if 0 |
468 | #if 0 |
494 | void do_fast_data_access_protection_fault(istate_t *istate, |
469 | void do_fast_data_access_protection_fault(istate_t *istate, |
495 | tlb_tag_access_reg_t tag, const char *str) |
470 | tlb_tag_access_reg_t tag, const char *str) |
496 | { |
471 | { |
497 | uintptr_t va; |
472 | uintptr_t va; |
498 | 473 | ||
499 | va = tag.vpn << MMU_PAGE_WIDTH; |
474 | va = tag.vpn << MMU_PAGE_WIDTH; |
500 | 475 | ||
501 | if (tag.context) { |
476 | if (tag.context) { |
502 | fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va, |
477 | fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va, |
503 | tag.context); |
478 | tag.context); |
504 | } |
479 | } |
505 | printf("Faulting page: %p, ASID=%d\n", va, tag.context); |
480 | printf("Faulting page: %p, ASID=%d\n", va, tag.context); |
506 | dump_istate(istate); |
481 | dump_istate(istate); |
507 | panic("%s\n", str); |
482 | panic("%s\n", str); |
508 | } |
483 | } |
509 | #endif |
484 | #endif |
510 | 485 | ||
511 | void describe_mmu_fault(void) |
486 | void describe_mmu_fault(void) |
512 | { |
487 | { |
513 | } |
488 | } |
514 | 489 | ||
515 | #if defined (US3) |
490 | #if defined (US3) |
516 | /** Invalidates given TLB entry if and only if it is non-locked or global. |
491 | /** Invalidates given TLB entry if and only if it is non-locked or global. |
517 | * |
492 | * |
518 | * @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1, |
493 | * @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1, |
519 | * TLB_ISMALL, TLB_IBIG). |
494 | * TLB_ISMALL, TLB_IBIG). |
520 | * @param entry Entry index within the given TLB. |
495 | * @param entry Entry index within the given TLB. |
521 | */ |
496 | */ |
522 | #if 0 |
497 | #if 0 |
523 | static void tlb_invalidate_entry(int tlb, index_t entry) |
498 | static void tlb_invalidate_entry(int tlb, index_t entry) |
524 | { |
499 | { |
525 | tlb_data_t d; |
500 | tlb_data_t d; |
526 | tlb_tag_read_reg_t t; |
501 | tlb_tag_read_reg_t t; |
527 | 502 | ||
528 | if (tlb == TLB_DSMALL || tlb == TLB_DBIG_0 || tlb == TLB_DBIG_1) { |
503 | if (tlb == TLB_DSMALL || tlb == TLB_DBIG_0 || tlb == TLB_DBIG_1) { |
529 | d.value = dtlb_data_access_read(tlb, entry); |
504 | d.value = dtlb_data_access_read(tlb, entry); |
530 | if (!d.l || d.g) { |
505 | if (!d.l || d.g) { |
531 | t.value = dtlb_tag_read_read(tlb, entry); |
506 | t.value = dtlb_tag_read_read(tlb, entry); |
532 | d.v = false; |
507 | d.v = false; |
533 | dtlb_tag_access_write(t.value); |
508 | dtlb_tag_access_write(t.value); |
534 | dtlb_data_access_write(tlb, entry, d.value); |
509 | dtlb_data_access_write(tlb, entry, d.value); |
535 | } |
510 | } |
536 | } else if (tlb == TLB_ISMALL || tlb == TLB_IBIG) { |
511 | } else if (tlb == TLB_ISMALL || tlb == TLB_IBIG) { |
537 | d.value = itlb_data_access_read(tlb, entry); |
512 | d.value = itlb_data_access_read(tlb, entry); |
538 | if (!d.l || d.g) { |
513 | if (!d.l || d.g) { |
539 | t.value = itlb_tag_read_read(tlb, entry); |
514 | t.value = itlb_tag_read_read(tlb, entry); |
540 | d.v = false; |
515 | d.v = false; |
541 | itlb_tag_access_write(t.value); |
516 | itlb_tag_access_write(t.value); |
542 | itlb_data_access_write(tlb, entry, d.value); |
517 | itlb_data_access_write(tlb, entry, d.value); |
543 | } |
518 | } |
544 | } |
519 | } |
545 | } |
520 | } |
546 | #endif |
521 | #endif |
547 | #endif |
522 | #endif |
548 | 523 | ||
549 | /** Invalidate all unlocked ITLB and DTLB entries. */ |
524 | /** Invalidate all unlocked ITLB and DTLB entries. */ |
550 | void tlb_invalidate_all(void) |
525 | void tlb_invalidate_all(void) |
551 | { |
526 | { |
552 | uint64_t errno = __hypercall_fast3(MMU_DEMAP_ALL, 0, 0, |
527 | uint64_t errno = __hypercall_fast3(MMU_DEMAP_ALL, 0, 0, |
553 | MMU_FLAG_DTLB | MMU_FLAG_ITLB); |
528 | MMU_FLAG_DTLB | MMU_FLAG_ITLB); |
554 | if (errno != EOK) { |
529 | if (errno != EOK) { |
555 | panic("Error code = %d.\n", errno); |
530 | panic("Error code = %d.\n", errno); |
556 | } |
531 | } |
557 | } |
532 | } |
558 | 533 | ||
559 | /** Invalidate all ITLB and DTLB entries that belong to specified ASID |
534 | /** Invalidate all ITLB and DTLB entries that belong to specified ASID |
560 | * (Context). |
535 | * (Context). |
561 | * |
536 | * |
562 | * @param asid Address Space ID. |
537 | * @param asid Address Space ID. |
563 | */ |
538 | */ |
564 | void tlb_invalidate_asid(asid_t asid) |
539 | void tlb_invalidate_asid(asid_t asid) |
565 | { |
540 | { |
566 | #if 0 |
541 | #if 0 |
567 | tlb_context_reg_t pc_save, ctx; |
542 | tlb_context_reg_t pc_save, ctx; |
568 | 543 | ||
569 | /* switch to nucleus because we are mapped by the primary context */ |
544 | /* switch to nucleus because we are mapped by the primary context */ |
570 | nucleus_enter(); |
545 | nucleus_enter(); |
571 | 546 | ||
572 | ctx.v = pc_save.v = mmu_primary_context_read(); |
547 | ctx.v = pc_save.v = mmu_primary_context_read(); |
573 | ctx.context = asid; |
548 | ctx.context = asid; |
574 | mmu_primary_context_write(ctx.v); |
549 | mmu_primary_context_write(ctx.v); |
575 | 550 | ||
576 | itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0); |
551 | itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0); |
577 | dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0); |
552 | dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0); |
578 | 553 | ||
579 | mmu_primary_context_write(pc_save.v); |
554 | mmu_primary_context_write(pc_save.v); |
580 | 555 | ||
581 | nucleus_leave(); |
556 | nucleus_leave(); |
582 | #endif |
557 | #endif |
583 | } |
558 | } |
584 | 559 | ||
585 | /** Invalidate all ITLB and DTLB entries for specified page range in specified |
560 | /** Invalidate all ITLB and DTLB entries for specified page range in specified |
586 | * address space. |
561 | * address space. |
587 | * |
562 | * |
588 | * @param asid Address Space ID. |
563 | * @param asid Address Space ID. |
589 | * @param page First page which to sweep out from ITLB and DTLB. |
564 | * @param page First page which to sweep out from ITLB and DTLB. |
590 | * @param cnt Number of ITLB and DTLB entries to invalidate. |
565 | * @param cnt Number of ITLB and DTLB entries to invalidate. |
591 | */ |
566 | */ |
592 | void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt) |
567 | void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt) |
593 | { |
568 | { |
594 | #if 0 |
569 | #if 0 |
595 | unsigned int i; |
570 | unsigned int i; |
596 | tlb_context_reg_t pc_save, ctx; |
571 | tlb_context_reg_t pc_save, ctx; |
597 | 572 | ||
598 | /* switch to nucleus because we are mapped by the primary context */ |
573 | /* switch to nucleus because we are mapped by the primary context */ |
599 | nucleus_enter(); |
574 | nucleus_enter(); |
600 | 575 | ||
601 | ctx.v = pc_save.v = mmu_primary_context_read(); |
576 | ctx.v = pc_save.v = mmu_primary_context_read(); |
602 | ctx.context = asid; |
577 | ctx.context = asid; |
603 | mmu_primary_context_write(ctx.v); |
578 | mmu_primary_context_write(ctx.v); |
604 | 579 | ||
605 | for (i = 0; i < cnt * MMU_PAGES_PER_PAGE; i++) { |
580 | for (i = 0; i < cnt * MMU_PAGES_PER_PAGE; i++) { |
606 | itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY, |
581 | itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY, |
607 | page + i * MMU_PAGE_SIZE); |
582 | page + i * MMU_PAGE_SIZE); |
608 | dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY, |
583 | dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY, |
609 | page + i * MMU_PAGE_SIZE); |
584 | page + i * MMU_PAGE_SIZE); |
610 | } |
585 | } |
611 | 586 | ||
612 | mmu_primary_context_write(pc_save.v); |
587 | mmu_primary_context_write(pc_save.v); |
613 | 588 | ||
614 | nucleus_leave(); |
589 | nucleus_leave(); |
615 | #endif |
590 | #endif |
616 | } |
591 | } |
617 | 592 | ||
618 | /** @} |
593 | /** @} |
619 | */ |
594 | */ |
620 | 595 |