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1 | /* |
1 | /* |
2 | * Copyright (c) 2006 Jakub Jermar |
2 | * Copyright (c) 2006 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup sparc64 |
29 | /** @addtogroup sparc64 |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | * |
33 | * |
34 | */ |
34 | */ |
35 | 35 | ||
36 | #include <fpu_context.h> |
36 | #include <fpu_context.h> |
37 | #include <arch/register.h> |
37 | #include <arch/register.h> |
38 | #include <arch/asm.h> |
38 | #include <arch/asm.h> |
39 | 39 | ||
40 | void fpu_context_save(fpu_context_t *fctx) |
40 | void fpu_context_save(fpu_context_t *fctx) |
41 | { |
41 | { |
42 | asm volatile ( |
42 | asm volatile ( |
43 | "std %%f0, %0\n" |
43 | "std %%f0, %0\n" |
44 | "std %%f2, %1\n" |
44 | "std %%f2, %1\n" |
45 | "std %%f4, %2\n" |
45 | "std %%f4, %2\n" |
46 | "std %%f6, %3\n" |
46 | "std %%f6, %3\n" |
47 | "std %%f8, %4\n" |
47 | "std %%f8, %4\n" |
48 | "std %%f10, %5\n" |
48 | "std %%f10, %5\n" |
49 | "std %%f12, %6\n" |
49 | "std %%f12, %6\n" |
50 | "std %%f14, %7\n" |
50 | "std %%f14, %7\n" |
51 | "std %%f16, %8\n" |
51 | "std %%f16, %8\n" |
52 | "std %%f18, %9\n" |
52 | "std %%f18, %9\n" |
53 | "std %%f20, %10\n" |
53 | "std %%f20, %10\n" |
54 | "std %%f22, %11\n" |
54 | "std %%f22, %11\n" |
55 | "std %%f24, %12\n" |
55 | "std %%f24, %12\n" |
56 | "std %%f26, %13\n" |
56 | "std %%f26, %13\n" |
57 | "std %%f28, %14\n" |
57 | "std %%f28, %14\n" |
58 | "std %%f30, %15\n" |
58 | "std %%f30, %15\n" |
59 | : "=m" (fctx->d[0]), "=m" (fctx->d[1]), "=m" (fctx->d[2]), "=m" (fctx->d[3]), |
59 | : "=m" (fctx->d[0]), "=m" (fctx->d[1]), "=m" (fctx->d[2]), "=m" (fctx->d[3]), |
60 | "=m" (fctx->d[4]), "=m" (fctx->d[5]), "=m" (fctx->d[6]), "=m" (fctx->d[7]), |
60 | "=m" (fctx->d[4]), "=m" (fctx->d[5]), "=m" (fctx->d[6]), "=m" (fctx->d[7]), |
61 | "=m" (fctx->d[8]), "=m" (fctx->d[9]), "=m" (fctx->d[10]), "=m" (fctx->d[11]), |
61 | "=m" (fctx->d[8]), "=m" (fctx->d[9]), "=m" (fctx->d[10]), "=m" (fctx->d[11]), |
62 | "=m" (fctx->d[12]), "=m" (fctx->d[13]), "=m" (fctx->d[14]), "=m" (fctx->d[15]) |
62 | "=m" (fctx->d[12]), "=m" (fctx->d[13]), "=m" (fctx->d[14]), "=m" (fctx->d[15]) |
63 | ); |
63 | ); |
64 | 64 | ||
65 | /* |
65 | /* |
66 | * We need to split loading of the floating-point registers because |
66 | * We need to split loading of the floating-point registers because |
67 | * GCC (4.1.1) can't handle more than 30 operands in one asm statement. |
67 | * GCC (4.1.1) can't handle more than 30 operands in one asm statement. |
68 | */ |
68 | */ |
69 | 69 | ||
70 | asm volatile ( |
70 | asm volatile ( |
71 | "std %%f32, %0\n" |
71 | "std %%f32, %0\n" |
72 | "std %%f34, %1\n" |
72 | "std %%f34, %1\n" |
73 | "std %%f36, %2\n" |
73 | "std %%f36, %2\n" |
74 | "std %%f38, %3\n" |
74 | "std %%f38, %3\n" |
75 | "std %%f40, %4\n" |
75 | "std %%f40, %4\n" |
76 | "std %%f42, %5\n" |
76 | "std %%f42, %5\n" |
77 | "std %%f44, %6\n" |
77 | "std %%f44, %6\n" |
78 | "std %%f46, %7\n" |
78 | "std %%f46, %7\n" |
79 | "std %%f48, %8\n" |
79 | "std %%f48, %8\n" |
80 | "std %%f50, %9\n" |
80 | "std %%f50, %9\n" |
81 | "std %%f52, %10\n" |
81 | "std %%f52, %10\n" |
82 | "std %%f54, %11\n" |
82 | "std %%f54, %11\n" |
83 | "std %%f56, %12\n" |
83 | "std %%f56, %12\n" |
84 | "std %%f58, %13\n" |
84 | "std %%f58, %13\n" |
85 | "std %%f60, %14\n" |
85 | "std %%f60, %14\n" |
86 | "std %%f62, %15\n" |
86 | "std %%f62, %15\n" |
87 | : "=m" (fctx->d[16]), "=m" (fctx->d[17]), "=m" (fctx->d[18]), "=m" (fctx->d[19]), |
87 | : "=m" (fctx->d[16]), "=m" (fctx->d[17]), "=m" (fctx->d[18]), "=m" (fctx->d[19]), |
88 | "=m" (fctx->d[20]), "=m" (fctx->d[21]), "=m" (fctx->d[22]), "=m" (fctx->d[23]), |
88 | "=m" (fctx->d[20]), "=m" (fctx->d[21]), "=m" (fctx->d[22]), "=m" (fctx->d[23]), |
89 | "=m" (fctx->d[24]), "=m" (fctx->d[25]), "=m" (fctx->d[26]), "=m" (fctx->d[27]), |
89 | "=m" (fctx->d[24]), "=m" (fctx->d[25]), "=m" (fctx->d[26]), "=m" (fctx->d[27]), |
90 | "=m" (fctx->d[28]), "=m" (fctx->d[29]), "=m" (fctx->d[30]), "=m" (fctx->d[31]) |
90 | "=m" (fctx->d[28]), "=m" (fctx->d[29]), "=m" (fctx->d[30]), "=m" (fctx->d[31]) |
91 | ); |
91 | ); |
92 | 92 | ||
93 | asm volatile ("stx %%fsr, %0\n" : "=m" (fctx->fsr)); |
93 | asm volatile ("stx %%fsr, %0\n" : "=m" (fctx->fsr)); |
94 | } |
94 | } |
95 | 95 | ||
96 | void fpu_context_restore(fpu_context_t *fctx) |
96 | void fpu_context_restore(fpu_context_t *fctx) |
97 | { |
97 | { |
98 | asm volatile ( |
98 | asm volatile ( |
99 | "ldd %0, %%f0\n" |
99 | "ldd %0, %%f0\n" |
100 | "ldd %1, %%f2\n" |
100 | "ldd %1, %%f2\n" |
101 | "ldd %2, %%f4\n" |
101 | "ldd %2, %%f4\n" |
102 | "ldd %3, %%f6\n" |
102 | "ldd %3, %%f6\n" |
103 | "ldd %4, %%f8\n" |
103 | "ldd %4, %%f8\n" |
104 | "ldd %5, %%f10\n" |
104 | "ldd %5, %%f10\n" |
105 | "ldd %6, %%f12\n" |
105 | "ldd %6, %%f12\n" |
106 | "ldd %7, %%f14\n" |
106 | "ldd %7, %%f14\n" |
107 | "ldd %8, %%f16\n" |
107 | "ldd %8, %%f16\n" |
108 | "ldd %9, %%f18\n" |
108 | "ldd %9, %%f18\n" |
109 | "ldd %10, %%f20\n" |
109 | "ldd %10, %%f20\n" |
110 | "ldd %11, %%f22\n" |
110 | "ldd %11, %%f22\n" |
111 | "ldd %12, %%f24\n" |
111 | "ldd %12, %%f24\n" |
112 | "ldd %13, %%f26\n" |
112 | "ldd %13, %%f26\n" |
113 | "ldd %14, %%f28\n" |
113 | "ldd %14, %%f28\n" |
114 | "ldd %15, %%f30\n" |
114 | "ldd %15, %%f30\n" |
115 | : |
115 | : |
116 | : "m" (fctx->d[0]), "m" (fctx->d[1]), "m" (fctx->d[2]), "m" (fctx->d[3]), |
116 | : "m" (fctx->d[0]), "m" (fctx->d[1]), "m" (fctx->d[2]), "m" (fctx->d[3]), |
117 | "m" (fctx->d[4]), "m" (fctx->d[5]), "m" (fctx->d[6]), "m" (fctx->d[7]), |
117 | "m" (fctx->d[4]), "m" (fctx->d[5]), "m" (fctx->d[6]), "m" (fctx->d[7]), |
118 | "m" (fctx->d[8]), "m" (fctx->d[9]), "m" (fctx->d[10]), "m" (fctx->d[11]), |
118 | "m" (fctx->d[8]), "m" (fctx->d[9]), "m" (fctx->d[10]), "m" (fctx->d[11]), |
119 | "m" (fctx->d[12]), "m" (fctx->d[13]), "m" (fctx->d[14]), "m" (fctx->d[15]) |
119 | "m" (fctx->d[12]), "m" (fctx->d[13]), "m" (fctx->d[14]), "m" (fctx->d[15]) |
120 | ); |
120 | ); |
121 | 121 | ||
122 | /* |
122 | /* |
123 | * We need to split loading of the floating-point registers because |
123 | * We need to split loading of the floating-point registers because |
124 | * GCC (4.1.1) can't handle more than 30 operands in one asm statement. |
124 | * GCC (4.1.1) can't handle more than 30 operands in one asm statement. |
125 | */ |
125 | */ |
126 | 126 | ||
127 | asm volatile ( |
127 | asm volatile ( |
128 | "ldd %0, %%f32\n" |
128 | "ldd %0, %%f32\n" |
129 | "ldd %1, %%f34\n" |
129 | "ldd %1, %%f34\n" |
130 | "ldd %2, %%f36\n" |
130 | "ldd %2, %%f36\n" |
131 | "ldd %3, %%f38\n" |
131 | "ldd %3, %%f38\n" |
132 | "ldd %4, %%f40\n" |
132 | "ldd %4, %%f40\n" |
133 | "ldd %5, %%f42\n" |
133 | "ldd %5, %%f42\n" |
134 | "ldd %6, %%f44\n" |
134 | "ldd %6, %%f44\n" |
135 | "ldd %7, %%f46\n" |
135 | "ldd %7, %%f46\n" |
136 | "ldd %8, %%f48\n" |
136 | "ldd %8, %%f48\n" |
137 | "ldd %9, %%f50\n" |
137 | "ldd %9, %%f50\n" |
138 | "ldd %10, %%f52\n" |
138 | "ldd %10, %%f52\n" |
139 | "ldd %11, %%f54\n" |
139 | "ldd %11, %%f54\n" |
140 | "ldd %12, %%f56\n" |
140 | "ldd %12, %%f56\n" |
141 | "ldd %13, %%f58\n" |
141 | "ldd %13, %%f58\n" |
142 | "ldd %14, %%f60\n" |
142 | "ldd %14, %%f60\n" |
143 | "ldd %15, %%f62\n" |
143 | "ldd %15, %%f62\n" |
144 | : |
144 | : |
145 | : "m" (fctx->d[16]), "m" (fctx->d[17]), "m" (fctx->d[18]), "m" (fctx->d[19]), |
145 | : "m" (fctx->d[16]), "m" (fctx->d[17]), "m" (fctx->d[18]), "m" (fctx->d[19]), |
146 | "m" (fctx->d[20]), "m" (fctx->d[21]), "m" (fctx->d[22]), "m" (fctx->d[23]), |
146 | "m" (fctx->d[20]), "m" (fctx->d[21]), "m" (fctx->d[22]), "m" (fctx->d[23]), |
147 | "m" (fctx->d[24]), "m" (fctx->d[25]), "m" (fctx->d[26]), "m" (fctx->d[27]), |
147 | "m" (fctx->d[24]), "m" (fctx->d[25]), "m" (fctx->d[26]), "m" (fctx->d[27]), |
148 | "m" (fctx->d[28]), "m" (fctx->d[29]), "m" (fctx->d[30]), "m" (fctx->d[31]) |
148 | "m" (fctx->d[28]), "m" (fctx->d[29]), "m" (fctx->d[30]), "m" (fctx->d[31]) |
149 | ); |
149 | ); |
150 | 150 | ||
151 | asm volatile ("ldx %0, %%fsr\n" : : "m" (fctx->fsr)); |
151 | asm volatile ("ldx %0, %%fsr\n" : : "m" (fctx->fsr)); |
152 | } |
152 | } |
153 | 153 | ||
154 | void fpu_enable(void) |
154 | void fpu_enable(void) |
155 | { |
155 | { |
156 | pstate_reg_t pstate; |
156 | pstate_reg_t pstate; |
157 | 157 | ||
158 | pstate.value = pstate_read(); |
158 | pstate.value = pstate_read(); |
159 | pstate.pef = true; |
159 | pstate.pef = true; |
160 | pstate_write(pstate.value); |
160 | pstate_write(pstate.value); |
161 | } |
161 | } |
162 | 162 | ||
163 | void fpu_disable(void) |
163 | void fpu_disable(void) |
164 | { |
164 | { |
165 | pstate_reg_t pstate; |
165 | pstate_reg_t pstate; |
166 | 166 | ||
167 | pstate.value = pstate_read(); |
167 | pstate.value = pstate_read(); |
168 | pstate.pef = false; |
168 | pstate.pef = false; |
169 | pstate_write(pstate.value); |
169 | pstate_write(pstate.value); |
170 | } |
170 | } |
171 | 171 | ||
172 | void fpu_init(void) |
172 | void fpu_init(void) |
173 | { |
173 | { |
174 | fpu_enable(); |
174 | fpu_enable(); |
175 | } |
175 | } |
176 | 176 | ||
177 | /** @} |
177 | /** @} |
178 | */ |
178 | */ |
179 | 179 |