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1 | /* |
1 | /* |
2 | * Copyright (c) 2005 Jakub Jermar |
2 | * Copyright (c) 2005 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup sparc64mm |
29 | /** @addtogroup sparc64mm |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | */ |
33 | */ |
34 | 34 | ||
35 | #ifndef KERN_sparc64_TLB_H_ |
35 | #ifndef KERN_sparc64_TLB_H_ |
36 | #define KERN_sparc64_TLB_H_ |
36 | #define KERN_sparc64_TLB_H_ |
37 | 37 | ||
38 | #if defined (US) |
38 | #if defined (US) |
39 | #define ITLB_ENTRY_COUNT 64 |
39 | #define ITLB_ENTRY_COUNT 64 |
40 | #define DTLB_ENTRY_COUNT 64 |
40 | #define DTLB_ENTRY_COUNT 64 |
41 | #define DTLB_MAX_LOCKED_ENTRIES DTLB_ENTRY_COUNT |
41 | #define DTLB_MAX_LOCKED_ENTRIES DTLB_ENTRY_COUNT |
42 | #endif |
42 | #endif |
43 | 43 | ||
44 | /** TLB_DSMALL is the only of the three DMMUs that can hold locked entries. */ |
44 | /** TLB_DSMALL is the only of the three DMMUs that can hold locked entries. */ |
45 | #if defined (US3) |
45 | #if defined (US3) |
46 | #define DTLB_MAX_LOCKED_ENTRIES 16 |
46 | #define DTLB_MAX_LOCKED_ENTRIES 16 |
47 | #endif |
47 | #endif |
48 | 48 | ||
49 | #define MEM_CONTEXT_KERNEL 0 |
49 | #define MEM_CONTEXT_KERNEL 0 |
50 | #define MEM_CONTEXT_TEMP 1 |
50 | #define MEM_CONTEXT_TEMP 1 |
51 | 51 | ||
52 | /** Page sizes. */ |
52 | /** Page sizes. */ |
53 | #define PAGESIZE_8K 0 |
53 | #define PAGESIZE_8K 0 |
54 | #define PAGESIZE_64K 1 |
54 | #define PAGESIZE_64K 1 |
55 | #define PAGESIZE_512K 2 |
55 | #define PAGESIZE_512K 2 |
56 | #define PAGESIZE_4M 3 |
56 | #define PAGESIZE_4M 3 |
57 | 57 | ||
58 | /** Bit width of the TLB-locked portion of kernel address space. */ |
58 | /** Bit width of the TLB-locked portion of kernel address space. */ |
59 | #define KERNEL_PAGE_WIDTH 22 /* 4M */ |
59 | #define KERNEL_PAGE_WIDTH 22 /* 4M */ |
60 | 60 | ||
61 | /* TLB Demap Operation types. */ |
61 | /* TLB Demap Operation types. */ |
62 | #define TLB_DEMAP_PAGE 0 |
62 | #define TLB_DEMAP_PAGE 0 |
63 | #define TLB_DEMAP_CONTEXT 1 |
63 | #define TLB_DEMAP_CONTEXT 1 |
64 | #if defined (US3) |
64 | #if defined (US3) |
65 | #define TLB_DEMAP_ALL 2 |
65 | #define TLB_DEMAP_ALL 2 |
66 | #endif |
66 | #endif |
67 | 67 | ||
68 | #define TLB_DEMAP_TYPE_SHIFT 6 |
68 | #define TLB_DEMAP_TYPE_SHIFT 6 |
69 | 69 | ||
70 | /* TLB Demap Operation Context register encodings. */ |
70 | /* TLB Demap Operation Context register encodings. */ |
71 | #define TLB_DEMAP_PRIMARY 0 |
71 | #define TLB_DEMAP_PRIMARY 0 |
72 | #define TLB_DEMAP_SECONDARY 1 |
72 | #define TLB_DEMAP_SECONDARY 1 |
73 | #define TLB_DEMAP_NUCLEUS 2 |
73 | #define TLB_DEMAP_NUCLEUS 2 |
74 | 74 | ||
75 | /* There are more TLBs in one MMU in US3, their codes are defined here. */ |
75 | /* There are more TLBs in one MMU in US3, their codes are defined here. */ |
76 | #if defined (US3) |
76 | #if defined (US3) |
77 | /* D-MMU: one small (16-entry) TLB and two big (512-entry) TLBs */ |
77 | /* D-MMU: one small (16-entry) TLB and two big (512-entry) TLBs */ |
78 | #define TLB_DSMALL 0 |
78 | #define TLB_DSMALL 0 |
79 | #define TLB_DBIG_0 2 |
79 | #define TLB_DBIG_0 2 |
80 | #define TLB_DBIG_1 3 |
80 | #define TLB_DBIG_1 3 |
81 | 81 | ||
82 | /* I-MMU: one small (16-entry) TLB and one big TLB */ |
82 | /* I-MMU: one small (16-entry) TLB and one big TLB */ |
83 | #define TLB_ISMALL 0 |
83 | #define TLB_ISMALL 0 |
84 | #define TLB_IBIG 2 |
84 | #define TLB_IBIG 2 |
85 | #endif |
85 | #endif |
86 | 86 | ||
87 | #define TLB_DEMAP_CONTEXT_SHIFT 4 |
87 | #define TLB_DEMAP_CONTEXT_SHIFT 4 |
88 | 88 | ||
89 | /* TLB Tag Access shifts */ |
89 | /* TLB Tag Access shifts */ |
90 | #define TLB_TAG_ACCESS_CONTEXT_SHIFT 0 |
90 | #define TLB_TAG_ACCESS_CONTEXT_SHIFT 0 |
91 | #define TLB_TAG_ACCESS_CONTEXT_MASK ((1 << 13) - 1) |
91 | #define TLB_TAG_ACCESS_CONTEXT_MASK ((1 << 13) - 1) |
92 | #define TLB_TAG_ACCESS_VPN_SHIFT 13 |
92 | #define TLB_TAG_ACCESS_VPN_SHIFT 13 |
93 | 93 | ||
94 | #ifndef __ASM__ |
94 | #ifndef __ASM__ |
95 | 95 | ||
96 | #include <arch/mm/tte.h> |
96 | #include <arch/mm/tte.h> |
97 | #include <arch/mm/mmu.h> |
97 | #include <arch/mm/mmu.h> |
98 | #include <arch/mm/page.h> |
98 | #include <arch/mm/page.h> |
99 | #include <arch/asm.h> |
99 | #include <arch/asm.h> |
100 | #include <arch/barrier.h> |
100 | #include <arch/barrier.h> |
101 | #include <arch/types.h> |
101 | #include <arch/types.h> |
102 | #include <arch/register.h> |
102 | #include <arch/register.h> |
103 | #include <arch/cpu.h> |
103 | #include <arch/cpu.h> |
104 | 104 | ||
105 | union tlb_context_reg { |
105 | union tlb_context_reg { |
106 | uint64_t v; |
106 | uint64_t v; |
107 | struct { |
107 | struct { |
108 | unsigned long : 51; |
108 | unsigned long : 51; |
109 | unsigned context : 13; /**< Context/ASID. */ |
109 | unsigned context : 13; /**< Context/ASID. */ |
110 | } __attribute__ ((packed)); |
110 | } __attribute__ ((packed)); |
111 | }; |
111 | }; |
112 | typedef union tlb_context_reg tlb_context_reg_t; |
112 | typedef union tlb_context_reg tlb_context_reg_t; |
113 | 113 | ||
114 | /** I-/D-TLB Data In/Access Register type. */ |
114 | /** I-/D-TLB Data In/Access Register type. */ |
115 | typedef tte_data_t tlb_data_t; |
115 | typedef tte_data_t tlb_data_t; |
116 | 116 | ||
117 | /** I-/D-TLB Data Access Address in Alternate Space. */ |
117 | /** I-/D-TLB Data Access Address in Alternate Space. */ |
118 | 118 | ||
119 | #if defined (US) |
119 | #if defined (US) |
120 | 120 | ||
121 | union tlb_data_access_addr { |
121 | union tlb_data_access_addr { |
122 | uint64_t value; |
122 | uint64_t value; |
123 | struct { |
123 | struct { |
124 | uint64_t : 55; |
124 | uint64_t : 55; |
125 | unsigned tlb_entry : 6; |
125 | unsigned tlb_entry : 6; |
126 | unsigned : 3; |
126 | unsigned : 3; |
127 | } __attribute__ ((packed)); |
127 | } __attribute__ ((packed)); |
128 | }; |
128 | }; |
129 | typedef union tlb_data_access_addr dtlb_data_access_addr_t; |
129 | typedef union tlb_data_access_addr dtlb_data_access_addr_t; |
130 | typedef union tlb_data_access_addr dtlb_tag_read_addr_t; |
130 | typedef union tlb_data_access_addr dtlb_tag_read_addr_t; |
131 | typedef union tlb_data_access_addr itlb_data_access_addr_t; |
131 | typedef union tlb_data_access_addr itlb_data_access_addr_t; |
132 | typedef union tlb_data_access_addr itlb_tag_read_addr_t; |
132 | typedef union tlb_data_access_addr itlb_tag_read_addr_t; |
133 | 133 | ||
134 | #elif defined (US3) |
134 | #elif defined (US3) |
135 | 135 | ||
136 | /* |
136 | /* |
137 | * In US3, I-MMU and D-MMU have different formats of the data |
137 | * In US3, I-MMU and D-MMU have different formats of the data |
138 | * access register virtual address. In the corresponding |
138 | * access register virtual address. In the corresponding |
139 | * structures the member variable for the entry number is |
139 | * structures the member variable for the entry number is |
140 | * called "local_tlb_entry" - it contrast with the "tlb_entry" |
140 | * called "local_tlb_entry" - it contrast with the "tlb_entry" |
141 | * for the US data access register VA structure. The rationale |
141 | * for the US data access register VA structure. The rationale |
142 | * behind this is to prevent careless mistakes in the code |
142 | * behind this is to prevent careless mistakes in the code |
143 | * caused by setting only the entry number and not the TLB |
143 | * caused by setting only the entry number and not the TLB |
144 | * number in the US3 code (when taking the code from US). |
144 | * number in the US3 code (when taking the code from US). |
145 | */ |
145 | */ |
146 | 146 | ||
147 | union dtlb_data_access_addr { |
147 | union dtlb_data_access_addr { |
148 | uint64_t value; |
148 | uint64_t value; |
149 | struct { |
149 | struct { |
150 | uint64_t : 45; |
150 | uint64_t : 45; |
151 | unsigned : 1; |
151 | unsigned : 1; |
152 | unsigned tlb_number : 2; |
152 | unsigned tlb_number : 2; |
153 | unsigned : 4; |
153 | unsigned : 4; |
154 | unsigned local_tlb_entry : 9; |
154 | unsigned local_tlb_entry : 9; |
155 | unsigned : 3; |
155 | unsigned : 3; |
156 | } __attribute__ ((packed)); |
156 | } __attribute__ ((packed)); |
157 | }; |
157 | }; |
158 | typedef union dtlb_data_access_addr dtlb_data_access_addr_t; |
158 | typedef union dtlb_data_access_addr dtlb_data_access_addr_t; |
159 | typedef union dtlb_data_access_addr dtlb_tag_read_addr_t; |
159 | typedef union dtlb_data_access_addr dtlb_tag_read_addr_t; |
160 | 160 | ||
161 | union itlb_data_access_addr { |
161 | union itlb_data_access_addr { |
162 | uint64_t value; |
162 | uint64_t value; |
163 | struct { |
163 | struct { |
164 | uint64_t : 45; |
164 | uint64_t : 45; |
165 | unsigned : 1; |
165 | unsigned : 1; |
166 | unsigned tlb_number : 2; |
166 | unsigned tlb_number : 2; |
167 | unsigned : 6; |
167 | unsigned : 6; |
168 | unsigned local_tlb_entry : 7; |
168 | unsigned local_tlb_entry : 7; |
169 | unsigned : 3; |
169 | unsigned : 3; |
170 | } __attribute__ ((packed)); |
170 | } __attribute__ ((packed)); |
171 | }; |
171 | }; |
172 | typedef union itlb_data_access_addr itlb_data_access_addr_t; |
172 | typedef union itlb_data_access_addr itlb_data_access_addr_t; |
173 | typedef union itlb_data_access_addr itlb_tag_read_addr_t; |
173 | typedef union itlb_data_access_addr itlb_tag_read_addr_t; |
174 | 174 | ||
175 | #endif |
175 | #endif |
176 | 176 | ||
177 | /** I-/D-TLB Tag Read Register. */ |
177 | /** I-/D-TLB Tag Read Register. */ |
178 | union tlb_tag_read_reg { |
178 | union tlb_tag_read_reg { |
179 | // TODO have a look at how non-8kB pages will be treated |
- | |
180 | uint64_t value; |
179 | uint64_t value; |
181 | struct { |
180 | struct { |
182 | uint64_t vpn : 51; /**< Virtual Address bits 63:13. */ |
181 | uint64_t vpn : 51; /**< Virtual Address bits 63:13. */ |
183 | unsigned context : 13; /**< Context identifier. */ |
182 | unsigned context : 13; /**< Context identifier. */ |
184 | } __attribute__ ((packed)); |
183 | } __attribute__ ((packed)); |
185 | }; |
184 | }; |
186 | typedef union tlb_tag_read_reg tlb_tag_read_reg_t; |
185 | typedef union tlb_tag_read_reg tlb_tag_read_reg_t; |
187 | typedef union tlb_tag_read_reg tlb_tag_access_reg_t; |
186 | typedef union tlb_tag_read_reg tlb_tag_access_reg_t; |
188 | 187 | ||
189 | 188 | ||
190 | /** TLB Demap Operation Address. */ |
189 | /** TLB Demap Operation Address. */ |
191 | union tlb_demap_addr { |
190 | union tlb_demap_addr { |
192 | uint64_t value; |
191 | uint64_t value; |
193 | struct { |
192 | struct { |
194 | uint64_t vpn: 51; /**< Virtual Address bits 63:13. */ |
193 | uint64_t vpn: 51; /**< Virtual Address bits 63:13. */ |
195 | #if defined (US) |
194 | #if defined (US) |
196 | unsigned : 6; /**< Ignored. */ |
195 | unsigned : 6; /**< Ignored. */ |
197 | unsigned type : 1; /**< The type of demap operation. */ |
196 | unsigned type : 1; /**< The type of demap operation. */ |
198 | #elif defined (US3) |
197 | #elif defined (US3) |
199 | unsigned : 5; /**< Ignored. */ |
198 | unsigned : 5; /**< Ignored. */ |
200 | unsigned type: 2; /**< The type of demap operation. */ |
199 | unsigned type: 2; /**< The type of demap operation. */ |
201 | #endif |
200 | #endif |
202 | unsigned context : 2; /**< Context register selection. */ |
201 | unsigned context : 2; /**< Context register selection. */ |
203 | unsigned : 4; /**< Zero. */ |
202 | unsigned : 4; /**< Zero. */ |
204 | } __attribute__ ((packed)); |
203 | } __attribute__ ((packed)); |
205 | }; |
204 | }; |
206 | typedef union tlb_demap_addr tlb_demap_addr_t; |
205 | typedef union tlb_demap_addr tlb_demap_addr_t; |
207 | 206 | ||
208 | /** TLB Synchronous Fault Status Register. */ |
207 | /** TLB Synchronous Fault Status Register. */ |
209 | union tlb_sfsr_reg { |
208 | union tlb_sfsr_reg { |
210 | uint64_t value; |
209 | uint64_t value; |
211 | struct { |
210 | struct { |
212 | #if defined (US) |
211 | #if defined (US) |
213 | unsigned long : 40; /**< Implementation dependent. */ |
212 | unsigned long : 40; /**< Implementation dependent. */ |
214 | unsigned asi : 8; /**< ASI. */ |
213 | unsigned asi : 8; /**< ASI. */ |
215 | unsigned : 2; |
214 | unsigned : 2; |
216 | unsigned ft : 7; /**< Fault type. */ |
215 | unsigned ft : 7; /**< Fault type. */ |
217 | #elif defined (US3) |
216 | #elif defined (US3) |
218 | unsigned long : 39; /**< Implementation dependent. */ |
217 | unsigned long : 39; /**< Implementation dependent. */ |
219 | unsigned nf : 1; /**< Non-faulting load. */ |
218 | unsigned nf : 1; /**< Non-faulting load. */ |
220 | unsigned asi : 8; /**< ASI. */ |
219 | unsigned asi : 8; /**< ASI. */ |
221 | unsigned tm : 1; /**< I-TLB miss. */ |
220 | unsigned tm : 1; /**< I-TLB miss. */ |
222 | unsigned : 3; /**< Reserved. */ |
221 | unsigned : 3; /**< Reserved. */ |
223 | unsigned ft : 5; /**< Fault type. */ |
222 | unsigned ft : 5; /**< Fault type. */ |
224 | #endif |
223 | #endif |
225 | unsigned e : 1; /**< Side-effect bit. */ |
224 | unsigned e : 1; /**< Side-effect bit. */ |
226 | unsigned ct : 2; /**< Context Register selection. */ |
225 | unsigned ct : 2; /**< Context Register selection. */ |
227 | unsigned pr : 1; /**< Privilege bit. */ |
226 | unsigned pr : 1; /**< Privilege bit. */ |
228 | unsigned w : 1; /**< Write bit. */ |
227 | unsigned w : 1; /**< Write bit. */ |
229 | unsigned ow : 1; /**< Overwrite bit. */ |
228 | unsigned ow : 1; /**< Overwrite bit. */ |
230 | unsigned fv : 1; /**< Fault Valid bit. */ |
229 | unsigned fv : 1; /**< Fault Valid bit. */ |
231 | } __attribute__ ((packed)); |
230 | } __attribute__ ((packed)); |
232 | }; |
231 | }; |
233 | typedef union tlb_sfsr_reg tlb_sfsr_reg_t; |
232 | typedef union tlb_sfsr_reg tlb_sfsr_reg_t; |
234 | 233 | ||
235 | #if defined (US3) |
234 | #if defined (US3) |
236 | 235 | ||
237 | /* |
236 | /* |
238 | * Functions for determining the number of entries in TLBs. They either return |
237 | * Functions for determining the number of entries in TLBs. They either return |
239 | * a constant value or a value based on the CPU autodetection. |
238 | * a constant value or a value based on the CPU autodetection. |
240 | */ |
239 | */ |
241 | 240 | ||
242 | /** |
241 | /** |
243 | * Determine the number od entries in the DMMU's small TLB. |
242 | * Determine the number od entries in the DMMU's small TLB. |
244 | */ |
243 | */ |
245 | static inline uint16_t tlb_dsmall_size(void) |
244 | static inline uint16_t tlb_dsmall_size(void) |
246 | { |
245 | { |
247 | return 16; |
246 | return 16; |
248 | } |
247 | } |
249 | 248 | ||
250 | /** |
249 | /** |
251 | * Determine the number od entries in each DMMU's big TLB. |
250 | * Determine the number od entries in each DMMU's big TLB. |
252 | */ |
251 | */ |
253 | static inline uint16_t tlb_dbig_size(void) |
252 | static inline uint16_t tlb_dbig_size(void) |
254 | { |
253 | { |
255 | return 512; |
254 | return 512; |
256 | } |
255 | } |
257 | 256 | ||
258 | /** |
257 | /** |
259 | * Determine the number od entries in the IMMU's small TLB. |
258 | * Determine the number od entries in the IMMU's small TLB. |
260 | */ |
259 | */ |
261 | static inline uint16_t tlb_ismall_size(void) |
260 | static inline uint16_t tlb_ismall_size(void) |
262 | { |
261 | { |
263 | return 16; |
262 | return 16; |
264 | } |
263 | } |
265 | 264 | ||
266 | /** |
265 | /** |
267 | * Determine the number od entries in the IMMU's big TLB. |
266 | * Determine the number od entries in the IMMU's big TLB. |
268 | */ |
267 | */ |
269 | static inline uint16_t tlb_ibig_size(void) |
268 | static inline uint16_t tlb_ibig_size(void) |
270 | { |
269 | { |
271 | if (((ver_reg_t) ver_read()).impl == IMPL_ULTRASPARCIV_PLUS) |
270 | if (((ver_reg_t) ver_read()).impl == IMPL_ULTRASPARCIV_PLUS) |
272 | return 512; |
271 | return 512; |
273 | else |
272 | else |
274 | return 128; |
273 | return 128; |
275 | } |
274 | } |
276 | 275 | ||
277 | #endif |
276 | #endif |
278 | 277 | ||
279 | /** Read MMU Primary Context Register. |
278 | /** Read MMU Primary Context Register. |
280 | * |
279 | * |
281 | * @return Current value of Primary Context Register. |
280 | * @return Current value of Primary Context Register. |
282 | */ |
281 | */ |
283 | static inline uint64_t mmu_primary_context_read(void) |
282 | static inline uint64_t mmu_primary_context_read(void) |
284 | { |
283 | { |
285 | return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG); |
284 | return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG); |
286 | } |
285 | } |
287 | 286 | ||
288 | /** Write MMU Primary Context Register. |
287 | /** Write MMU Primary Context Register. |
289 | * |
288 | * |
290 | * @param v New value of Primary Context Register. |
289 | * @param v New value of Primary Context Register. |
291 | */ |
290 | */ |
292 | static inline void mmu_primary_context_write(uint64_t v) |
291 | static inline void mmu_primary_context_write(uint64_t v) |
293 | { |
292 | { |
294 | asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v); |
293 | asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v); |
295 | flush_pipeline(); |
294 | flush_pipeline(); |
296 | } |
295 | } |
297 | 296 | ||
298 | /** Read MMU Secondary Context Register. |
297 | /** Read MMU Secondary Context Register. |
299 | * |
298 | * |
300 | * @return Current value of Secondary Context Register. |
299 | * @return Current value of Secondary Context Register. |
301 | */ |
300 | */ |
302 | static inline uint64_t mmu_secondary_context_read(void) |
301 | static inline uint64_t mmu_secondary_context_read(void) |
303 | { |
302 | { |
304 | return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG); |
303 | return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG); |
305 | } |
304 | } |
306 | 305 | ||
307 | /** Write MMU Primary Context Register. |
306 | /** Write MMU Primary Context Register. |
308 | * |
307 | * |
309 | * @param v New value of Primary Context Register. |
308 | * @param v New value of Primary Context Register. |
310 | */ |
309 | */ |
311 | static inline void mmu_secondary_context_write(uint64_t v) |
310 | static inline void mmu_secondary_context_write(uint64_t v) |
312 | { |
311 | { |
313 | asi_u64_write(ASI_DMMU, VA_SECONDARY_CONTEXT_REG, v); |
312 | asi_u64_write(ASI_DMMU, VA_SECONDARY_CONTEXT_REG, v); |
314 | flush_pipeline(); |
313 | flush_pipeline(); |
315 | } |
314 | } |
316 | 315 | ||
317 | #if defined (US) |
316 | #if defined (US) |
318 | 317 | ||
319 | /** Read IMMU TLB Data Access Register. |
318 | /** Read IMMU TLB Data Access Register. |
320 | * |
319 | * |
321 | * @param entry TLB Entry index. |
320 | * @param entry TLB Entry index. |
322 | * |
321 | * |
323 | * @return Current value of specified IMMU TLB Data Access Register. |
322 | * @return Current value of specified IMMU TLB Data Access Register. |
324 | */ |
323 | */ |
325 | static inline uint64_t itlb_data_access_read(index_t entry) |
324 | static inline uint64_t itlb_data_access_read(index_t entry) |
326 | { |
325 | { |
327 | itlb_data_access_addr_t reg; |
326 | itlb_data_access_addr_t reg; |
328 | 327 | ||
329 | reg.value = 0; |
328 | reg.value = 0; |
330 | reg.tlb_entry = entry; |
329 | reg.tlb_entry = entry; |
331 | return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value); |
330 | return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value); |
332 | } |
331 | } |
333 | 332 | ||
334 | /** Write IMMU TLB Data Access Register. |
333 | /** Write IMMU TLB Data Access Register. |
335 | * |
334 | * |
336 | * @param entry TLB Entry index. |
335 | * @param entry TLB Entry index. |
337 | * @param value Value to be written. |
336 | * @param value Value to be written. |
338 | */ |
337 | */ |
339 | static inline void itlb_data_access_write(index_t entry, uint64_t value) |
338 | static inline void itlb_data_access_write(index_t entry, uint64_t value) |
340 | { |
339 | { |
341 | itlb_data_access_addr_t reg; |
340 | itlb_data_access_addr_t reg; |
342 | 341 | ||
343 | reg.value = 0; |
342 | reg.value = 0; |
344 | reg.tlb_entry = entry; |
343 | reg.tlb_entry = entry; |
345 | asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value); |
344 | asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value); |
346 | flush_pipeline(); |
345 | flush_pipeline(); |
347 | } |
346 | } |
348 | 347 | ||
349 | /** Read DMMU TLB Data Access Register. |
348 | /** Read DMMU TLB Data Access Register. |
350 | * |
349 | * |
351 | * @param entry TLB Entry index. |
350 | * @param entry TLB Entry index. |
352 | * |
351 | * |
353 | * @return Current value of specified DMMU TLB Data Access Register. |
352 | * @return Current value of specified DMMU TLB Data Access Register. |
354 | */ |
353 | */ |
355 | static inline uint64_t dtlb_data_access_read(index_t entry) |
354 | static inline uint64_t dtlb_data_access_read(index_t entry) |
356 | { |
355 | { |
357 | dtlb_data_access_addr_t reg; |
356 | dtlb_data_access_addr_t reg; |
358 | 357 | ||
359 | reg.value = 0; |
358 | reg.value = 0; |
360 | reg.tlb_entry = entry; |
359 | reg.tlb_entry = entry; |
361 | return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value); |
360 | return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value); |
362 | } |
361 | } |
363 | 362 | ||
364 | /** Write DMMU TLB Data Access Register. |
363 | /** Write DMMU TLB Data Access Register. |
365 | * |
364 | * |
366 | * @param entry TLB Entry index. |
365 | * @param entry TLB Entry index. |
367 | * @param value Value to be written. |
366 | * @param value Value to be written. |
368 | */ |
367 | */ |
369 | static inline void dtlb_data_access_write(index_t entry, uint64_t value) |
368 | static inline void dtlb_data_access_write(index_t entry, uint64_t value) |
370 | { |
369 | { |
371 | dtlb_data_access_addr_t reg; |
370 | dtlb_data_access_addr_t reg; |
372 | 371 | ||
373 | reg.value = 0; |
372 | reg.value = 0; |
374 | reg.tlb_entry = entry; |
373 | reg.tlb_entry = entry; |
375 | asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value); |
374 | asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value); |
376 | membar(); |
375 | membar(); |
377 | } |
376 | } |
378 | 377 | ||
379 | /** Read IMMU TLB Tag Read Register. |
378 | /** Read IMMU TLB Tag Read Register. |
380 | * |
379 | * |
381 | * @param entry TLB Entry index. |
380 | * @param entry TLB Entry index. |
382 | * |
381 | * |
383 | * @return Current value of specified IMMU TLB Tag Read Register. |
382 | * @return Current value of specified IMMU TLB Tag Read Register. |
384 | */ |
383 | */ |
385 | static inline uint64_t itlb_tag_read_read(index_t entry) |
384 | static inline uint64_t itlb_tag_read_read(index_t entry) |
386 | { |
385 | { |
387 | itlb_tag_read_addr_t tag; |
386 | itlb_tag_read_addr_t tag; |
388 | 387 | ||
389 | tag.value = 0; |
388 | tag.value = 0; |
390 | tag.tlb_entry = entry; |
389 | tag.tlb_entry = entry; |
391 | return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value); |
390 | return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value); |
392 | } |
391 | } |
393 | 392 | ||
394 | /** Read DMMU TLB Tag Read Register. |
393 | /** Read DMMU TLB Tag Read Register. |
395 | * |
394 | * |
396 | * @param entry TLB Entry index. |
395 | * @param entry TLB Entry index. |
397 | * |
396 | * |
398 | * @return Current value of specified DMMU TLB Tag Read Register. |
397 | * @return Current value of specified DMMU TLB Tag Read Register. |
399 | */ |
398 | */ |
400 | static inline uint64_t dtlb_tag_read_read(index_t entry) |
399 | static inline uint64_t dtlb_tag_read_read(index_t entry) |
401 | { |
400 | { |
402 | dtlb_tag_read_addr_t tag; |
401 | dtlb_tag_read_addr_t tag; |
403 | 402 | ||
404 | tag.value = 0; |
403 | tag.value = 0; |
405 | tag.tlb_entry = entry; |
404 | tag.tlb_entry = entry; |
406 | return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value); |
405 | return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value); |
407 | } |
406 | } |
408 | 407 | ||
409 | #elif defined (US3) |
408 | #elif defined (US3) |
410 | 409 | ||
411 | 410 | ||
412 | /** Read IMMU TLB Data Access Register. |
411 | /** Read IMMU TLB Data Access Register. |
413 | * |
412 | * |
414 | * @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG) |
413 | * @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG) |
415 | * @param entry TLB Entry index. |
414 | * @param entry TLB Entry index. |
416 | * |
415 | * |
417 | * @return Current value of specified IMMU TLB Data Access Register. |
416 | * @return Current value of specified IMMU TLB Data Access Register. |
418 | */ |
417 | */ |
419 | static inline uint64_t itlb_data_access_read(int tlb, index_t entry) |
418 | static inline uint64_t itlb_data_access_read(int tlb, index_t entry) |
420 | { |
419 | { |
421 | itlb_data_access_addr_t reg; |
420 | itlb_data_access_addr_t reg; |
422 | 421 | ||
423 | reg.value = 0; |
422 | reg.value = 0; |
424 | reg.tlb_number = tlb; |
423 | reg.tlb_number = tlb; |
425 | reg.local_tlb_entry = entry; |
424 | reg.local_tlb_entry = entry; |
426 | return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value); |
425 | return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value); |
427 | } |
426 | } |
428 | 427 | ||
429 | /** Write IMMU TLB Data Access Register. |
428 | /** Write IMMU TLB Data Access Register. |
430 | * @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG) |
429 | * @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG) |
431 | * @param entry TLB Entry index. |
430 | * @param entry TLB Entry index. |
432 | * @param value Value to be written. |
431 | * @param value Value to be written. |
433 | */ |
432 | */ |
434 | static inline void itlb_data_access_write(int tlb, index_t entry, uint64_t value) |
433 | static inline void itlb_data_access_write(int tlb, index_t entry, |
- | 434 | uint64_t value) |
|
435 | { |
435 | { |
436 | itlb_data_access_addr_t reg; |
436 | itlb_data_access_addr_t reg; |
437 | 437 | ||
438 | reg.value = 0; |
438 | reg.value = 0; |
439 | reg.tlb_number = tlb; |
439 | reg.tlb_number = tlb; |
440 | reg.local_tlb_entry = entry; |
440 | reg.local_tlb_entry = entry; |
441 | asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value); |
441 | asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value); |
442 | flush_pipeline(); |
442 | flush_pipeline(); |
443 | } |
443 | } |
444 | 444 | ||
445 | /** Read DMMU TLB Data Access Register. |
445 | /** Read DMMU TLB Data Access Register. |
446 | * |
446 | * |
447 | * @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG, TLB_DBIG) |
447 | * @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG, TLB_DBIG) |
448 | * @param entry TLB Entry index. |
448 | * @param entry TLB Entry index. |
449 | * |
449 | * |
450 | * @return Current value of specified DMMU TLB Data Access Register. |
450 | * @return Current value of specified DMMU TLB Data Access Register. |
451 | */ |
451 | */ |
452 | static inline uint64_t dtlb_data_access_read(int tlb, index_t entry) |
452 | static inline uint64_t dtlb_data_access_read(int tlb, index_t entry) |
453 | { |
453 | { |
454 | dtlb_data_access_addr_t reg; |
454 | dtlb_data_access_addr_t reg; |
455 | 455 | ||
456 | reg.value = 0; |
456 | reg.value = 0; |
457 | reg.tlb_number = tlb; |
457 | reg.tlb_number = tlb; |
458 | reg.local_tlb_entry = entry; |
458 | reg.local_tlb_entry = entry; |
459 | return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value); |
459 | return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value); |
460 | } |
460 | } |
461 | 461 | ||
462 | /** Write DMMU TLB Data Access Register. |
462 | /** Write DMMU TLB Data Access Register. |
463 | * |
463 | * |
464 | * @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1) |
464 | * @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1) |
465 | * @param entry TLB Entry index. |
465 | * @param entry TLB Entry index. |
466 | * @param value Value to be written. |
466 | * @param value Value to be written. |
467 | */ |
467 | */ |
468 | static inline void dtlb_data_access_write(int tlb, index_t entry, uint64_t value) |
468 | static inline void dtlb_data_access_write(int tlb, index_t entry, |
- | 469 | uint64_t value) |
|
469 | { |
470 | { |
470 | dtlb_data_access_addr_t reg; |
471 | dtlb_data_access_addr_t reg; |
471 | 472 | ||
472 | reg.value = 0; |
473 | reg.value = 0; |
473 | reg.tlb_number = tlb; |
474 | reg.tlb_number = tlb; |
474 | reg.local_tlb_entry = entry; |
475 | reg.local_tlb_entry = entry; |
475 | asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value); |
476 | asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value); |
476 | membar(); |
477 | membar(); |
477 | } |
478 | } |
478 | 479 | ||
479 | /** Read IMMU TLB Tag Read Register. |
480 | /** Read IMMU TLB Tag Read Register. |
480 | * |
481 | * |
481 | * @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG) |
482 | * @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG) |
482 | * @param entry TLB Entry index. |
483 | * @param entry TLB Entry index. |
483 | * |
484 | * |
484 | * @return Current value of specified IMMU TLB Tag Read Register. |
485 | * @return Current value of specified IMMU TLB Tag Read Register. |
485 | */ |
486 | */ |
486 | static inline uint64_t itlb_tag_read_read(int tlb, index_t entry) |
487 | static inline uint64_t itlb_tag_read_read(int tlb, index_t entry) |
487 | { |
488 | { |
488 | itlb_tag_read_addr_t tag; |
489 | itlb_tag_read_addr_t tag; |
489 | 490 | ||
490 | tag.value = 0; |
491 | tag.value = 0; |
491 | tag.tlb_number = tlb; |
492 | tag.tlb_number = tlb; |
492 | tag.local_tlb_entry = entry; |
493 | tag.local_tlb_entry = entry; |
493 | return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value); |
494 | return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value); |
494 | } |
495 | } |
495 | 496 | ||
496 | /** Read DMMU TLB Tag Read Register. |
497 | /** Read DMMU TLB Tag Read Register. |
497 | * |
498 | * |
498 | * @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1) |
499 | * @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1) |
499 | * @param entry TLB Entry index. |
500 | * @param entry TLB Entry index. |
500 | * |
501 | * |
501 | * @return Current value of specified DMMU TLB Tag Read Register. |
502 | * @return Current value of specified DMMU TLB Tag Read Register. |
502 | */ |
503 | */ |
503 | static inline uint64_t dtlb_tag_read_read(int tlb, index_t entry) |
504 | static inline uint64_t dtlb_tag_read_read(int tlb, index_t entry) |
504 | { |
505 | { |
505 | dtlb_tag_read_addr_t tag; |
506 | dtlb_tag_read_addr_t tag; |
506 | 507 | ||
507 | tag.value = 0; |
508 | tag.value = 0; |
508 | tag.tlb_number = tlb; |
509 | tag.tlb_number = tlb; |
509 | tag.local_tlb_entry = entry; |
510 | tag.local_tlb_entry = entry; |
510 | return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value); |
511 | return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value); |
511 | } |
512 | } |
512 | 513 | ||
513 | #endif |
514 | #endif |
514 | 515 | ||
515 | 516 | ||
516 | /** Write IMMU TLB Tag Access Register. |
517 | /** Write IMMU TLB Tag Access Register. |
517 | * |
518 | * |
518 | * @param v Value to be written. |
519 | * @param v Value to be written. |
519 | */ |
520 | */ |
520 | static inline void itlb_tag_access_write(uint64_t v) |
521 | static inline void itlb_tag_access_write(uint64_t v) |
521 | { |
522 | { |
522 | asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v); |
523 | asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v); |
523 | flush_pipeline(); |
524 | flush_pipeline(); |
524 | } |
525 | } |
525 | 526 | ||
526 | /** Read IMMU TLB Tag Access Register. |
527 | /** Read IMMU TLB Tag Access Register. |
527 | * |
528 | * |
528 | * @return Current value of IMMU TLB Tag Access Register. |
529 | * @return Current value of IMMU TLB Tag Access Register. |
529 | */ |
530 | */ |
530 | static inline uint64_t itlb_tag_access_read(void) |
531 | static inline uint64_t itlb_tag_access_read(void) |
531 | { |
532 | { |
532 | return asi_u64_read(ASI_IMMU, VA_IMMU_TAG_ACCESS); |
533 | return asi_u64_read(ASI_IMMU, VA_IMMU_TAG_ACCESS); |
533 | } |
534 | } |
534 | 535 | ||
535 | /** Write DMMU TLB Tag Access Register. |
536 | /** Write DMMU TLB Tag Access Register. |
536 | * |
537 | * |
537 | * @param v Value to be written. |
538 | * @param v Value to be written. |
538 | */ |
539 | */ |
539 | static inline void dtlb_tag_access_write(uint64_t v) |
540 | static inline void dtlb_tag_access_write(uint64_t v) |
540 | { |
541 | { |
541 | asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v); |
542 | asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v); |
542 | membar(); |
543 | membar(); |
543 | } |
544 | } |
544 | 545 | ||
545 | /** Read DMMU TLB Tag Access Register. |
546 | /** Read DMMU TLB Tag Access Register. |
546 | * |
547 | * |
547 | * @return Current value of DMMU TLB Tag Access Register. |
548 | * @return Current value of DMMU TLB Tag Access Register. |
548 | */ |
549 | */ |
549 | static inline uint64_t dtlb_tag_access_read(void) |
550 | static inline uint64_t dtlb_tag_access_read(void) |
550 | { |
551 | { |
551 | return asi_u64_read(ASI_DMMU, VA_DMMU_TAG_ACCESS); |
552 | return asi_u64_read(ASI_DMMU, VA_DMMU_TAG_ACCESS); |
552 | } |
553 | } |
553 | 554 | ||
554 | 555 | ||
555 | /** Write IMMU TLB Data in Register. |
556 | /** Write IMMU TLB Data in Register. |
556 | * |
557 | * |
557 | * @param v Value to be written. |
558 | * @param v Value to be written. |
558 | */ |
559 | */ |
559 | static inline void itlb_data_in_write(uint64_t v) |
560 | static inline void itlb_data_in_write(uint64_t v) |
560 | { |
561 | { |
561 | asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v); |
562 | asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v); |
562 | flush_pipeline(); |
563 | flush_pipeline(); |
563 | } |
564 | } |
564 | 565 | ||
565 | /** Write DMMU TLB Data in Register. |
566 | /** Write DMMU TLB Data in Register. |
566 | * |
567 | * |
567 | * @param v Value to be written. |
568 | * @param v Value to be written. |
568 | */ |
569 | */ |
569 | static inline void dtlb_data_in_write(uint64_t v) |
570 | static inline void dtlb_data_in_write(uint64_t v) |
570 | { |
571 | { |
571 | asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v); |
572 | asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v); |
572 | membar(); |
573 | membar(); |
573 | } |
574 | } |
574 | 575 | ||
575 | /** Read ITLB Synchronous Fault Status Register. |
576 | /** Read ITLB Synchronous Fault Status Register. |
576 | * |
577 | * |
577 | * @return Current content of I-SFSR register. |
578 | * @return Current content of I-SFSR register. |
578 | */ |
579 | */ |
579 | static inline uint64_t itlb_sfsr_read(void) |
580 | static inline uint64_t itlb_sfsr_read(void) |
580 | { |
581 | { |
581 | return asi_u64_read(ASI_IMMU, VA_IMMU_SFSR); |
582 | return asi_u64_read(ASI_IMMU, VA_IMMU_SFSR); |
582 | } |
583 | } |
583 | 584 | ||
584 | /** Write ITLB Synchronous Fault Status Register. |
585 | /** Write ITLB Synchronous Fault Status Register. |
585 | * |
586 | * |
586 | * @param v New value of I-SFSR register. |
587 | * @param v New value of I-SFSR register. |
587 | */ |
588 | */ |
588 | static inline void itlb_sfsr_write(uint64_t v) |
589 | static inline void itlb_sfsr_write(uint64_t v) |
589 | { |
590 | { |
590 | asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v); |
591 | asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v); |
591 | flush_pipeline(); |
592 | flush_pipeline(); |
592 | } |
593 | } |
593 | 594 | ||
594 | /** Read DTLB Synchronous Fault Status Register. |
595 | /** Read DTLB Synchronous Fault Status Register. |
595 | * |
596 | * |
596 | * @return Current content of D-SFSR register. |
597 | * @return Current content of D-SFSR register. |
597 | */ |
598 | */ |
598 | static inline uint64_t dtlb_sfsr_read(void) |
599 | static inline uint64_t dtlb_sfsr_read(void) |
599 | { |
600 | { |
600 | return asi_u64_read(ASI_DMMU, VA_DMMU_SFSR); |
601 | return asi_u64_read(ASI_DMMU, VA_DMMU_SFSR); |
601 | } |
602 | } |
602 | 603 | ||
603 | /** Write DTLB Synchronous Fault Status Register. |
604 | /** Write DTLB Synchronous Fault Status Register. |
604 | * |
605 | * |
605 | * @param v New value of D-SFSR register. |
606 | * @param v New value of D-SFSR register. |
606 | */ |
607 | */ |
607 | static inline void dtlb_sfsr_write(uint64_t v) |
608 | static inline void dtlb_sfsr_write(uint64_t v) |
608 | { |
609 | { |
609 | asi_u64_write(ASI_DMMU, VA_DMMU_SFSR, v); |
610 | asi_u64_write(ASI_DMMU, VA_DMMU_SFSR, v); |
610 | membar(); |
611 | membar(); |
611 | } |
612 | } |
612 | 613 | ||
613 | /** Read DTLB Synchronous Fault Address Register. |
614 | /** Read DTLB Synchronous Fault Address Register. |
614 | * |
615 | * |
615 | * @return Current content of D-SFAR register. |
616 | * @return Current content of D-SFAR register. |
616 | */ |
617 | */ |
617 | static inline uint64_t dtlb_sfar_read(void) |
618 | static inline uint64_t dtlb_sfar_read(void) |
618 | { |
619 | { |
619 | return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR); |
620 | return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR); |
620 | } |
621 | } |
621 | 622 | ||
622 | /** Perform IMMU TLB Demap Operation. |
623 | /** Perform IMMU TLB Demap Operation. |
623 | * |
624 | * |
624 | * @param type |
625 | * @param type |
625 | * Selects between context and page demap |
626 | * Selects between context and page demap |
626 | * (and entire MMU demap on US3). |
627 | * (and entire MMU demap on US3). |
627 | * @param context_encoding Specifies which Context register has Context ID for |
628 | * @param context_encoding Specifies which Context register has Context ID for |
628 | * demap. |
629 | * demap. |
629 | * @param page Address which is on the page to be demapped. |
630 | * @param page Address which is on the page to be demapped. |
630 | */ |
631 | */ |
631 | static inline void itlb_demap(int type, int context_encoding, uintptr_t page) |
632 | static inline void itlb_demap(int type, int context_encoding, uintptr_t page) |
632 | { |
633 | { |
633 | tlb_demap_addr_t da; |
634 | tlb_demap_addr_t da; |
634 | page_address_t pg; |
635 | page_address_t pg; |
635 | 636 | ||
636 | da.value = 0; |
637 | da.value = 0; |
637 | pg.address = page; |
638 | pg.address = page; |
638 | 639 | ||
639 | da.type = type; |
640 | da.type = type; |
640 | da.context = context_encoding; |
641 | da.context = context_encoding; |
641 | da.vpn = pg.vpn; |
642 | da.vpn = pg.vpn; |
642 | 643 | ||
643 | asi_u64_write(ASI_IMMU_DEMAP, da.value, 0); /* da.value is the |
644 | asi_u64_write(ASI_IMMU_DEMAP, da.value, 0); /* da.value is the |
644 | * address within the |
645 | * address within the |
645 | * ASI */ |
646 | * ASI */ |
646 | flush_pipeline(); |
647 | flush_pipeline(); |
647 | } |
648 | } |
648 | 649 | ||
649 | /** Perform DMMU TLB Demap Operation. |
650 | /** Perform DMMU TLB Demap Operation. |
650 | * |
651 | * |
651 | * @param type |
652 | * @param type |
652 | * Selects between context and page demap |
653 | * Selects between context and page demap |
653 | * (and entire MMU demap on US3). |
654 | * (and entire MMU demap on US3). |
654 | * @param context_encoding Specifies which Context register has Context ID for |
655 | * @param context_encoding Specifies which Context register has Context ID for |
655 | * demap. |
656 | * demap. |
656 | * @param page Address which is on the page to be demapped. |
657 | * @param page Address which is on the page to be demapped. |
657 | */ |
658 | */ |
658 | static inline void dtlb_demap(int type, int context_encoding, uintptr_t page) |
659 | static inline void dtlb_demap(int type, int context_encoding, uintptr_t page) |
659 | { |
660 | { |
660 | tlb_demap_addr_t da; |
661 | tlb_demap_addr_t da; |
661 | page_address_t pg; |
662 | page_address_t pg; |
662 | 663 | ||
663 | da.value = 0; |
664 | da.value = 0; |
664 | pg.address = page; |
665 | pg.address = page; |
665 | 666 | ||
666 | da.type = type; |
667 | da.type = type; |
667 | da.context = context_encoding; |
668 | da.context = context_encoding; |
668 | da.vpn = pg.vpn; |
669 | da.vpn = pg.vpn; |
669 | 670 | ||
670 | asi_u64_write(ASI_DMMU_DEMAP, da.value, 0); /* da.value is the |
671 | asi_u64_write(ASI_DMMU_DEMAP, da.value, 0); /* da.value is the |
671 | * address within the |
672 | * address within the |
672 | * ASI */ |
673 | * ASI */ |
673 | membar(); |
674 | membar(); |
674 | } |
675 | } |
675 | 676 | ||
676 | extern void fast_instruction_access_mmu_miss(unative_t unused, istate_t *istate); |
677 | extern void fast_instruction_access_mmu_miss(unative_t unused, istate_t *istate); |
677 | extern void fast_data_access_mmu_miss(tlb_tag_access_reg_t tag, istate_t *istate); |
678 | extern void fast_data_access_mmu_miss(tlb_tag_access_reg_t tag, istate_t *istate); |
678 | extern void fast_data_access_protection(tlb_tag_access_reg_t tag , istate_t *istate); |
679 | extern void fast_data_access_protection(tlb_tag_access_reg_t tag , istate_t *istate); |
679 | 680 | ||
680 | extern void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable); |
681 | extern void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable); |
681 | 682 | ||
682 | extern void dump_sfsr_and_sfar(void); |
683 | extern void dump_sfsr_and_sfar(void); |
683 | 684 | ||
684 | #endif /* !def __ASM__ */ |
685 | #endif /* !def __ASM__ */ |
685 | 686 | ||
686 | #endif |
687 | #endif |
687 | 688 | ||
688 | /** @} |
689 | /** @} |
689 | */ |
690 | */ |
690 | 691 |