WebSVN – HelenOS – Diff – /branches/snapshot/kernel/arch/mips32/include/mm/tlb.h


/*
 * Copyright (c) 2003-2004 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup mips32mm
 * @{
 */
/** @file
 */
 
#ifndef KERN_mips32_TLB_H_
#define KERN_mips32_TLB_H_
 
#include <arch/types.h>
#include <typedefs.h>
#include <arch/mm/asid.h>
#include <arch/exception.h>
 
#define TLB_ENTRY_COUNT  48
 
#define TLB_WIRED               1
#define TLB_KSTACK_WIRED_INDEX  0
 
#define TLB_PAGE_MASK_4K    (0x000 << 13)
#define TLB_PAGE_MASK_16K   (0x003 << 13)
#define TLB_PAGE_MASK_64K   (0x00f << 13)
#define TLB_PAGE_MASK_256K  (0x03f << 13)
#define TLB_PAGE_MASK_1M    (0x0ff << 13)
#define TLB_PAGE_MASK_4M    (0x3ff << 13)
#define TLB_PAGE_MASK_16M   (0xfff << 13)
 
#define PAGE_UNCACHED             2
#define PAGE_CACHEABLE_EXC_WRITE  5
 
typedef union {
    struct {
#ifdef BIG_ENDIAN
        unsigned : 2;       /* zero */
        unsigned pfn : 24;  /* frame number */
        unsigned c : 3;     /* cache coherency attribute */
        unsigned d : 1;     /* dirty/write-protect bit */
        unsigned v : 1;     /* valid bit */
        unsigned g : 1;     /* global bit */
#else
        unsigned g : 1;     /* global bit */
        unsigned v : 1;     /* valid bit */
        unsigned d : 1;     /* dirty/write-protect bit */
        unsigned c : 3;     /* cache coherency attribute */
        unsigned pfn : 24;  /* frame number */
        unsigned : 2;       /* zero */
#endif
    } __attribute__ ((packed));
    uint32_t value;
} entry_lo_t;
 
typedef union {
    struct {
#ifdef BIG_ENDIAN
        unsigned vpn2 : 19;
        unsigned : 5;
        unsigned asid : 8;
#else
        unsigned asid : 8;
        unsigned : 5;
        unsigned vpn2 : 19;
#endif
    } __attribute__ ((packed));
    uint32_t value;
} entry_hi_t;
 
typedef union {
    struct {
#ifdef BIG_ENDIAN
        unsigned : 7;
        unsigned mask : 12;
        unsigned : 13;
#else
        unsigned : 13;
        unsigned mask : 12;
        unsigned : 7;
#endif
    } __attribute__ ((packed));
    uint32_t value;
} page_mask_t;
 
typedef union {
    struct {
#ifdef BIG_ENDIAN
        unsigned p : 1;
        unsigned : 27;
        unsigned index : 4;
#else
        unsigned index : 4;
        unsigned : 27;
        unsigned p : 1;
#endif
    } __attribute__ ((packed));
    uint32_t value;
} tlb_index_t;
 
/** Probe TLB for Matching Entry
 *
 * Probe TLB for Matching Entry.
 */
static inline void tlbp(void)
{
    asm volatile ("tlbp\n\t");
}
 
 
/** Read Indexed TLB Entry
 *
 * Read Indexed TLB Entry.
 */
static inline void tlbr(void)
{
    asm volatile ("tlbr\n\t");
}
 
/** Write Indexed TLB Entry
 *
 * Write Indexed TLB Entry.
 */
static inline void tlbwi(void)
{
    asm volatile ("tlbwi\n\t");
}
 
/** Write Random TLB Entry
 *
 * Write Random TLB Entry.
 */
static inline void tlbwr(void)
{
    asm volatile ("tlbwr\n\t");
}
 
#define tlb_invalidate(asid)  tlb_invalidate_asid(asid)
 
extern void tlb_invalid(istate_t *istate);
extern void tlb_refill(istate_t *istate);
extern void tlb_modified(istate_t *istate);
extern void tlb_prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, uintptr_t pfn);
extern void tlb_prepare_entry_hi(entry_hi_t *hi, asid_t asid, uintptr_t addr);
 
#endif
 
/** @}
 */
 

Rev 4106	Rev 4605
1	/*	1	/*
2	* Copyright (c) 2003-2004 Jakub Jermar	2	* Copyright (c) 2003-2004 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup mips32mm	29	/** @addtogroup mips32mm
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#ifndef KERN_mips32_TLB_H_	35	#ifndef KERN_mips32_TLB_H_
36	#define KERN_mips32_TLB_H_	36	#define KERN_mips32_TLB_H_
37		37
38	#include <arch/types.h>	38	#include <arch/types.h>
39	#include <typedefs.h>	39	#include <typedefs.h>
40	#include <arch/mm/asid.h>	40	#include <arch/mm/asid.h>
41	#include <arch/exception.h>	41	#include <arch/exception.h>
42		42
43	#define TLB_ENTRY_COUNT 48	43	#define TLB_ENTRY_COUNT 48
44		44
45	#define TLB_WIRED 1	45	#define TLB_WIRED 1
46	#define TLB_KSTACK_WIRED_INDEX 0	46	#define TLB_KSTACK_WIRED_INDEX 0
47		47
48	#define TLB_PAGE_MASK_4K (0x000 << 13)	48	#define TLB_PAGE_MASK_4K (0x000 << 13)
49	#define TLB_PAGE_MASK_16K (0x003 << 13)	49	#define TLB_PAGE_MASK_16K (0x003 << 13)
50	#define TLB_PAGE_MASK_64K (0x00f << 13)	50	#define TLB_PAGE_MASK_64K (0x00f << 13)
51	#define TLB_PAGE_MASK_256K (0x03f << 13)	51	#define TLB_PAGE_MASK_256K (0x03f << 13)
52	#define TLB_PAGE_MASK_1M (0x0ff << 13)	52	#define TLB_PAGE_MASK_1M (0x0ff << 13)
53	#define TLB_PAGE_MASK_4M (0x3ff << 13)	53	#define TLB_PAGE_MASK_4M (0x3ff << 13)
54	#define TLB_PAGE_MASK_16M (0xfff << 13)	54	#define TLB_PAGE_MASK_16M (0xfff << 13)
55		55
56	#define PAGE_UNCACHED 2	56	#define PAGE_UNCACHED 2
57	#define PAGE_CACHEABLE_EXC_WRITE 5	57	#define PAGE_CACHEABLE_EXC_WRITE 5
58		58
59	typedef union {	59	typedef union {
60	struct {	60	struct {
61	#ifdef BIG_ENDIAN	61	#ifdef BIG_ENDIAN
62	unsigned : 2; /* zero */	62	unsigned : 2; /* zero */
63	unsigned pfn : 24; /* frame number */	63	unsigned pfn : 24; /* frame number */
64	unsigned c : 3; /* cache coherency attribute */	64	unsigned c : 3; /* cache coherency attribute */
65	unsigned d : 1; /* dirty/write-protect bit */	65	unsigned d : 1; /* dirty/write-protect bit */
66	unsigned v : 1; /* valid bit */	66	unsigned v : 1; /* valid bit */
67	unsigned g : 1; /* global bit */	67	unsigned g : 1; /* global bit */
68	#else	68	#else
69	unsigned g : 1; /* global bit */	69	unsigned g : 1; /* global bit */
70	unsigned v : 1; /* valid bit */	70	unsigned v : 1; /* valid bit */
71	unsigned d : 1; /* dirty/write-protect bit */	71	unsigned d : 1; /* dirty/write-protect bit */
72	unsigned c : 3; /* cache coherency attribute */	72	unsigned c : 3; /* cache coherency attribute */
73	unsigned pfn : 24; /* frame number */	73	unsigned pfn : 24; /* frame number */
74	unsigned : 2; /* zero */	74	unsigned : 2; /* zero */
75	#endif	75	#endif
76	} __attribute__ ((packed));	76	} __attribute__ ((packed));
77	uint32_t value;	77	uint32_t value;
78	} entry_lo_t;	78	} entry_lo_t;
79		79
80	typedef union {	80	typedef union {
81	struct {	81	struct {
82	#ifdef BIG_ENDIAN	82	#ifdef BIG_ENDIAN
83	unsigned vpn2 : 19;	83	unsigned vpn2 : 19;
84	unsigned : 5;	84	unsigned : 5;
85	unsigned asid : 8;	85	unsigned asid : 8;
86	#else	86	#else
87	unsigned asid : 8;	87	unsigned asid : 8;
88	unsigned : 5;	88	unsigned : 5;
89	unsigned vpn2 : 19;	89	unsigned vpn2 : 19;
90	#endif	90	#endif
91	} __attribute__ ((packed));	91	} __attribute__ ((packed));
92	uint32_t value;	92	uint32_t value;
93	} entry_hi_t;	93	} entry_hi_t;
94		94
95	typedef union {	95	typedef union {
96	struct {	96	struct {
97	#ifdef BIG_ENDIAN	97	#ifdef BIG_ENDIAN
98	unsigned : 7;	98	unsigned : 7;
99	unsigned mask : 12;	99	unsigned mask : 12;
100	unsigned : 13;	100	unsigned : 13;
101	#else	101	#else
102	unsigned : 13;	102	unsigned : 13;
103	unsigned mask : 12;	103	unsigned mask : 12;
104	unsigned : 7;	104	unsigned : 7;
105	#endif	105	#endif
106	} __attribute__ ((packed));	106	} __attribute__ ((packed));
107	uint32_t value;	107	uint32_t value;
108	} page_mask_t;	108	} page_mask_t;
109		109
110	typedef union {	110	typedef union {
111	struct {	111	struct {
112	#ifdef BIG_ENDIAN	112	#ifdef BIG_ENDIAN
113	unsigned p : 1;	113	unsigned p : 1;
114	unsigned : 27;	114	unsigned : 27;
115	unsigned index : 4;	115	unsigned index : 4;
116	#else	116	#else
117	unsigned index : 4;	117	unsigned index : 4;
118	unsigned : 27;	118	unsigned : 27;
119	unsigned p : 1;	119	unsigned p : 1;
120	#endif	120	#endif
121	} __attribute__ ((packed));	121	} __attribute__ ((packed));
122	uint32_t value;	122	uint32_t value;
123	} tlb_index_t;	123	} tlb_index_t;
124		124
125	/** Probe TLB for Matching Entry	125	/** Probe TLB for Matching Entry
126	*	126	*
127	* Probe TLB for Matching Entry.	127	* Probe TLB for Matching Entry.
128	*/	128	*/
129	static inline void tlbp(void)	129	static inline void tlbp(void)
130	{	130	{
131	asm volatile ("tlbp\n\t");	131	asm volatile ("tlbp\n\t");
132	}	132	}
133		133
134		134
135	/** Read Indexed TLB Entry	135	/** Read Indexed TLB Entry
136	*	136	*
137	* Read Indexed TLB Entry.	137	* Read Indexed TLB Entry.
138	*/	138	*/
139	static inline void tlbr(void)	139	static inline void tlbr(void)
140	{	140	{
141	asm volatile ("tlbr\n\t");	141	asm volatile ("tlbr\n\t");
142	}	142	}
143		143
144	/** Write Indexed TLB Entry	144	/** Write Indexed TLB Entry
145	*	145	*
146	* Write Indexed TLB Entry.	146	* Write Indexed TLB Entry.
147	*/	147	*/
148	static inline void tlbwi(void)	148	static inline void tlbwi(void)
149	{	149	{
150	asm volatile ("tlbwi\n\t");	150	asm volatile ("tlbwi\n\t");
151	}	151	}
152		152
153	/** Write Random TLB Entry	153	/** Write Random TLB Entry
154	*	154	*
155	* Write Random TLB Entry.	155	* Write Random TLB Entry.
156	*/	156	*/
157	static inline void tlbwr(void)	157	static inline void tlbwr(void)
158	{	158	{
159	asm volatile ("tlbwr\n\t");	159	asm volatile ("tlbwr\n\t");
160	}	160	}
161		161
162	#define tlb_invalidate(asid) tlb_invalidate_asid(asid)	162	#define tlb_invalidate(asid) tlb_invalidate_asid(asid)
163		163
164	extern void tlb_invalid(istate_t *istate);	164	extern void tlb_invalid(istate_t *istate);
165	extern void tlb_refill(istate_t *istate);	165	extern void tlb_refill(istate_t *istate);
166	extern void tlb_modified(istate_t *istate);	166	extern void tlb_modified(istate_t *istate);
167	extern void tlb_prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, uintptr_t pfn);	167	extern void tlb_prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, uintptr_t pfn);
168	extern void tlb_prepare_entry_hi(entry_hi_t *hi, asid_t asid, uintptr_t addr);	168	extern void tlb_prepare_entry_hi(entry_hi_t *hi, asid_t asid, uintptr_t addr);
169		169
170	#endif	170	#endif
171		171
172	/** @}	172	/** @}
173	*/	173	*/
174		174

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(root)/branches/snapshot/kernel/arch/mips32/include/mm/tlb.h – Rev 4106 → 4605