WebSVN – HelenOS – Diff – /branches/snapshot/kernel/arch/ia32/src/cpu/cpu.c


/*
 * Copyright (c) 2001-2004 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup ia32
 * @{
 */
/** @file
 */
 
#include <arch/cpu.h>
#include <arch/cpuid.h>
#include <arch/pm.h>
 
#include <arch.h>
#include <arch/types.h>
#include <print.h>
#include <fpu_context.h>
 
#include <arch/smp/apic.h>
#include <arch/syscall.h>
 
/*
 * Identification of CPUs.
 * Contains only non-MP-Specification specific SMP code.
 */
#define AMD_CPUID_EBX  0x68747541
#define AMD_CPUID_ECX  0x444d4163
#define AMD_CPUID_EDX  0x69746e65
 
#define INTEL_CPUID_EBX  0x756e6547
#define INTEL_CPUID_ECX  0x6c65746e
#define INTEL_CPUID_EDX  0x49656e69
 
 
enum vendor {
    VendorUnknown = 0,
    VendorAMD,
    VendorIntel
};
 
static char *vendor_str[] = {
    "Unknown Vendor",
    "AMD",
    "Intel"
};
 
void fpu_disable(void)
{
    asm volatile (
        "mov %%cr0, %%eax\n"
        "or $8, %%eax\n"
        "mov %%eax, %%cr0\n"
        ::: "%eax"
    );
}
 
void fpu_enable(void)
{
    asm volatile (
        "mov %%cr0, %%eax\n"
        "and $0xffFFffF7, %%eax\n"
        "mov %%eax,%%cr0\n"
        ::: "%eax"
    );
}
 
void cpu_arch_init(void)
{
    cpuid_feature_info fi;
    cpuid_extended_feature_info efi;
    cpu_info_t info;
    uint32_t help = 0;
   
    CPU->arch.tss = tss_p;
    CPU->arch.tss->iomap_base = &CPU->arch.tss->iomap[0] - ((uint8_t *) CPU->arch.tss);
   
    CPU->fpu_owner = NULL;
   
    cpuid(1, &info);
   
    fi.word = info.cpuid_edx;
    efi.word = info.cpuid_ecx;
   
    if (fi.bits.fxsr)
        fpu_fxsr();
    else
        fpu_fsr();
   
    if (fi.bits.sse) {
        asm volatile (
            "mov %%cr4, %[help]\n"
            "or %[mask], %[help]\n"
            "mov %[help], %%cr4\n"
            : [help] "+r" (help)
            : [mask] "i" (CR4_OSFXSR_MASK | (1 << 10))
        );
    }
   
    /* Setup fast SYSENTER/SYSEXIT syscalls */
    syscall_setup_cpu();
}
 
void cpu_identify(void)
{
    cpu_info_t info;
 
    CPU->arch.vendor = VendorUnknown;
    if (has_cpuid()) {
        cpuid(0, &info);
 
        /*
         * Check for AMD processor.
         */
        if ((info.cpuid_ebx == AMD_CPUID_EBX)
            && (info.cpuid_ecx == AMD_CPUID_ECX)
            && (info.cpuid_edx == AMD_CPUID_EDX))
            CPU->arch.vendor = VendorAMD;
       
        /*
         * Check for Intel processor.
         */    
        if ((info.cpuid_ebx == INTEL_CPUID_EBX)
            && (info.cpuid_ecx == INTEL_CPUID_ECX)
            && (info.cpuid_edx == INTEL_CPUID_EDX))
            CPU->arch.vendor = VendorIntel;
       
        cpuid(1, &info);
        CPU->arch.family = (info.cpuid_eax >> 8) & 0x0f;
        CPU->arch.model = (info.cpuid_eax >> 4) & 0x0f;
        CPU->arch.stepping = (info.cpuid_eax >> 0) & 0x0f;                     
    }
}
 
void cpu_print_report(cpu_t* cpu)
{
    printf("cpu%u: (%s family=%u model=%u stepping=%u) %" PRIu16 " MHz\n",
        cpu->id, vendor_str[cpu->arch.vendor], cpu->arch.family,
        cpu->arch.model, cpu->arch.stepping, cpu->frequency_mhz);
}
 
/** @}
 */
 

Rev 4016	Rev 4605
1	/*	1	/*
2	* Copyright (c) 2001-2004 Jakub Jermar	2	* Copyright (c) 2001-2004 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup ia32	29	/** @addtogroup ia32
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#include <arch/cpu.h>	35	#include <arch/cpu.h>
36	#include <arch/cpuid.h>	36	#include <arch/cpuid.h>
37	#include <arch/pm.h>	37	#include <arch/pm.h>
38		38
39	#include <arch.h>	39	#include <arch.h>
40	#include <arch/types.h>	40	#include <arch/types.h>
41	#include <print.h>	41	#include <print.h>
42	#include <fpu_context.h>	42	#include <fpu_context.h>
43		43
44	#include <arch/smp/apic.h>	44	#include <arch/smp/apic.h>
45	#include <arch/syscall.h>	45	#include <arch/syscall.h>
46		46
47	/*	47	/*
48	* Identification of CPUs.	48	* Identification of CPUs.
49	* Contains only non-MP-Specification specific SMP code.	49	* Contains only non-MP-Specification specific SMP code.
50	*/	50	*/
51	#define AMD_CPUID_EBX 0x68747541	51	#define AMD_CPUID_EBX 0x68747541
52	#define AMD_CPUID_ECX 0x444d4163	52	#define AMD_CPUID_ECX 0x444d4163
53	#define AMD_CPUID_EDX 0x69746e65	53	#define AMD_CPUID_EDX 0x69746e65
54		54
55	#define INTEL_CPUID_EBX 0x756e6547	55	#define INTEL_CPUID_EBX 0x756e6547
56	#define INTEL_CPUID_ECX 0x6c65746e	56	#define INTEL_CPUID_ECX 0x6c65746e
57	#define INTEL_CPUID_EDX 0x49656e69	57	#define INTEL_CPUID_EDX 0x49656e69
58		58
59		59
60	enum vendor {	60	enum vendor {
61	VendorUnknown = 0,	61	VendorUnknown = 0,
62	VendorAMD,	62	VendorAMD,
63	VendorIntel	63	VendorIntel
64	};	64	};
65		65
66	static char *vendor_str[] = {	66	static char *vendor_str[] = {
67	"Unknown Vendor",	67	"Unknown Vendor",
68	"AMD",	68	"AMD",
69	"Intel"	69	"Intel"
70	};	70	};
71		71
72	void fpu_disable(void)	72	void fpu_disable(void)
73	{	73	{
74	asm volatile (	74	asm volatile (
75	"mov %%cr0, %%eax\n"	75	"mov %%cr0, %%eax\n"
76	"or $8, %%eax\n"	76	"or $8, %%eax\n"
77	"mov %%eax, %%cr0\n"	77	"mov %%eax, %%cr0\n"
78	::: "%eax"	78	::: "%eax"
79	);	79	);
80	}	80	}
81		81
82	void fpu_enable(void)	82	void fpu_enable(void)
83	{	83	{
84	asm volatile (	84	asm volatile (
85	"mov %%cr0, %%eax\n"	85	"mov %%cr0, %%eax\n"
86	"and $0xffFFffF7, %%eax\n"	86	"and $0xffFFffF7, %%eax\n"
87	"mov %%eax,%%cr0\n"	87	"mov %%eax,%%cr0\n"
88	::: "%eax"	88	::: "%eax"
89	);	89	);
90	}	90	}
91		91
92	void cpu_arch_init(void)	92	void cpu_arch_init(void)
93	{	93	{
94	cpuid_feature_info fi;	94	cpuid_feature_info fi;
95	cpuid_extended_feature_info efi;	95	cpuid_extended_feature_info efi;
96	cpu_info_t info;	96	cpu_info_t info;
97	uint32_t help = 0;	97	uint32_t help = 0;
98		98
99	CPU->arch.tss = tss_p;	99	CPU->arch.tss = tss_p;
100	CPU->arch.tss->iomap_base = &CPU->arch.tss->iomap[0] - ((uint8_t *) CPU->arch.tss);	100	CPU->arch.tss->iomap_base = &CPU->arch.tss->iomap[0] - ((uint8_t *) CPU->arch.tss);
101		101
102	CPU->fpu_owner = NULL;	102	CPU->fpu_owner = NULL;
103		103
104	cpuid(1, &info);	104	cpuid(1, &info);
105		105
106	fi.word = info.cpuid_edx;	106	fi.word = info.cpuid_edx;
107	efi.word = info.cpuid_ecx;	107	efi.word = info.cpuid_ecx;
108		108
109	if (fi.bits.fxsr)	109	if (fi.bits.fxsr)
110	fpu_fxsr();	110	fpu_fxsr();
111	else	111	else
112	fpu_fsr();	112	fpu_fsr();
113		113
114	if (fi.bits.sse) {	114	if (fi.bits.sse) {
115	asm volatile (	115	asm volatile (
116	"mov %%cr4, %[help]\n"	116	"mov %%cr4, %[help]\n"
117	"or %[mask], %[help]\n"	117	"or %[mask], %[help]\n"
118	"mov %[help], %%cr4\n"	118	"mov %[help], %%cr4\n"
119	: [help] "+r" (help)	119	: [help] "+r" (help)
120	: [mask] "i" (CR4_OSFXSR_MASK \| (1 << 10))	120	: [mask] "i" (CR4_OSFXSR_MASK \| (1 << 10))
121	);	121	);
122	}	122	}
123		123
124	/* Setup fast SYSENTER/SYSEXIT syscalls */	124	/* Setup fast SYSENTER/SYSEXIT syscalls */
125	syscall_setup_cpu();	125	syscall_setup_cpu();
126	}	126	}
127		127
128	void cpu_identify(void)	128	void cpu_identify(void)
129	{	129	{
130	cpu_info_t info;	130	cpu_info_t info;
131		131
132	CPU->arch.vendor = VendorUnknown;	132	CPU->arch.vendor = VendorUnknown;
133	if (has_cpuid()) {	133	if (has_cpuid()) {
134	cpuid(0, &info);	134	cpuid(0, &info);
135		135
136	/*	136	/*
137	* Check for AMD processor.	137	* Check for AMD processor.
138	*/	138	*/
139	if ((info.cpuid_ebx == AMD_CPUID_EBX)	139	if ((info.cpuid_ebx == AMD_CPUID_EBX)
140	&& (info.cpuid_ecx == AMD_CPUID_ECX)	140	&& (info.cpuid_ecx == AMD_CPUID_ECX)
141	&& (info.cpuid_edx == AMD_CPUID_EDX))	141	&& (info.cpuid_edx == AMD_CPUID_EDX))
142	CPU->arch.vendor = VendorAMD;	142	CPU->arch.vendor = VendorAMD;
143		143
144	/*	144	/*
145	* Check for Intel processor.	145	* Check for Intel processor.
146	*/	146	*/
147	if ((info.cpuid_ebx == INTEL_CPUID_EBX)	147	if ((info.cpuid_ebx == INTEL_CPUID_EBX)
148	&& (info.cpuid_ecx == INTEL_CPUID_ECX)	148	&& (info.cpuid_ecx == INTEL_CPUID_ECX)
149	&& (info.cpuid_edx == INTEL_CPUID_EDX))	149	&& (info.cpuid_edx == INTEL_CPUID_EDX))
150	CPU->arch.vendor = VendorIntel;	150	CPU->arch.vendor = VendorIntel;
151		151
152	cpuid(1, &info);	152	cpuid(1, &info);
153	CPU->arch.family = (info.cpuid_eax >> 8) & 0x0f;	153	CPU->arch.family = (info.cpuid_eax >> 8) & 0x0f;
154	CPU->arch.model = (info.cpuid_eax >> 4) & 0x0f;	154	CPU->arch.model = (info.cpuid_eax >> 4) & 0x0f;
155	CPU->arch.stepping = (info.cpuid_eax >> 0) & 0x0f;	155	CPU->arch.stepping = (info.cpuid_eax >> 0) & 0x0f;
156	}	156	}
157	}	157	}
158		158
159	void cpu_print_report(cpu_t* cpu)	159	void cpu_print_report(cpu_t* cpu)
160	{	160	{
161	printf("cpu%u: (%s family=%u model=%u stepping=%u) %" PRIu16 " MHz\n",	161	printf("cpu%u: (%s family=%u model=%u stepping=%u) %" PRIu16 " MHz\n",
162	cpu->id, vendor_str[cpu->arch.vendor], cpu->arch.family,	162	cpu->id, vendor_str[cpu->arch.vendor], cpu->arch.family,
163	cpu->arch.model, cpu->arch.stepping, cpu->frequency_mhz);	163	cpu->arch.model, cpu->arch.stepping, cpu->frequency_mhz);
164	}	164	}
165		165
166	/** @}	166	/** @}
167	*/	167	*/
168		168

Subversion Repositories HelenOS

(root)/branches/snapshot/kernel/arch/ia32/src/cpu/cpu.c – Rev 4016 → 4605