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1 | /* |
1 | /* |
2 | * Copyright (C) 2005 Jakub Jermar |
2 | * Copyright (C) 2005 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup sparc64mm |
29 | /** @addtogroup sparc64mm |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | */ |
33 | */ |
34 | 34 | ||
35 | #ifndef __sparc64_TLB_H__ |
35 | #ifndef __sparc64_TLB_H__ |
36 | #define __sparc64_TLB_H__ |
36 | #define __sparc64_TLB_H__ |
37 | 37 | ||
38 | 38 | ||
39 | #define ITLB_ENTRY_COUNT 64 |
39 | #define ITLB_ENTRY_COUNT 64 |
40 | #define DTLB_ENTRY_COUNT 64 |
40 | #define DTLB_ENTRY_COUNT 64 |
41 | 41 | ||
42 | #define MEM_CONTEXT_KERNEL 0 |
42 | #define MEM_CONTEXT_KERNEL 0 |
43 | #define MEM_CONTEXT_TEMP 1 |
43 | #define MEM_CONTEXT_TEMP 1 |
44 | 44 | ||
45 | /** Page sizes. */ |
45 | /** Page sizes. */ |
46 | #define PAGESIZE_8K 0 |
46 | #define PAGESIZE_8K 0 |
47 | #define PAGESIZE_64K 1 |
47 | #define PAGESIZE_64K 1 |
48 | #define PAGESIZE_512K 2 |
48 | #define PAGESIZE_512K 2 |
49 | #define PAGESIZE_4M 3 |
49 | #define PAGESIZE_4M 3 |
50 | 50 | ||
51 | /** Bit width of the TLB-locked portion of kernel address space. */ |
51 | /** Bit width of the TLB-locked portion of kernel address space. */ |
52 | #define KERNEL_PAGE_WIDTH 22 /* 4M */ |
52 | #define KERNEL_PAGE_WIDTH 22 /* 4M */ |
53 | 53 | ||
54 | /* TLB Demap Operation types. */ |
54 | /* TLB Demap Operation types. */ |
55 | #define TLB_DEMAP_PAGE 0 |
55 | #define TLB_DEMAP_PAGE 0 |
56 | #define TLB_DEMAP_CONTEXT 1 |
56 | #define TLB_DEMAP_CONTEXT 1 |
57 | 57 | ||
58 | #define TLB_DEMAP_TYPE_SHIFT 6 |
58 | #define TLB_DEMAP_TYPE_SHIFT 6 |
59 | 59 | ||
60 | /* TLB Demap Operation Context register encodings. */ |
60 | /* TLB Demap Operation Context register encodings. */ |
61 | #define TLB_DEMAP_PRIMARY 0 |
61 | #define TLB_DEMAP_PRIMARY 0 |
62 | #define TLB_DEMAP_SECONDARY 1 |
62 | #define TLB_DEMAP_SECONDARY 1 |
63 | #define TLB_DEMAP_NUCLEUS 2 |
63 | #define TLB_DEMAP_NUCLEUS 2 |
64 | 64 | ||
65 | #define TLB_DEMAP_CONTEXT_SHIFT 4 |
65 | #define TLB_DEMAP_CONTEXT_SHIFT 4 |
66 | 66 | ||
67 | /* TLB Tag Access shifts */ |
67 | /* TLB Tag Access shifts */ |
68 | #define TLB_TAG_ACCESS_CONTEXT_SHIFT 0 |
68 | #define TLB_TAG_ACCESS_CONTEXT_SHIFT 0 |
- | 69 | #define TLB_TAG_ACCESS_CONTEXT_MASK ((1<<13)-1) |
|
69 | #define TLB_TAG_ACCESS_VPN_SHIFT 13 |
70 | #define TLB_TAG_ACCESS_VPN_SHIFT 13 |
70 | 71 | ||
71 | #ifndef __ASM__ |
72 | #ifndef __ASM__ |
72 | 73 | ||
73 | #include <arch/mm/tte.h> |
74 | #include <arch/mm/tte.h> |
74 | #include <arch/mm/mmu.h> |
75 | #include <arch/mm/mmu.h> |
75 | #include <arch/mm/page.h> |
76 | #include <arch/mm/page.h> |
76 | #include <arch/asm.h> |
77 | #include <arch/asm.h> |
77 | #include <arch/barrier.h> |
78 | #include <arch/barrier.h> |
78 | #include <arch/types.h> |
79 | #include <arch/types.h> |
79 | #include <typedefs.h> |
80 | #include <typedefs.h> |
80 | 81 | ||
81 | union tlb_context_reg { |
82 | union tlb_context_reg { |
82 | uint64_t v; |
83 | uint64_t v; |
83 | struct { |
84 | struct { |
84 | unsigned long : 51; |
85 | unsigned long : 51; |
85 | unsigned context : 13; /**< Context/ASID. */ |
86 | unsigned context : 13; /**< Context/ASID. */ |
86 | } __attribute__ ((packed)); |
87 | } __attribute__ ((packed)); |
87 | }; |
88 | }; |
88 | typedef union tlb_context_reg tlb_context_reg_t; |
89 | typedef union tlb_context_reg tlb_context_reg_t; |
89 | 90 | ||
90 | /** I-/D-TLB Data In/Access Register type. */ |
91 | /** I-/D-TLB Data In/Access Register type. */ |
91 | typedef tte_data_t tlb_data_t; |
92 | typedef tte_data_t tlb_data_t; |
92 | 93 | ||
93 | /** I-/D-TLB Data Access Address in Alternate Space. */ |
94 | /** I-/D-TLB Data Access Address in Alternate Space. */ |
94 | union tlb_data_access_addr { |
95 | union tlb_data_access_addr { |
95 | uint64_t value; |
96 | uint64_t value; |
96 | struct { |
97 | struct { |
97 | uint64_t : 55; |
98 | uint64_t : 55; |
98 | unsigned tlb_entry : 6; |
99 | unsigned tlb_entry : 6; |
99 | unsigned : 3; |
100 | unsigned : 3; |
100 | } __attribute__ ((packed)); |
101 | } __attribute__ ((packed)); |
101 | }; |
102 | }; |
102 | typedef union tlb_data_access_addr tlb_data_access_addr_t; |
103 | typedef union tlb_data_access_addr tlb_data_access_addr_t; |
103 | typedef union tlb_data_access_addr tlb_tag_read_addr_t; |
104 | typedef union tlb_data_access_addr tlb_tag_read_addr_t; |
104 | 105 | ||
105 | /** I-/D-TLB Tag Read Register. */ |
106 | /** I-/D-TLB Tag Read Register. */ |
106 | union tlb_tag_read_reg { |
107 | union tlb_tag_read_reg { |
107 | uint64_t value; |
108 | uint64_t value; |
108 | struct { |
109 | struct { |
109 | uint64_t vpn : 51; /**< Virtual Address bits 63:13. */ |
110 | uint64_t vpn : 51; /**< Virtual Address bits 63:13. */ |
110 | unsigned context : 13; /**< Context identifier. */ |
111 | unsigned context : 13; /**< Context identifier. */ |
111 | } __attribute__ ((packed)); |
112 | } __attribute__ ((packed)); |
112 | }; |
113 | }; |
113 | typedef union tlb_tag_read_reg tlb_tag_read_reg_t; |
114 | typedef union tlb_tag_read_reg tlb_tag_read_reg_t; |
114 | typedef union tlb_tag_read_reg tlb_tag_access_reg_t; |
115 | typedef union tlb_tag_read_reg tlb_tag_access_reg_t; |
115 | 116 | ||
116 | 117 | ||
117 | /** TLB Demap Operation Address. */ |
118 | /** TLB Demap Operation Address. */ |
118 | union tlb_demap_addr { |
119 | union tlb_demap_addr { |
119 | uint64_t value; |
120 | uint64_t value; |
120 | struct { |
121 | struct { |
121 | uint64_t vpn: 51; /**< Virtual Address bits 63:13. */ |
122 | uint64_t vpn: 51; /**< Virtual Address bits 63:13. */ |
122 | unsigned : 6; /**< Ignored. */ |
123 | unsigned : 6; /**< Ignored. */ |
123 | unsigned type : 1; /**< The type of demap operation. */ |
124 | unsigned type : 1; /**< The type of demap operation. */ |
124 | unsigned context : 2; /**< Context register selection. */ |
125 | unsigned context : 2; /**< Context register selection. */ |
125 | unsigned : 4; /**< Zero. */ |
126 | unsigned : 4; /**< Zero. */ |
126 | } __attribute__ ((packed)); |
127 | } __attribute__ ((packed)); |
127 | }; |
128 | }; |
128 | typedef union tlb_demap_addr tlb_demap_addr_t; |
129 | typedef union tlb_demap_addr tlb_demap_addr_t; |
129 | 130 | ||
130 | /** TLB Synchronous Fault Status Register. */ |
131 | /** TLB Synchronous Fault Status Register. */ |
131 | union tlb_sfsr_reg { |
132 | union tlb_sfsr_reg { |
132 | uint64_t value; |
133 | uint64_t value; |
133 | struct { |
134 | struct { |
134 | unsigned long : 39; /**< Implementation dependent. */ |
135 | unsigned long : 40; /**< Implementation dependent. */ |
135 | unsigned nf : 1; /**< Nonfaulting load. */ |
- | |
136 | unsigned asi : 8; /**< ASI. */ |
136 | unsigned asi : 8; /**< ASI. */ |
137 | unsigned tm : 1; /**< TLB miss. */ |
- | |
138 | unsigned : 1; |
137 | unsigned : 2; |
139 | unsigned ft : 7; /**< Fault type. */ |
138 | unsigned ft : 7; /**< Fault type. */ |
140 | unsigned e : 1; /**< Side-effect bit. */ |
139 | unsigned e : 1; /**< Side-effect bit. */ |
141 | unsigned ct : 2; /**< Context Register selection. */ |
140 | unsigned ct : 2; /**< Context Register selection. */ |
142 | unsigned pr : 1; /**< Privilege bit. */ |
141 | unsigned pr : 1; /**< Privilege bit. */ |
143 | unsigned w : 1; /**< Write bit. */ |
142 | unsigned w : 1; /**< Write bit. */ |
144 | unsigned ow : 1; /**< Overwrite bit. */ |
143 | unsigned ow : 1; /**< Overwrite bit. */ |
145 | unsigned fv : 1; /**< Fault Valid bit. */ |
144 | unsigned fv : 1; /**< Fault Valid bit. */ |
146 | } __attribute__ ((packed)); |
145 | } __attribute__ ((packed)); |
147 | }; |
146 | }; |
148 | typedef union tlb_sfsr_reg tlb_sfsr_reg_t; |
147 | typedef union tlb_sfsr_reg tlb_sfsr_reg_t; |
149 | 148 | ||
150 | /** Read MMU Primary Context Register. |
149 | /** Read MMU Primary Context Register. |
151 | * |
150 | * |
152 | * @return Current value of Primary Context Register. |
151 | * @return Current value of Primary Context Register. |
153 | */ |
152 | */ |
154 | static inline uint64_t mmu_primary_context_read(void) |
153 | static inline uint64_t mmu_primary_context_read(void) |
155 | { |
154 | { |
156 | return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG); |
155 | return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG); |
157 | } |
156 | } |
158 | 157 | ||
159 | /** Write MMU Primary Context Register. |
158 | /** Write MMU Primary Context Register. |
160 | * |
159 | * |
161 | * @param v New value of Primary Context Register. |
160 | * @param v New value of Primary Context Register. |
162 | */ |
161 | */ |
163 | static inline void mmu_primary_context_write(uint64_t v) |
162 | static inline void mmu_primary_context_write(uint64_t v) |
164 | { |
163 | { |
165 | asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v); |
164 | asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v); |
166 | flush(); |
165 | flush(); |
167 | } |
166 | } |
168 | 167 | ||
169 | /** Read MMU Secondary Context Register. |
168 | /** Read MMU Secondary Context Register. |
170 | * |
169 | * |
171 | * @return Current value of Secondary Context Register. |
170 | * @return Current value of Secondary Context Register. |
172 | */ |
171 | */ |
173 | static inline uint64_t mmu_secondary_context_read(void) |
172 | static inline uint64_t mmu_secondary_context_read(void) |
174 | { |
173 | { |
175 | return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG); |
174 | return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG); |
176 | } |
175 | } |
177 | 176 | ||
178 | /** Write MMU Primary Context Register. |
177 | /** Write MMU Primary Context Register. |
179 | * |
178 | * |
180 | * @param v New value of Primary Context Register. |
179 | * @param v New value of Primary Context Register. |
181 | */ |
180 | */ |
182 | static inline void mmu_secondary_context_write(uint64_t v) |
181 | static inline void mmu_secondary_context_write(uint64_t v) |
183 | { |
182 | { |
184 | asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v); |
183 | asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v); |
185 | flush(); |
184 | flush(); |
186 | } |
185 | } |
187 | 186 | ||
188 | /** Read IMMU TLB Data Access Register. |
187 | /** Read IMMU TLB Data Access Register. |
189 | * |
188 | * |
190 | * @param entry TLB Entry index. |
189 | * @param entry TLB Entry index. |
191 | * |
190 | * |
192 | * @return Current value of specified IMMU TLB Data Access Register. |
191 | * @return Current value of specified IMMU TLB Data Access Register. |
193 | */ |
192 | */ |
194 | static inline uint64_t itlb_data_access_read(index_t entry) |
193 | static inline uint64_t itlb_data_access_read(index_t entry) |
195 | { |
194 | { |
196 | tlb_data_access_addr_t reg; |
195 | tlb_data_access_addr_t reg; |
197 | 196 | ||
198 | reg.value = 0; |
197 | reg.value = 0; |
199 | reg.tlb_entry = entry; |
198 | reg.tlb_entry = entry; |
200 | return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value); |
199 | return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value); |
201 | } |
200 | } |
202 | 201 | ||
203 | /** Write IMMU TLB Data Access Register. |
202 | /** Write IMMU TLB Data Access Register. |
204 | * |
203 | * |
205 | * @param entry TLB Entry index. |
204 | * @param entry TLB Entry index. |
206 | * @param value Value to be written. |
205 | * @param value Value to be written. |
207 | */ |
206 | */ |
208 | static inline void itlb_data_access_write(index_t entry, uint64_t value) |
207 | static inline void itlb_data_access_write(index_t entry, uint64_t value) |
209 | { |
208 | { |
210 | tlb_data_access_addr_t reg; |
209 | tlb_data_access_addr_t reg; |
211 | 210 | ||
212 | reg.value = 0; |
211 | reg.value = 0; |
213 | reg.tlb_entry = entry; |
212 | reg.tlb_entry = entry; |
214 | asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value); |
213 | asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value); |
215 | flush(); |
214 | flush(); |
216 | } |
215 | } |
217 | 216 | ||
218 | /** Read DMMU TLB Data Access Register. |
217 | /** Read DMMU TLB Data Access Register. |
219 | * |
218 | * |
220 | * @param entry TLB Entry index. |
219 | * @param entry TLB Entry index. |
221 | * |
220 | * |
222 | * @return Current value of specified DMMU TLB Data Access Register. |
221 | * @return Current value of specified DMMU TLB Data Access Register. |
223 | */ |
222 | */ |
224 | static inline uint64_t dtlb_data_access_read(index_t entry) |
223 | static inline uint64_t dtlb_data_access_read(index_t entry) |
225 | { |
224 | { |
226 | tlb_data_access_addr_t reg; |
225 | tlb_data_access_addr_t reg; |
227 | 226 | ||
228 | reg.value = 0; |
227 | reg.value = 0; |
229 | reg.tlb_entry = entry; |
228 | reg.tlb_entry = entry; |
230 | return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value); |
229 | return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value); |
231 | } |
230 | } |
232 | 231 | ||
233 | /** Write DMMU TLB Data Access Register. |
232 | /** Write DMMU TLB Data Access Register. |
234 | * |
233 | * |
235 | * @param entry TLB Entry index. |
234 | * @param entry TLB Entry index. |
236 | * @param value Value to be written. |
235 | * @param value Value to be written. |
237 | */ |
236 | */ |
238 | static inline void dtlb_data_access_write(index_t entry, uint64_t value) |
237 | static inline void dtlb_data_access_write(index_t entry, uint64_t value) |
239 | { |
238 | { |
240 | tlb_data_access_addr_t reg; |
239 | tlb_data_access_addr_t reg; |
241 | 240 | ||
242 | reg.value = 0; |
241 | reg.value = 0; |
243 | reg.tlb_entry = entry; |
242 | reg.tlb_entry = entry; |
244 | asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value); |
243 | asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value); |
245 | membar(); |
244 | membar(); |
246 | } |
245 | } |
247 | 246 | ||
248 | /** Read IMMU TLB Tag Read Register. |
247 | /** Read IMMU TLB Tag Read Register. |
249 | * |
248 | * |
250 | * @param entry TLB Entry index. |
249 | * @param entry TLB Entry index. |
251 | * |
250 | * |
252 | * @return Current value of specified IMMU TLB Tag Read Register. |
251 | * @return Current value of specified IMMU TLB Tag Read Register. |
253 | */ |
252 | */ |
254 | static inline uint64_t itlb_tag_read_read(index_t entry) |
253 | static inline uint64_t itlb_tag_read_read(index_t entry) |
255 | { |
254 | { |
256 | tlb_tag_read_addr_t tag; |
255 | tlb_tag_read_addr_t tag; |
257 | 256 | ||
258 | tag.value = 0; |
257 | tag.value = 0; |
259 | tag.tlb_entry = entry; |
258 | tag.tlb_entry = entry; |
260 | return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value); |
259 | return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value); |
261 | } |
260 | } |
262 | 261 | ||
263 | /** Read DMMU TLB Tag Read Register. |
262 | /** Read DMMU TLB Tag Read Register. |
264 | * |
263 | * |
265 | * @param entry TLB Entry index. |
264 | * @param entry TLB Entry index. |
266 | * |
265 | * |
267 | * @return Current value of specified DMMU TLB Tag Read Register. |
266 | * @return Current value of specified DMMU TLB Tag Read Register. |
268 | */ |
267 | */ |
269 | static inline uint64_t dtlb_tag_read_read(index_t entry) |
268 | static inline uint64_t dtlb_tag_read_read(index_t entry) |
270 | { |
269 | { |
271 | tlb_tag_read_addr_t tag; |
270 | tlb_tag_read_addr_t tag; |
272 | 271 | ||
273 | tag.value = 0; |
272 | tag.value = 0; |
274 | tag.tlb_entry = entry; |
273 | tag.tlb_entry = entry; |
275 | return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value); |
274 | return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value); |
276 | } |
275 | } |
277 | 276 | ||
278 | /** Write IMMU TLB Tag Access Register. |
277 | /** Write IMMU TLB Tag Access Register. |
279 | * |
278 | * |
280 | * @param v Value to be written. |
279 | * @param v Value to be written. |
281 | */ |
280 | */ |
282 | static inline void itlb_tag_access_write(uint64_t v) |
281 | static inline void itlb_tag_access_write(uint64_t v) |
283 | { |
282 | { |
284 | asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v); |
283 | asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v); |
285 | flush(); |
284 | flush(); |
286 | } |
285 | } |
287 | 286 | ||
288 | /** Read IMMU TLB Tag Access Register. |
287 | /** Read IMMU TLB Tag Access Register. |
289 | * |
288 | * |
290 | * @return Current value of IMMU TLB Tag Access Register. |
289 | * @return Current value of IMMU TLB Tag Access Register. |
291 | */ |
290 | */ |
292 | static inline uint64_t itlb_tag_access_read(void) |
291 | static inline uint64_t itlb_tag_access_read(void) |
293 | { |
292 | { |
294 | return asi_u64_read(ASI_IMMU, VA_IMMU_TAG_ACCESS); |
293 | return asi_u64_read(ASI_IMMU, VA_IMMU_TAG_ACCESS); |
295 | } |
294 | } |
296 | 295 | ||
297 | /** Write DMMU TLB Tag Access Register. |
296 | /** Write DMMU TLB Tag Access Register. |
298 | * |
297 | * |
299 | * @param v Value to be written. |
298 | * @param v Value to be written. |
300 | */ |
299 | */ |
301 | static inline void dtlb_tag_access_write(uint64_t v) |
300 | static inline void dtlb_tag_access_write(uint64_t v) |
302 | { |
301 | { |
303 | asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v); |
302 | asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v); |
304 | membar(); |
303 | membar(); |
305 | } |
304 | } |
306 | 305 | ||
307 | /** Read DMMU TLB Tag Access Register. |
306 | /** Read DMMU TLB Tag Access Register. |
308 | * |
307 | * |
309 | * @return Current value of DMMU TLB Tag Access Register. |
308 | * @return Current value of DMMU TLB Tag Access Register. |
310 | */ |
309 | */ |
311 | static inline uint64_t dtlb_tag_access_read(void) |
310 | static inline uint64_t dtlb_tag_access_read(void) |
312 | { |
311 | { |
313 | return asi_u64_read(ASI_DMMU, VA_DMMU_TAG_ACCESS); |
312 | return asi_u64_read(ASI_DMMU, VA_DMMU_TAG_ACCESS); |
314 | } |
313 | } |
315 | 314 | ||
316 | 315 | ||
317 | /** Write IMMU TLB Data in Register. |
316 | /** Write IMMU TLB Data in Register. |
318 | * |
317 | * |
319 | * @param v Value to be written. |
318 | * @param v Value to be written. |
320 | */ |
319 | */ |
321 | static inline void itlb_data_in_write(uint64_t v) |
320 | static inline void itlb_data_in_write(uint64_t v) |
322 | { |
321 | { |
323 | asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v); |
322 | asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v); |
324 | flush(); |
323 | flush(); |
325 | } |
324 | } |
326 | 325 | ||
327 | /** Write DMMU TLB Data in Register. |
326 | /** Write DMMU TLB Data in Register. |
328 | * |
327 | * |
329 | * @param v Value to be written. |
328 | * @param v Value to be written. |
330 | */ |
329 | */ |
331 | static inline void dtlb_data_in_write(uint64_t v) |
330 | static inline void dtlb_data_in_write(uint64_t v) |
332 | { |
331 | { |
333 | asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v); |
332 | asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v); |
334 | membar(); |
333 | membar(); |
335 | } |
334 | } |
336 | 335 | ||
337 | /** Read ITLB Synchronous Fault Status Register. |
336 | /** Read ITLB Synchronous Fault Status Register. |
338 | * |
337 | * |
339 | * @return Current content of I-SFSR register. |
338 | * @return Current content of I-SFSR register. |
340 | */ |
339 | */ |
341 | static inline uint64_t itlb_sfsr_read(void) |
340 | static inline uint64_t itlb_sfsr_read(void) |
342 | { |
341 | { |
343 | return asi_u64_read(ASI_IMMU, VA_IMMU_SFSR); |
342 | return asi_u64_read(ASI_IMMU, VA_IMMU_SFSR); |
344 | } |
343 | } |
345 | 344 | ||
346 | /** Write ITLB Synchronous Fault Status Register. |
345 | /** Write ITLB Synchronous Fault Status Register. |
347 | * |
346 | * |
348 | * @param v New value of I-SFSR register. |
347 | * @param v New value of I-SFSR register. |
349 | */ |
348 | */ |
350 | static inline void itlb_sfsr_write(uint64_t v) |
349 | static inline void itlb_sfsr_write(uint64_t v) |
351 | { |
350 | { |
352 | asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v); |
351 | asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v); |
353 | flush(); |
352 | flush(); |
354 | } |
353 | } |
355 | 354 | ||
356 | /** Read DTLB Synchronous Fault Status Register. |
355 | /** Read DTLB Synchronous Fault Status Register. |
357 | * |
356 | * |
358 | * @return Current content of D-SFSR register. |
357 | * @return Current content of D-SFSR register. |
359 | */ |
358 | */ |
360 | static inline uint64_t dtlb_sfsr_read(void) |
359 | static inline uint64_t dtlb_sfsr_read(void) |
361 | { |
360 | { |
362 | return asi_u64_read(ASI_DMMU, VA_DMMU_SFSR); |
361 | return asi_u64_read(ASI_DMMU, VA_DMMU_SFSR); |
363 | } |
362 | } |
364 | 363 | ||
365 | /** Write DTLB Synchronous Fault Status Register. |
364 | /** Write DTLB Synchronous Fault Status Register. |
366 | * |
365 | * |
367 | * @param v New value of D-SFSR register. |
366 | * @param v New value of D-SFSR register. |
368 | */ |
367 | */ |
369 | static inline void dtlb_sfsr_write(uint64_t v) |
368 | static inline void dtlb_sfsr_write(uint64_t v) |
370 | { |
369 | { |
371 | asi_u64_write(ASI_DMMU, VA_DMMU_SFSR, v); |
370 | asi_u64_write(ASI_DMMU, VA_DMMU_SFSR, v); |
372 | membar(); |
371 | membar(); |
373 | } |
372 | } |
374 | 373 | ||
375 | /** Read DTLB Synchronous Fault Address Register. |
374 | /** Read DTLB Synchronous Fault Address Register. |
376 | * |
375 | * |
377 | * @return Current content of D-SFAR register. |
376 | * @return Current content of D-SFAR register. |
378 | */ |
377 | */ |
379 | static inline uint64_t dtlb_sfar_read(void) |
378 | static inline uint64_t dtlb_sfar_read(void) |
380 | { |
379 | { |
381 | return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR); |
380 | return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR); |
382 | } |
381 | } |
383 | 382 | ||
384 | /** Perform IMMU TLB Demap Operation. |
383 | /** Perform IMMU TLB Demap Operation. |
385 | * |
384 | * |
386 | * @param type Selects between context and page demap. |
385 | * @param type Selects between context and page demap. |
387 | * @param context_encoding Specifies which Context register has Context ID for demap. |
386 | * @param context_encoding Specifies which Context register has Context ID for demap. |
388 | * @param page Address which is on the page to be demapped. |
387 | * @param page Address which is on the page to be demapped. |
389 | */ |
388 | */ |
390 | static inline void itlb_demap(int type, int context_encoding, uintptr_t page) |
389 | static inline void itlb_demap(int type, int context_encoding, uintptr_t page) |
391 | { |
390 | { |
392 | tlb_demap_addr_t da; |
391 | tlb_demap_addr_t da; |
393 | page_address_t pg; |
392 | page_address_t pg; |
394 | 393 | ||
395 | da.value = 0; |
394 | da.value = 0; |
396 | pg.address = page; |
395 | pg.address = page; |
397 | 396 | ||
398 | da.type = type; |
397 | da.type = type; |
399 | da.context = context_encoding; |
398 | da.context = context_encoding; |
400 | da.vpn = pg.vpn; |
399 | da.vpn = pg.vpn; |
401 | 400 | ||
402 | asi_u64_write(ASI_IMMU_DEMAP, da.value, 0); /* da.value is the address within the ASI */ |
401 | asi_u64_write(ASI_IMMU_DEMAP, da.value, 0); /* da.value is the address within the ASI */ |
403 | flush(); |
402 | flush(); |
404 | } |
403 | } |
405 | 404 | ||
406 | /** Perform DMMU TLB Demap Operation. |
405 | /** Perform DMMU TLB Demap Operation. |
407 | * |
406 | * |
408 | * @param type Selects between context and page demap. |
407 | * @param type Selects between context and page demap. |
409 | * @param context_encoding Specifies which Context register has Context ID for demap. |
408 | * @param context_encoding Specifies which Context register has Context ID for demap. |
410 | * @param page Address which is on the page to be demapped. |
409 | * @param page Address which is on the page to be demapped. |
411 | */ |
410 | */ |
412 | static inline void dtlb_demap(int type, int context_encoding, uintptr_t page) |
411 | static inline void dtlb_demap(int type, int context_encoding, uintptr_t page) |
413 | { |
412 | { |
414 | tlb_demap_addr_t da; |
413 | tlb_demap_addr_t da; |
415 | page_address_t pg; |
414 | page_address_t pg; |
416 | 415 | ||
417 | da.value = 0; |
416 | da.value = 0; |
418 | pg.address = page; |
417 | pg.address = page; |
419 | 418 | ||
420 | da.type = type; |
419 | da.type = type; |
421 | da.context = context_encoding; |
420 | da.context = context_encoding; |
422 | da.vpn = pg.vpn; |
421 | da.vpn = pg.vpn; |
423 | 422 | ||
424 | asi_u64_write(ASI_DMMU_DEMAP, da.value, 0); /* da.value is the address within the ASI */ |
423 | asi_u64_write(ASI_DMMU_DEMAP, da.value, 0); /* da.value is the address within the ASI */ |
425 | membar(); |
424 | membar(); |
426 | } |
425 | } |
427 | 426 | ||
428 | extern void fast_instruction_access_mmu_miss(void); |
427 | extern void fast_instruction_access_mmu_miss(int n, istate_t *istate); |
429 | extern void fast_data_access_mmu_miss(void); |
428 | extern void fast_data_access_mmu_miss(int n, istate_t *istate); |
430 | extern void fast_data_access_protection(void); |
429 | extern void fast_data_access_protection(int n, istate_t *istate); |
431 | 430 | ||
432 | extern void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable); |
431 | extern void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable); |
433 | 432 | ||
434 | #endif /* !def __ASM__ */ |
433 | #endif /* !def __ASM__ */ |
435 | 434 | ||
436 | #endif |
435 | #endif |
437 | 436 | ||
438 | /** @} |
437 | /** @} |
439 | */ |
438 | */ |
440 | 439 |