WebSVN – HelenOS – Diff – /branches/rcu/kernel/arch/ia32/src/smp/apic.c


/*
 * Copyright (c) 2001-2004 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup ia32   
 * @{
 */
/** @file
 */
 
#include <arch/types.h>
#include <arch/smp/apic.h>
#include <arch/smp/ap.h>
#include <arch/smp/mps.h>
#include <arch/boot/boot.h>
#include <mm/page.h>
#include <time/delay.h>
#include <interrupt.h>
#include <arch/interrupt.h>
#include <print.h>
#include <arch/asm.h>
#include <arch.h>
#include <ddi/irq.h>
#include <ddi/device.h>
 
#ifdef CONFIG_SMP
 
/*
 * Advanced Programmable Interrupt Controller for SMP systems.
 * Tested on:
 *  Bochs 2.0.2 - Bochs 2.2.6 with 2-8 CPUs
 *  Simics 2.0.28 - Simics 2.2.19 2-15 CPUs
 *  VMware Workstation 5.5 with 2 CPUs
 *  QEMU 0.8.0 with 2-15 CPUs
 *  ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs
 *  ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs
 *  MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs
 */
 
/*
 * These variables either stay configured as initilalized, or are changed by
 * the MP configuration code.
 *
 * Pay special attention to the volatile keyword. Without it, gcc -O2 would
 * optimize the code too much and accesses to l_apic and io_apic, that must
 * always be 32-bit, would use byte oriented instructions.
 */
volatile uint32_t *l_apic = (uint32_t *) 0xfee00000;
volatile uint32_t *io_apic = (uint32_t *) 0xfec00000;
 
uint32_t apic_id_mask = 0;
static irq_t l_apic_timer_irq;
 
static int apic_poll_errors(void);
 
#ifdef LAPIC_VERBOSE
static char *delmod_str[] = {
    "Fixed",
    "Lowest Priority",
    "SMI",
    "Reserved",
    "NMI",
    "INIT",
    "STARTUP",
    "ExtInt"
};
 
static char *destmod_str[] = {
    "Physical",
    "Logical"
};
 
static char *trigmod_str[] = {
    "Edge",
    "Level"
};
 
static char *mask_str[] = {
    "Unmasked",
    "Masked"
};
 
static char *delivs_str[] = {
    "Idle",
    "Send Pending"
};
 
static char *tm_mode_str[] = {
    "One-shot",
    "Periodic"
};
 
static char *intpol_str[] = {
    "Polarity High",
    "Polarity Low"
};
#endif /* LAPIC_VERBOSE */
 
/** APIC spurious interrupt handler.
 *
 * @param n Interrupt vector.
 * @param istate Interrupted state.
 */
static void apic_spurious(int n, istate_t *istate)
{
#ifdef CONFIG_DEBUG
    printf("cpu%d: APIC spurious interrupt\n", CPU->id);
#endif
}
 
static irq_ownership_t l_apic_timer_claim(void)
{
    return IRQ_ACCEPT;
}
 
static void l_apic_timer_irq_handler(irq_t *irq, void *arg, ...)
{
 
 
 
 
 
 
    clock();
 
}
 
/** Initialize APIC on BSP. */
void apic_init(void)
{
    io_apic_id_t idreg;
    unsigned int i;
 
    exc_register(VECTOR_APIC_SPUR, "apic_spurious", (iroutine) apic_spurious);
 
    enable_irqs_function = io_apic_enable_irqs;
    disable_irqs_function = io_apic_disable_irqs;
    eoi_function = l_apic_eoi;
   
    /*
     * Configure interrupt routing.
     * IRQ 0 remains masked as the time signal is generated by l_apic's themselves.
     * Other interrupts will be forwarded to the lowest priority CPU.
     */
    io_apic_disable_irqs(0xffff);
   
    irq_initialize(&l_apic_timer_irq);
 
    l_apic_timer_irq.devno = device_assign_devno();
    l_apic_timer_irq.inr = IRQ_CLK;
    l_apic_timer_irq.claim = l_apic_timer_claim;
    l_apic_timer_irq.handler = l_apic_timer_irq_handler;
    irq_register(&l_apic_timer_irq);
   
    for (i = 0; i < IRQ_COUNT; i++) {
        int pin;
   
        if ((pin = smp_irq_to_pin(i)) != -1)
            io_apic_change_ioredtbl(pin, DEST_ALL, IVT_IRQBASE + i, LOPRI);
    }
   
    /*
     * Ensure that io_apic has unique ID.
     */
    idreg.value = io_apic_read(IOAPICID);
    if ((1 << idreg.apic_id) & apic_id_mask) {  /* see if IO APIC ID is used already */
        for (i = 0; i < APIC_ID_COUNT; i++) {
            if (!((1 << i) & apic_id_mask)) {
                idreg.apic_id = i;
                io_apic_write(IOAPICID, idreg.value);
                break;
            }
        }
    }
 
    /*
     * Configure the BSP's lapic.
     */
    l_apic_init();
 
    l_apic_debug();
}
 
/** Poll for APIC errors.
 *
 * Examine Error Status Register and report all errors found.
 *
 * @return 0 on error, 1 on success.
 */
int apic_poll_errors(void)
{
    esr_t esr;
   
    esr.value = l_apic[ESR];
   
    if (esr.send_checksum_error)
        printf("Send Checksum Error\n");
    if (esr.receive_checksum_error)
        printf("Receive Checksum Error\n");
    if (esr.send_accept_error)
        printf("Send Accept Error\n");
    if (esr.receive_accept_error)
        printf("Receive Accept Error\n");
    if (esr.send_illegal_vector)
        printf("Send Illegal Vector\n");
    if (esr.received_illegal_vector)
        printf("Received Illegal Vector\n");
    if (esr.illegal_register_address)
        printf("Illegal Register Address\n");
 
    return !esr.err_bitmap;
}
 
/** Send all CPUs excluding CPU IPI vector.
 *
 * @param vector Interrupt vector to be sent.
 *
 * @return 0 on failure, 1 on success.
 */
int l_apic_broadcast_custom_ipi(uint8_t vector)
{
    icr_t icr;
 
    icr.lo = l_apic[ICRlo];
    icr.delmod = DELMOD_FIXED;
    icr.destmod = DESTMOD_LOGIC;
    icr.level = LEVEL_ASSERT;
    icr.shorthand = SHORTHAND_ALL_EXCL;
    icr.trigger_mode = TRIGMOD_LEVEL;
    icr.vector = vector;
 
    l_apic[ICRlo] = icr.lo;
 
    icr.lo = l_apic[ICRlo];
    if (icr.delivs == DELIVS_PENDING) {
#ifdef CONFIG_DEBUG
        printf("IPI is pending.\n");
#endif
    }
 
    return apic_poll_errors();
}
 
/** Universal Start-up Algorithm for bringing up the AP processors.
 *
 * @param apicid APIC ID of the processor to be brought up.
 *
 * @return 0 on failure, 1 on success.
 */
int l_apic_send_init_ipi(uint8_t apicid)
{
    icr_t icr;
    int i;
 
    /*
     * Read the ICR register in and zero all non-reserved fields.
     */
    icr.lo = l_apic[ICRlo];
    icr.hi = l_apic[ICRhi];
   
    icr.delmod = DELMOD_INIT;
    icr.destmod = DESTMOD_PHYS;
    icr.level = LEVEL_ASSERT;
    icr.trigger_mode = TRIGMOD_LEVEL;
    icr.shorthand = SHORTHAND_NONE;
    icr.vector = 0;
    icr.dest = apicid;
   
    l_apic[ICRhi] = icr.hi;
    l_apic[ICRlo] = icr.lo;
 
    /*
     * According to MP Specification, 20us should be enough to
     * deliver the IPI.
     */
    delay(20);
 
    if (!apic_poll_errors())
        return 0;
 
    icr.lo = l_apic[ICRlo];
    if (icr.delivs == DELIVS_PENDING) {
#ifdef CONFIG_DEBUG
        printf("IPI is pending.\n");
#endif
    }
 
    icr.delmod = DELMOD_INIT;
    icr.destmod = DESTMOD_PHYS;
    icr.level = LEVEL_DEASSERT;
    icr.shorthand = SHORTHAND_NONE;
    icr.trigger_mode = TRIGMOD_LEVEL;
    icr.vector = 0;
    l_apic[ICRlo] = icr.lo;
 
    /*
     * Wait 10ms as MP Specification specifies.
     */
    delay(10000);
 
    if (!is_82489DX_apic(l_apic[LAVR])) {
        /*
         * If this is not 82489DX-based l_apic we must send two STARTUP IPI's.
         */
        for (i = 0; i<2; i++) {
            icr.lo = l_apic[ICRlo];
            icr.vector = ((uintptr_t) ap_boot) / 4096; /* calculate the reset vector */
            icr.delmod = DELMOD_STARTUP;
            icr.destmod = DESTMOD_PHYS;
            icr.level = LEVEL_ASSERT;
            icr.shorthand = SHORTHAND_NONE;
            icr.trigger_mode = TRIGMOD_LEVEL;
            l_apic[ICRlo] = icr.lo;
            delay(200);
        }
    }
   
    return apic_poll_errors();
}
 
/** Initialize Local APIC. */
void l_apic_init(void)
{
    lvt_error_t error;
    lvt_lint_t lint;
    tpr_t tpr;
    svr_t svr;
    icr_t icr;
    tdcr_t tdcr;
    lvt_tm_t tm;
    ldr_t ldr;
    dfr_t dfr;
    uint32_t t1, t2;
 
    /* Initialize LVT Error register. */
    error.value = l_apic[LVT_Err];
    error.masked = true;
    l_apic[LVT_Err] = error.value;
 
    /* Initialize LVT LINT0 register. */
    lint.value = l_apic[LVT_LINT0];
    lint.masked = true;
    l_apic[LVT_LINT0] = lint.value;
 
    /* Initialize LVT LINT1 register. */
    lint.value = l_apic[LVT_LINT1];
    lint.masked = true;
    l_apic[LVT_LINT1] = lint.value;
 
    /* Task Priority Register initialization. */
    tpr.value = l_apic[TPR];
    tpr.pri_sc = 0;
    tpr.pri = 0;
    l_apic[TPR] = tpr.value;
   
    /* Spurious-Interrupt Vector Register initialization. */
    svr.value = l_apic[SVR];
    svr.vector = VECTOR_APIC_SPUR;
    svr.lapic_enabled = true;
    svr.focus_checking = true;
    l_apic[SVR] = svr.value;
 
    if (CPU->arch.family >= 6)
        enable_l_apic_in_msr();
   
    /* Interrupt Command Register initialization. */
    icr.lo = l_apic[ICRlo];
    icr.delmod = DELMOD_INIT;
    icr.destmod = DESTMOD_PHYS;
    icr.level = LEVEL_DEASSERT;
    icr.shorthand = SHORTHAND_ALL_INCL;
    icr.trigger_mode = TRIGMOD_LEVEL;
    l_apic[ICRlo] = icr.lo;
   
    /* Timer Divide Configuration Register initialization. */
    tdcr.value = l_apic[TDCR];
    tdcr.div_value = DIVIDE_1;
    l_apic[TDCR] = tdcr.value;
 
    /* Program local timer. */
    tm.value = l_apic[LVT_Tm];
    tm.vector = VECTOR_CLK;
    tm.mode = TIMER_PERIODIC;
    tm.masked = false;
    l_apic[LVT_Tm] = tm.value;
 
    /*
     * Measure and configure the timer to generate timer
     * interrupt with period 1s/HZ seconds.
     */
    t1 = l_apic[CCRT];
    l_apic[ICRT] = 0xffffffff;
 
    while (l_apic[CCRT] == t1)
        ;
       
    t1 = l_apic[CCRT];
    delay(1000000/HZ);
    t2 = l_apic[CCRT];
   
    l_apic[ICRT] = t1-t2;
   
    /* Program Logical Destination Register. */
    ldr.value = l_apic[LDR];
    if (CPU->id < sizeof(CPU->id)*8)    /* size in bits */
        ldr.id = (1<<CPU->id);
    l_apic[LDR] = ldr.value;
   
    /* Program Destination Format Register for Flat mode. */
    dfr.value = l_apic[DFR];
    dfr.model = MODEL_FLAT;
    l_apic[DFR] = dfr.value;
}
 
/** Local APIC End of Interrupt. */
void l_apic_eoi(void)
{
    l_apic[EOI] = 0;
}
 
/** Dump content of Local APIC registers. */
void l_apic_debug(void)
{
#ifdef LAPIC_VERBOSE
    lvt_tm_t tm;
    lvt_lint_t lint;
    lvt_error_t error; 
   
    printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id());
 
    tm.value = l_apic[LVT_Tm];
    printf("LVT Tm: vector=%hhd, %s, %s, %s\n", tm.vector, delivs_str[tm.delivs], mask_str[tm.masked], tm_mode_str[tm.mode]);
    lint.value = l_apic[LVT_LINT0];
    printf("LVT LINT0: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]);
    lint.value = l_apic[LVT_LINT1];
    printf("LVT LINT1: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]); 
    error.value = l_apic[LVT_Err];
    printf("LVT Err: vector=%hhd, %s, %s\n", error.vector, delivs_str[error.delivs], mask_str[error.masked]);
#endif
}
 
/** Get Local APIC ID.
 *
 * @return Local APIC ID.
 */
uint8_t l_apic_id(void)
{
    l_apic_id_t idreg;
   
    idreg.value = l_apic[L_APIC_ID];
    return idreg.apic_id;
}
 
/** Read from IO APIC register.
 *
 * @param address IO APIC register address.
 *
 * @return Content of the addressed IO APIC register.
 */
uint32_t io_apic_read(uint8_t address)
{
    io_regsel_t regsel;
   
    regsel.value = io_apic[IOREGSEL];
    regsel.reg_addr = address;
    io_apic[IOREGSEL] = regsel.value;
    return io_apic[IOWIN];
}
 
/** Write to IO APIC register.
 *
 * @param address IO APIC register address.
 * @param x Content to be written to the addressed IO APIC register.
 */
void io_apic_write(uint8_t address, uint32_t x)
{
    io_regsel_t regsel;
   
    regsel.value = io_apic[IOREGSEL];
    regsel.reg_addr = address;
    io_apic[IOREGSEL] = regsel.value;
    io_apic[IOWIN] = x;
}
 
/** Change some attributes of one item in I/O Redirection Table.
 *
 * @param pin IO APIC pin number.
 * @param dest Interrupt destination address.
 * @param v Interrupt vector to trigger.
 * @param flags Flags.
 */
void io_apic_change_ioredtbl(int pin, int dest, uint8_t v, int flags)
{
    io_redirection_reg_t reg;
    int dlvr = DELMOD_FIXED;
   
    if (flags & LOPRI)
        dlvr = DELMOD_LOWPRI;
 
    reg.lo = io_apic_read(IOREDTBL + pin*2);
    reg.hi = io_apic_read(IOREDTBL + pin*2 + 1);
   
    reg.dest = dest;
    reg.destmod = DESTMOD_LOGIC;
    reg.trigger_mode = TRIGMOD_EDGE;
    reg.intpol = POLARITY_HIGH;
    reg.delmod = dlvr;
    reg.intvec = v;
 
    io_apic_write(IOREDTBL + pin*2, reg.lo);
    io_apic_write(IOREDTBL + pin*2 + 1, reg.hi);
}
 
/** Mask IRQs in IO APIC.
 *
 * @param irqmask Bitmask of IRQs to be masked (0 = do not mask, 1 = mask).
 */
void io_apic_disable_irqs(uint16_t irqmask)
{
    io_redirection_reg_t reg;
    unsigned int i;
    int pin;
   
    for (i = 0; i < 16; i++) {
        if (irqmask & (1 << i)) {
            /*
             * Mask the signal input in IO APIC if there is a
             * mapping for the respective IRQ number.
             */
            pin = smp_irq_to_pin(i);
            if (pin != -1) {
                reg.lo = io_apic_read(IOREDTBL + pin * 2);
                reg.masked = true;
                io_apic_write(IOREDTBL + pin * 2, reg.lo);
            }
           
        }
    }
}
 
/** Unmask IRQs in IO APIC.
 *
 * @param irqmask Bitmask of IRQs to be unmasked (0 = do not unmask, 1 = unmask).
 */
void io_apic_enable_irqs(uint16_t irqmask)
{
    unsigned int i;
    int pin;
    io_redirection_reg_t reg;  
   
    for (i = 0;i < 16; i++) {
        if (irqmask & (1 << i)) {
            /*
             * Unmask the signal input in IO APIC if there is a
             * mapping for the respective IRQ number.
             */
            pin = smp_irq_to_pin(i);
            if (pin != -1) {
                reg.lo = io_apic_read(IOREDTBL + pin * 2);
                reg.masked = false;
                io_apic_write(IOREDTBL + pin * 2, reg.lo);
            }
           
        }
    }
}
 
#endif /* CONFIG_SMP */
 
/** @}
 */
 

Rev 2265	Rev 2292
1	/*	1	/*
2	* Copyright (c) 2001-2004 Jakub Jermar	2	* Copyright (c) 2001-2004 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup ia32	29	/** @addtogroup ia32
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#include <arch/types.h>	35	#include <arch/types.h>
36	#include <arch/smp/apic.h>	36	#include <arch/smp/apic.h>
37	#include <arch/smp/ap.h>	37	#include <arch/smp/ap.h>
38	#include <arch/smp/mps.h>	38	#include <arch/smp/mps.h>
39	#include <arch/boot/boot.h>	39	#include <arch/boot/boot.h>
40	#include <mm/page.h>	40	#include <mm/page.h>
41	#include <time/delay.h>	41	#include <time/delay.h>
42	#include <interrupt.h>	42	#include <interrupt.h>
43	#include <arch/interrupt.h>	43	#include <arch/interrupt.h>
44	#include <print.h>	44	#include <print.h>
45	#include <arch/asm.h>	45	#include <arch/asm.h>
46	#include <arch.h>	46	#include <arch.h>
47	#include <ddi/irq.h>	47	#include <ddi/irq.h>
48	#include <ddi/device.h>	48	#include <ddi/device.h>
49		49
50	#ifdef CONFIG_SMP	50	#ifdef CONFIG_SMP
51		51
52	/*	52	/*
53	* Advanced Programmable Interrupt Controller for SMP systems.	53	* Advanced Programmable Interrupt Controller for SMP systems.
54	* Tested on:	54	* Tested on:
55	* Bochs 2.0.2 - Bochs 2.2.6 with 2-8 CPUs	55	* Bochs 2.0.2 - Bochs 2.2.6 with 2-8 CPUs
56	* Simics 2.0.28 - Simics 2.2.19 2-15 CPUs	56	* Simics 2.0.28 - Simics 2.2.19 2-15 CPUs
57	* VMware Workstation 5.5 with 2 CPUs	57	* VMware Workstation 5.5 with 2 CPUs
58	* QEMU 0.8.0 with 2-15 CPUs	58	* QEMU 0.8.0 with 2-15 CPUs
59	* ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs	59	* ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs
60	* ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs	60	* ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs
61	* MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs	61	* MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs
62	*/	62	*/
63		63
64	/*	64	/*
65	* These variables either stay configured as initilalized, or are changed by	65	* These variables either stay configured as initilalized, or are changed by
66	* the MP configuration code.	66	* the MP configuration code.
67	*	67	*
68	* Pay special attention to the volatile keyword. Without it, gcc -O2 would	68	* Pay special attention to the volatile keyword. Without it, gcc -O2 would
69	* optimize the code too much and accesses to l_apic and io_apic, that must	69	* optimize the code too much and accesses to l_apic and io_apic, that must
70	* always be 32-bit, would use byte oriented instructions.	70	* always be 32-bit, would use byte oriented instructions.
71	*/	71	*/
72	volatile uint32_t l_apic = (uint32_t ) 0xfee00000;	72	volatile uint32_t l_apic = (uint32_t ) 0xfee00000;
73	volatile uint32_t io_apic = (uint32_t ) 0xfec00000;	73	volatile uint32_t io_apic = (uint32_t ) 0xfec00000;
74		74
75	uint32_t apic_id_mask = 0;	75	uint32_t apic_id_mask = 0;
76	static irq_t l_apic_timer_irq;	76	static irq_t l_apic_timer_irq;
77		77
78	static int apic_poll_errors(void);	78	static int apic_poll_errors(void);
79		79
80	#ifdef LAPIC_VERBOSE	80	#ifdef LAPIC_VERBOSE
81	static char *delmod_str[] = {	81	static char *delmod_str[] = {
82	"Fixed",	82	"Fixed",
83	"Lowest Priority",	83	"Lowest Priority",
84	"SMI",	84	"SMI",
85	"Reserved",	85	"Reserved",
86	"NMI",	86	"NMI",
87	"INIT",	87	"INIT",
88	"STARTUP",	88	"STARTUP",
89	"ExtInt"	89	"ExtInt"
90	};	90	};
91		91
92	static char *destmod_str[] = {	92	static char *destmod_str[] = {
93	"Physical",	93	"Physical",
94	"Logical"	94	"Logical"
95	};	95	};
96		96
97	static char *trigmod_str[] = {	97	static char *trigmod_str[] = {
98	"Edge",	98	"Edge",
99	"Level"	99	"Level"
100	};	100	};
101		101
102	static char *mask_str[] = {	102	static char *mask_str[] = {
103	"Unmasked",	103	"Unmasked",
104	"Masked"	104	"Masked"
105	};	105	};
106		106
107	static char *delivs_str[] = {	107	static char *delivs_str[] = {
108	"Idle",	108	"Idle",
109	"Send Pending"	109	"Send Pending"
110	};	110	};
111		111
112	static char *tm_mode_str[] = {	112	static char *tm_mode_str[] = {
113	"One-shot",	113	"One-shot",
114	"Periodic"	114	"Periodic"
115	};	115	};
116		116
117	static char *intpol_str[] = {	117	static char *intpol_str[] = {
118	"Polarity High",	118	"Polarity High",
119	"Polarity Low"	119	"Polarity Low"
120	};	120	};
121	#endif /* LAPIC_VERBOSE */	121	#endif /* LAPIC_VERBOSE */
122		122
123	/** APIC spurious interrupt handler.	123	/** APIC spurious interrupt handler.
124	*	124	*
125	* @param n Interrupt vector.	125	* @param n Interrupt vector.
126	* @param istate Interrupted state.	126	* @param istate Interrupted state.
127	*/	127	*/
128	static void apic_spurious(int n, istate_t *istate)	128	static void apic_spurious(int n, istate_t *istate)
129	{	129	{
130	#ifdef CONFIG_DEBUG	130	#ifdef CONFIG_DEBUG
131	printf("cpu%d: APIC spurious interrupt\n", CPU->id);	131	printf("cpu%d: APIC spurious interrupt\n", CPU->id);
132	#endif	132	#endif
133	}	133	}
134		134
135	static irq_ownership_t l_apic_timer_claim(void)	135	static irq_ownership_t l_apic_timer_claim(void)
136	{	136	{
137	return IRQ_ACCEPT;	137	return IRQ_ACCEPT;
138	}	138	}
139		139
140	static void l_apic_timer_irq_handler(irq_t irq, void arg, ...)	140	static void l_apic_timer_irq_handler(irq_t irq, void arg, ...)
141	{	141	{
142	/*	-
143	* Holding a spinlock could prevent clock() from preempting	-
144	* the current thread. In this case, we don't need to hold the	-
145	* irq->lock so we just unlock it and then lock it again.	-
146	*/	-
147	spinlock_unlock(&irq->lock);	-
148	clock();	142	clock();
149	spinlock_lock(&irq->lock);	-
150	}	143	}
151		144
152	/** Initialize APIC on BSP. */	145	/** Initialize APIC on BSP. */
153	void apic_init(void)	146	void apic_init(void)
154	{	147	{
155	io_apic_id_t idreg;	148	io_apic_id_t idreg;
156	unsigned int i;	149	unsigned int i;
157		150
158	exc_register(VECTOR_APIC_SPUR, "apic_spurious", (iroutine) apic_spurious);	151	exc_register(VECTOR_APIC_SPUR, "apic_spurious", (iroutine) apic_spurious);
159		152
160	enable_irqs_function = io_apic_enable_irqs;	153	enable_irqs_function = io_apic_enable_irqs;
161	disable_irqs_function = io_apic_disable_irqs;	154	disable_irqs_function = io_apic_disable_irqs;
162	eoi_function = l_apic_eoi;	155	eoi_function = l_apic_eoi;
163		156
164	/*	157	/*
165	* Configure interrupt routing.	158	* Configure interrupt routing.
166	* IRQ 0 remains masked as the time signal is generated by l_apic's themselves.	159	* IRQ 0 remains masked as the time signal is generated by l_apic's themselves.
167	* Other interrupts will be forwarded to the lowest priority CPU.	160	* Other interrupts will be forwarded to the lowest priority CPU.
168	*/	161	*/
169	io_apic_disable_irqs(0xffff);	162	io_apic_disable_irqs(0xffff);
170		163
171	irq_initialize(&l_apic_timer_irq);	164	irq_initialize(&l_apic_timer_irq);
172	l_apic_timer_irq.preack = true;	-
173	l_apic_timer_irq.devno = device_assign_devno();	165	l_apic_timer_irq.devno = device_assign_devno();
174	l_apic_timer_irq.inr = IRQ_CLK;	166	l_apic_timer_irq.inr = IRQ_CLK;
175	l_apic_timer_irq.claim = l_apic_timer_claim;	167	l_apic_timer_irq.claim = l_apic_timer_claim;
176	l_apic_timer_irq.handler = l_apic_timer_irq_handler;	168	l_apic_timer_irq.handler = l_apic_timer_irq_handler;
177	irq_register(&l_apic_timer_irq);	169	irq_register(&l_apic_timer_irq);
178		170
179	for (i = 0; i < IRQ_COUNT; i++) {	171	for (i = 0; i < IRQ_COUNT; i++) {
180	int pin;	172	int pin;
181		173
182	if ((pin = smp_irq_to_pin(i)) != -1)	174	if ((pin = smp_irq_to_pin(i)) != -1)
183	io_apic_change_ioredtbl(pin, DEST_ALL, IVT_IRQBASE + i, LOPRI);	175	io_apic_change_ioredtbl(pin, DEST_ALL, IVT_IRQBASE + i, LOPRI);
184	}	176	}
185		177
186	/*	178	/*
187	* Ensure that io_apic has unique ID.	179	* Ensure that io_apic has unique ID.
188	*/	180	*/
189	idreg.value = io_apic_read(IOAPICID);	181	idreg.value = io_apic_read(IOAPICID);
190	if ((1 << idreg.apic_id) & apic_id_mask) { /* see if IO APIC ID is used already */	182	if ((1 << idreg.apic_id) & apic_id_mask) { /* see if IO APIC ID is used already */
191	for (i = 0; i < APIC_ID_COUNT; i++) {	183	for (i = 0; i < APIC_ID_COUNT; i++) {
192	if (!((1 << i) & apic_id_mask)) {	184	if (!((1 << i) & apic_id_mask)) {
193	idreg.apic_id = i;	185	idreg.apic_id = i;
194	io_apic_write(IOAPICID, idreg.value);	186	io_apic_write(IOAPICID, idreg.value);
195	break;	187	break;
196	}	188	}
197	}	189	}
198	}	190	}
199		191
200	/*	192	/*
201	* Configure the BSP's lapic.	193	* Configure the BSP's lapic.
202	*/	194	*/
203	l_apic_init();	195	l_apic_init();
204		196
205	l_apic_debug();	197	l_apic_debug();
206	}	198	}
207		199
208	/** Poll for APIC errors.	200	/** Poll for APIC errors.
209	*	201	*
210	* Examine Error Status Register and report all errors found.	202	* Examine Error Status Register and report all errors found.
211	*	203	*
212	* @return 0 on error, 1 on success.	204	* @return 0 on error, 1 on success.
213	*/	205	*/
214	int apic_poll_errors(void)	206	int apic_poll_errors(void)
215	{	207	{
216	esr_t esr;	208	esr_t esr;
217		209
218	esr.value = l_apic[ESR];	210	esr.value = l_apic[ESR];
219		211
220	if (esr.send_checksum_error)	212	if (esr.send_checksum_error)
221	printf("Send Checksum Error\n");	213	printf("Send Checksum Error\n");
222	if (esr.receive_checksum_error)	214	if (esr.receive_checksum_error)
223	printf("Receive Checksum Error\n");	215	printf("Receive Checksum Error\n");
224	if (esr.send_accept_error)	216	if (esr.send_accept_error)
225	printf("Send Accept Error\n");	217	printf("Send Accept Error\n");
226	if (esr.receive_accept_error)	218	if (esr.receive_accept_error)
227	printf("Receive Accept Error\n");	219	printf("Receive Accept Error\n");
228	if (esr.send_illegal_vector)	220	if (esr.send_illegal_vector)
229	printf("Send Illegal Vector\n");	221	printf("Send Illegal Vector\n");
230	if (esr.received_illegal_vector)	222	if (esr.received_illegal_vector)
231	printf("Received Illegal Vector\n");	223	printf("Received Illegal Vector\n");
232	if (esr.illegal_register_address)	224	if (esr.illegal_register_address)
233	printf("Illegal Register Address\n");	225	printf("Illegal Register Address\n");
234		226
235	return !esr.err_bitmap;	227	return !esr.err_bitmap;
236	}	228	}
237		229
238	/** Send all CPUs excluding CPU IPI vector.	230	/** Send all CPUs excluding CPU IPI vector.
239	*	231	*
240	* @param vector Interrupt vector to be sent.	232	* @param vector Interrupt vector to be sent.
241	*	233	*
242	* @return 0 on failure, 1 on success.	234	* @return 0 on failure, 1 on success.
243	*/	235	*/
244	int l_apic_broadcast_custom_ipi(uint8_t vector)	236	int l_apic_broadcast_custom_ipi(uint8_t vector)
245	{	237	{
246	icr_t icr;	238	icr_t icr;
247		239
248	icr.lo = l_apic[ICRlo];	240	icr.lo = l_apic[ICRlo];
249	icr.delmod = DELMOD_FIXED;	241	icr.delmod = DELMOD_FIXED;
250	icr.destmod = DESTMOD_LOGIC;	242	icr.destmod = DESTMOD_LOGIC;
251	icr.level = LEVEL_ASSERT;	243	icr.level = LEVEL_ASSERT;
252	icr.shorthand = SHORTHAND_ALL_EXCL;	244	icr.shorthand = SHORTHAND_ALL_EXCL;
253	icr.trigger_mode = TRIGMOD_LEVEL;	245	icr.trigger_mode = TRIGMOD_LEVEL;
254	icr.vector = vector;	246	icr.vector = vector;
255		247
256	l_apic[ICRlo] = icr.lo;	248	l_apic[ICRlo] = icr.lo;
257		249
258	icr.lo = l_apic[ICRlo];	250	icr.lo = l_apic[ICRlo];
259	if (icr.delivs == DELIVS_PENDING) {	251	if (icr.delivs == DELIVS_PENDING) {
260	#ifdef CONFIG_DEBUG	252	#ifdef CONFIG_DEBUG
261	printf("IPI is pending.\n");	253	printf("IPI is pending.\n");
262	#endif	254	#endif
263	}	255	}
264		256
265	return apic_poll_errors();	257	return apic_poll_errors();
266	}	258	}
267		259
268	/** Universal Start-up Algorithm for bringing up the AP processors.	260	/** Universal Start-up Algorithm for bringing up the AP processors.
269	*	261	*
270	* @param apicid APIC ID of the processor to be brought up.	262	* @param apicid APIC ID of the processor to be brought up.
271	*	263	*
272	* @return 0 on failure, 1 on success.	264	* @return 0 on failure, 1 on success.
273	*/	265	*/
274	int l_apic_send_init_ipi(uint8_t apicid)	266	int l_apic_send_init_ipi(uint8_t apicid)
275	{	267	{
276	icr_t icr;	268	icr_t icr;
277	int i;	269	int i;
278		270
279	/*	271	/*
280	* Read the ICR register in and zero all non-reserved fields.	272	* Read the ICR register in and zero all non-reserved fields.
281	*/	273	*/
282	icr.lo = l_apic[ICRlo];	274	icr.lo = l_apic[ICRlo];
283	icr.hi = l_apic[ICRhi];	275	icr.hi = l_apic[ICRhi];
284		276
285	icr.delmod = DELMOD_INIT;	277	icr.delmod = DELMOD_INIT;
286	icr.destmod = DESTMOD_PHYS;	278	icr.destmod = DESTMOD_PHYS;
287	icr.level = LEVEL_ASSERT;	279	icr.level = LEVEL_ASSERT;
288	icr.trigger_mode = TRIGMOD_LEVEL;	280	icr.trigger_mode = TRIGMOD_LEVEL;
289	icr.shorthand = SHORTHAND_NONE;	281	icr.shorthand = SHORTHAND_NONE;
290	icr.vector = 0;	282	icr.vector = 0;
291	icr.dest = apicid;	283	icr.dest = apicid;
292		284
293	l_apic[ICRhi] = icr.hi;	285	l_apic[ICRhi] = icr.hi;
294	l_apic[ICRlo] = icr.lo;	286	l_apic[ICRlo] = icr.lo;
295		287
296	/*	288	/*
297	* According to MP Specification, 20us should be enough to	289	* According to MP Specification, 20us should be enough to
298	* deliver the IPI.	290	* deliver the IPI.
299	*/	291	*/
300	delay(20);	292	delay(20);
301		293
302	if (!apic_poll_errors())	294	if (!apic_poll_errors())
303	return 0;	295	return 0;
304		296
305	icr.lo = l_apic[ICRlo];	297	icr.lo = l_apic[ICRlo];
306	if (icr.delivs == DELIVS_PENDING) {	298	if (icr.delivs == DELIVS_PENDING) {
307	#ifdef CONFIG_DEBUG	299	#ifdef CONFIG_DEBUG
308	printf("IPI is pending.\n");	300	printf("IPI is pending.\n");
309	#endif	301	#endif
310	}	302	}
311		303
312	icr.delmod = DELMOD_INIT;	304	icr.delmod = DELMOD_INIT;
313	icr.destmod = DESTMOD_PHYS;	305	icr.destmod = DESTMOD_PHYS;
314	icr.level = LEVEL_DEASSERT;	306	icr.level = LEVEL_DEASSERT;
315	icr.shorthand = SHORTHAND_NONE;	307	icr.shorthand = SHORTHAND_NONE;
316	icr.trigger_mode = TRIGMOD_LEVEL;	308	icr.trigger_mode = TRIGMOD_LEVEL;
317	icr.vector = 0;	309	icr.vector = 0;
318	l_apic[ICRlo] = icr.lo;	310	l_apic[ICRlo] = icr.lo;
319		311
320	/*	312	/*
321	* Wait 10ms as MP Specification specifies.	313	* Wait 10ms as MP Specification specifies.
322	*/	314	*/
323	delay(10000);	315	delay(10000);
324		316
325	if (!is_82489DX_apic(l_apic[LAVR])) {	317	if (!is_82489DX_apic(l_apic[LAVR])) {
326	/*	318	/*
327	* If this is not 82489DX-based l_apic we must send two STARTUP IPI's.	319	* If this is not 82489DX-based l_apic we must send two STARTUP IPI's.
328	*/	320	*/
329	for (i = 0; i<2; i++) {	321	for (i = 0; i<2; i++) {
330	icr.lo = l_apic[ICRlo];	322	icr.lo = l_apic[ICRlo];
331	icr.vector = ((uintptr_t) ap_boot) / 4096; /* calculate the reset vector */	323	icr.vector = ((uintptr_t) ap_boot) / 4096; /* calculate the reset vector */
332	icr.delmod = DELMOD_STARTUP;	324	icr.delmod = DELMOD_STARTUP;
333	icr.destmod = DESTMOD_PHYS;	325	icr.destmod = DESTMOD_PHYS;
334	icr.level = LEVEL_ASSERT;	326	icr.level = LEVEL_ASSERT;
335	icr.shorthand = SHORTHAND_NONE;	327	icr.shorthand = SHORTHAND_NONE;
336	icr.trigger_mode = TRIGMOD_LEVEL;	328	icr.trigger_mode = TRIGMOD_LEVEL;
337	l_apic[ICRlo] = icr.lo;	329	l_apic[ICRlo] = icr.lo;
338	delay(200);	330	delay(200);
339	}	331	}
340	}	332	}
341		333
342	return apic_poll_errors();	334	return apic_poll_errors();
343	}	335	}
344		336
345	/** Initialize Local APIC. */	337	/** Initialize Local APIC. */
346	void l_apic_init(void)	338	void l_apic_init(void)
347	{	339	{
348	lvt_error_t error;	340	lvt_error_t error;
349	lvt_lint_t lint;	341	lvt_lint_t lint;
350	tpr_t tpr;	342	tpr_t tpr;
351	svr_t svr;	343	svr_t svr;
352	icr_t icr;	344	icr_t icr;
353	tdcr_t tdcr;	345	tdcr_t tdcr;
354	lvt_tm_t tm;	346	lvt_tm_t tm;
355	ldr_t ldr;	347	ldr_t ldr;
356	dfr_t dfr;	348	dfr_t dfr;
357	uint32_t t1, t2;	349	uint32_t t1, t2;
358		350
359	/* Initialize LVT Error register. */	351	/* Initialize LVT Error register. */
360	error.value = l_apic[LVT_Err];	352	error.value = l_apic[LVT_Err];
361	error.masked = true;	353	error.masked = true;
362	l_apic[LVT_Err] = error.value;	354	l_apic[LVT_Err] = error.value;
363		355
364	/* Initialize LVT LINT0 register. */	356	/* Initialize LVT LINT0 register. */
365	lint.value = l_apic[LVT_LINT0];	357	lint.value = l_apic[LVT_LINT0];
366	lint.masked = true;	358	lint.masked = true;
367	l_apic[LVT_LINT0] = lint.value;	359	l_apic[LVT_LINT0] = lint.value;
368		360
369	/* Initialize LVT LINT1 register. */	361	/* Initialize LVT LINT1 register. */
370	lint.value = l_apic[LVT_LINT1];	362	lint.value = l_apic[LVT_LINT1];
371	lint.masked = true;	363	lint.masked = true;
372	l_apic[LVT_LINT1] = lint.value;	364	l_apic[LVT_LINT1] = lint.value;
373		365
374	/* Task Priority Register initialization. */	366	/* Task Priority Register initialization. */
375	tpr.value = l_apic[TPR];	367	tpr.value = l_apic[TPR];
376	tpr.pri_sc = 0;	368	tpr.pri_sc = 0;
377	tpr.pri = 0;	369	tpr.pri = 0;
378	l_apic[TPR] = tpr.value;	370	l_apic[TPR] = tpr.value;
379		371
380	/* Spurious-Interrupt Vector Register initialization. */	372	/* Spurious-Interrupt Vector Register initialization. */
381	svr.value = l_apic[SVR];	373	svr.value = l_apic[SVR];
382	svr.vector = VECTOR_APIC_SPUR;	374	svr.vector = VECTOR_APIC_SPUR;
383	svr.lapic_enabled = true;	375	svr.lapic_enabled = true;
384	svr.focus_checking = true;	376	svr.focus_checking = true;
385	l_apic[SVR] = svr.value;	377	l_apic[SVR] = svr.value;
386		378
387	if (CPU->arch.family >= 6)	379	if (CPU->arch.family >= 6)
388	enable_l_apic_in_msr();	380	enable_l_apic_in_msr();
389		381
390	/* Interrupt Command Register initialization. */	382	/* Interrupt Command Register initialization. */
391	icr.lo = l_apic[ICRlo];	383	icr.lo = l_apic[ICRlo];
392	icr.delmod = DELMOD_INIT;	384	icr.delmod = DELMOD_INIT;
393	icr.destmod = DESTMOD_PHYS;	385	icr.destmod = DESTMOD_PHYS;
394	icr.level = LEVEL_DEASSERT;	386	icr.level = LEVEL_DEASSERT;
395	icr.shorthand = SHORTHAND_ALL_INCL;	387	icr.shorthand = SHORTHAND_ALL_INCL;
396	icr.trigger_mode = TRIGMOD_LEVEL;	388	icr.trigger_mode = TRIGMOD_LEVEL;
397	l_apic[ICRlo] = icr.lo;	389	l_apic[ICRlo] = icr.lo;
398		390
399	/* Timer Divide Configuration Register initialization. */	391	/* Timer Divide Configuration Register initialization. */
400	tdcr.value = l_apic[TDCR];	392	tdcr.value = l_apic[TDCR];
401	tdcr.div_value = DIVIDE_1;	393	tdcr.div_value = DIVIDE_1;
402	l_apic[TDCR] = tdcr.value;	394	l_apic[TDCR] = tdcr.value;
403		395
404	/* Program local timer. */	396	/* Program local timer. */
405	tm.value = l_apic[LVT_Tm];	397	tm.value = l_apic[LVT_Tm];
406	tm.vector = VECTOR_CLK;	398	tm.vector = VECTOR_CLK;
407	tm.mode = TIMER_PERIODIC;	399	tm.mode = TIMER_PERIODIC;
408	tm.masked = false;	400	tm.masked = false;
409	l_apic[LVT_Tm] = tm.value;	401	l_apic[LVT_Tm] = tm.value;
410		402
411	/*	403	/*
412	* Measure and configure the timer to generate timer	404	* Measure and configure the timer to generate timer
413	* interrupt with period 1s/HZ seconds.	405	* interrupt with period 1s/HZ seconds.
414	*/	406	*/
415	t1 = l_apic[CCRT];	407	t1 = l_apic[CCRT];
416	l_apic[ICRT] = 0xffffffff;	408	l_apic[ICRT] = 0xffffffff;
417		409
418	while (l_apic[CCRT] == t1)	410	while (l_apic[CCRT] == t1)
419	;	411	;
420		412
421	t1 = l_apic[CCRT];	413	t1 = l_apic[CCRT];
422	delay(1000000/HZ);	414	delay(1000000/HZ);
423	t2 = l_apic[CCRT];	415	t2 = l_apic[CCRT];
424		416
425	l_apic[ICRT] = t1-t2;	417	l_apic[ICRT] = t1-t2;
426		418
427	/* Program Logical Destination Register. */	419	/* Program Logical Destination Register. */
428	ldr.value = l_apic[LDR];	420	ldr.value = l_apic[LDR];
429	if (CPU->id < sizeof(CPU->id)8) / size in bits */	421	if (CPU->id < sizeof(CPU->id)8) / size in bits */
430	ldr.id = (1<<CPU->id);	422	ldr.id = (1<<CPU->id);
431	l_apic[LDR] = ldr.value;	423	l_apic[LDR] = ldr.value;
432		424
433	/* Program Destination Format Register for Flat mode. */	425	/* Program Destination Format Register for Flat mode. */
434	dfr.value = l_apic[DFR];	426	dfr.value = l_apic[DFR];
435	dfr.model = MODEL_FLAT;	427	dfr.model = MODEL_FLAT;
436	l_apic[DFR] = dfr.value;	428	l_apic[DFR] = dfr.value;
437	}	429	}
438		430
439	/** Local APIC End of Interrupt. */	431	/** Local APIC End of Interrupt. */
440	void l_apic_eoi(void)	432	void l_apic_eoi(void)
441	{	433	{
442	l_apic[EOI] = 0;	434	l_apic[EOI] = 0;
443	}	435	}
444		436
445	/** Dump content of Local APIC registers. */	437	/** Dump content of Local APIC registers. */
446	void l_apic_debug(void)	438	void l_apic_debug(void)
447	{	439	{
448	#ifdef LAPIC_VERBOSE	440	#ifdef LAPIC_VERBOSE
449	lvt_tm_t tm;	441	lvt_tm_t tm;
450	lvt_lint_t lint;	442	lvt_lint_t lint;
451	lvt_error_t error;	443	lvt_error_t error;
452		444
453	printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id());	445	printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id());
454		446
455	tm.value = l_apic[LVT_Tm];	447	tm.value = l_apic[LVT_Tm];
456	printf("LVT Tm: vector=%hhd, %s, %s, %s\n", tm.vector, delivs_str[tm.delivs], mask_str[tm.masked], tm_mode_str[tm.mode]);	448	printf("LVT Tm: vector=%hhd, %s, %s, %s\n", tm.vector, delivs_str[tm.delivs], mask_str[tm.masked], tm_mode_str[tm.mode]);
457	lint.value = l_apic[LVT_LINT0];	449	lint.value = l_apic[LVT_LINT0];
458	printf("LVT LINT0: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]);	450	printf("LVT LINT0: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]);
459	lint.value = l_apic[LVT_LINT1];	451	lint.value = l_apic[LVT_LINT1];
460	printf("LVT LINT1: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]);	452	printf("LVT LINT1: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]);
461	error.value = l_apic[LVT_Err];	453	error.value = l_apic[LVT_Err];
462	printf("LVT Err: vector=%hhd, %s, %s\n", error.vector, delivs_str[error.delivs], mask_str[error.masked]);	454	printf("LVT Err: vector=%hhd, %s, %s\n", error.vector, delivs_str[error.delivs], mask_str[error.masked]);
463	#endif	455	#endif
464	}	456	}
465		457
466	/** Get Local APIC ID.	458	/** Get Local APIC ID.
467	*	459	*
468	* @return Local APIC ID.	460	* @return Local APIC ID.
469	*/	461	*/
470	uint8_t l_apic_id(void)	462	uint8_t l_apic_id(void)
471	{	463	{
472	l_apic_id_t idreg;	464	l_apic_id_t idreg;
473		465
474	idreg.value = l_apic[L_APIC_ID];	466	idreg.value = l_apic[L_APIC_ID];
475	return idreg.apic_id;	467	return idreg.apic_id;
476	}	468	}
477		469
478	/** Read from IO APIC register.	470	/** Read from IO APIC register.
479	*	471	*
480	* @param address IO APIC register address.	472	* @param address IO APIC register address.
481	*	473	*
482	* @return Content of the addressed IO APIC register.	474	* @return Content of the addressed IO APIC register.
483	*/	475	*/
484	uint32_t io_apic_read(uint8_t address)	476	uint32_t io_apic_read(uint8_t address)
485	{	477	{
486	io_regsel_t regsel;	478	io_regsel_t regsel;
487		479
488	regsel.value = io_apic[IOREGSEL];	480	regsel.value = io_apic[IOREGSEL];
489	regsel.reg_addr = address;	481	regsel.reg_addr = address;
490	io_apic[IOREGSEL] = regsel.value;	482	io_apic[IOREGSEL] = regsel.value;
491	return io_apic[IOWIN];	483	return io_apic[IOWIN];
492	}	484	}
493		485
494	/** Write to IO APIC register.	486	/** Write to IO APIC register.
495	*	487	*
496	* @param address IO APIC register address.	488	* @param address IO APIC register address.
497	* @param x Content to be written to the addressed IO APIC register.	489	* @param x Content to be written to the addressed IO APIC register.
498	*/	490	*/
499	void io_apic_write(uint8_t address, uint32_t x)	491	void io_apic_write(uint8_t address, uint32_t x)
500	{	492	{

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(root)/branches/rcu/kernel/arch/ia32/src/smp/apic.c @ 4757 – Rev 2265 → 2292