Rev 216 | Rev 224 | Go to most recent revision | Only display areas with differences | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
Rev 216 | Rev 219 | ||
---|---|---|---|
1 | /* |
1 | /* |
2 | * Copyright (C) 2005 Jakub Jermar |
2 | * Copyright (C) 2005 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | #ifndef __amd64_ASM_H__ |
29 | #ifndef __amd64_ASM_H__ |
30 | #define __amd64_ASM_H__ |
30 | #define __amd64_ASM_H__ |
31 | 31 | ||
32 | #include <arch/types.h> |
32 | #include <arch/types.h> |
33 | #include <config.h> |
33 | #include <config.h> |
34 | 34 | ||
35 | 35 | ||
36 | void asm_delay_loop(__u32 t); |
36 | void asm_delay_loop(__u32 t); |
37 | void asm_fake_loop(__u32 t); |
37 | void asm_fake_loop(__u32 t); |
38 | 38 | ||
39 | 39 | ||
40 | /* TODO: implement the real stuff */ |
40 | /* TODO: implement the real stuff */ |
41 | static inline __address get_stack_base(void) |
41 | static inline __address get_stack_base(void) |
42 | { |
42 | { |
43 | return NULL; |
43 | return NULL; |
44 | } |
44 | } |
45 | 45 | ||
46 | static inline void cpu_sleep(void) { __asm__("hlt"); }; |
46 | static inline void cpu_sleep(void) { __asm__("hlt"); }; |
47 | 47 | ||
48 | 48 | ||
49 | static inline __u8 inb(__u16 port) |
49 | static inline __u8 inb(__u16 port) |
50 | { |
50 | { |
51 | __u8 out; |
51 | __u8 out; |
52 | 52 | ||
53 | asm ( |
53 | asm ( |
54 | "mov %0, %%dx;" |
54 | "mov %0, %%dx;" |
55 | "inb %%dx,%%al;" |
55 | "inb %%dx,%%al;" |
56 | "mov %%al, %1;" |
56 | "mov %%al, %1;" |
57 | :"=m"(out) |
57 | :"=m"(out) |
58 | :"m"(port) |
58 | :"m"(port) |
59 | :"%dx","%al" |
59 | :"%dx","%al" |
60 | ); |
60 | ); |
61 | return out; |
61 | return out; |
62 | } |
62 | } |
63 | 63 | ||
64 | static inline __u8 outb(__u16 port,__u8 b) |
64 | static inline __u8 outb(__u16 port,__u8 b) |
65 | { |
65 | { |
66 | asm ( |
66 | asm ( |
67 | "mov %0,%%dx;" |
67 | "mov %0,%%dx;" |
68 | "mov %1,%%al;" |
68 | "mov %1,%%al;" |
69 | "outb %%al,%%dx;" |
69 | "outb %%al,%%dx;" |
70 | : |
70 | : |
71 | :"m"( port), "m" (b) |
71 | :"m"( port), "m" (b) |
72 | :"%dx","%al" |
72 | :"%dx","%al" |
73 | ); |
73 | ); |
74 | } |
74 | } |
75 | 75 | ||
76 | /** Set priority level low |
76 | /** Set priority level low |
77 | * |
77 | * |
78 | * Enable interrupts and return previous |
78 | * Enable interrupts and return previous |
79 | * value of EFLAGS. |
79 | * value of EFLAGS. |
80 | */ |
80 | */ |
81 | static inline pri_t cpu_priority_low(void) { |
81 | static inline pri_t cpu_priority_low(void) { |
82 | pri_t v; |
82 | pri_t v; |
83 | __asm__ volatile ( |
83 | __asm__ volatile ( |
84 | "pushfq\n" |
84 | "pushfq\n" |
85 | "popq %0\n" |
85 | "popq %0\n" |
86 | "sti\n" |
86 | "sti\n" |
87 | : "=r" (v) |
87 | : "=r" (v) |
88 | ); |
88 | ); |
89 | return v; |
89 | return v; |
90 | } |
90 | } |
91 | 91 | ||
92 | /** Set priority level high |
92 | /** Set priority level high |
93 | * |
93 | * |
94 | * Disable interrupts and return previous |
94 | * Disable interrupts and return previous |
95 | * value of EFLAGS. |
95 | * value of EFLAGS. |
96 | */ |
96 | */ |
97 | static inline pri_t cpu_priority_high(void) { |
97 | static inline pri_t cpu_priority_high(void) { |
98 | pri_t v; |
98 | pri_t v; |
99 | __asm__ volatile ( |
99 | __asm__ volatile ( |
100 | "pushfq\n" |
100 | "pushfq\n" |
101 | "popq %0\n" |
101 | "popq %0\n" |
102 | "cli\n" |
102 | "cli\n" |
103 | : "=r" (v) |
103 | : "=r" (v) |
104 | ); |
104 | ); |
105 | return v; |
105 | return v; |
106 | } |
106 | } |
107 | 107 | ||
108 | /** Restore priority level |
108 | /** Restore priority level |
109 | * |
109 | * |
110 | * Restore EFLAGS. |
110 | * Restore EFLAGS. |
111 | */ |
111 | */ |
112 | static inline void cpu_priority_restore(pri_t pri) { |
112 | static inline void cpu_priority_restore(pri_t pri) { |
113 | __asm__ volatile ( |
113 | __asm__ volatile ( |
114 | "pushq %0\n" |
114 | "pushq %0\n" |
115 | "popfq\n" |
115 | "popfq\n" |
116 | : : "r" (pri) |
116 | : : "r" (pri) |
117 | ); |
117 | ); |
118 | } |
118 | } |
119 | 119 | ||
120 | /** Return raw priority level |
120 | /** Return raw priority level |
121 | * |
121 | * |
122 | * Return EFLAFS. |
122 | * Return EFLAFS. |
123 | */ |
123 | */ |
124 | static inline pri_t cpu_priority_read(void) { |
124 | static inline pri_t cpu_priority_read(void) { |
125 | pri_t v; |
125 | pri_t v; |
126 | __asm__ volatile ( |
126 | __asm__ volatile ( |
127 | "pushfq\n" |
127 | "pushfq\n" |
128 | "popq %0\n" |
128 | "popq %0\n" |
129 | : "=r" (v) |
129 | : "=r" (v) |
130 | ); |
130 | ); |
131 | return v; |
131 | return v; |
132 | } |
132 | } |
133 | 133 | ||
134 | /** Read CR2 |
134 | /** Read CR2 |
135 | * |
135 | * |
136 | * Return value in CR2 |
136 | * Return value in CR2 |
137 | * |
137 | * |
138 | * @return Value read. |
138 | * @return Value read. |
139 | */ |
139 | */ |
140 | static inline __u32 read_cr2(void) { __u64 v; __asm__ volatile ("movq %%cr2,%0" : "=r" (v)); return v; } |
140 | static inline __u32 read_cr2(void) { __u64 v; __asm__ volatile ("movq %%cr2,%0" : "=r" (v)); return v; } |
141 | 141 | ||
- | 142 | /** Write CR3 |
|
- | 143 | * |
|
- | 144 | * Write value to CR3. |
|
- | 145 | * |
|
- | 146 | * @param v Value to be written. |
|
- | 147 | */ |
|
- | 148 | static inline void write_cr3(__u64 v) { __asm__ volatile ("movq %0,%%cr3\n" : : "r" (v)); } |
|
- | 149 | ||
- | 150 | /** Read CR3 |
|
- | 151 | * |
|
- | 152 | * Return value in CR3 |
|
- | 153 | * |
|
- | 154 | * @return Value read. |
|
- | 155 | */ |
|
- | 156 | static inline __u32 read_cr3(void) { __u64 v; __asm__ volatile ("movq %%cr3,%0" : "=r" (v)); return v; } |
|
- | 157 | ||
- | 158 | /** Set priority level low |
|
- | 159 | * |
|
- | 160 | * Enable interrupts and return previous |
|
- | 161 | * value of EFLAGS. |
|
- | 162 | */ |
|
- | 163 | ||
- | 164 | ||
142 | 165 | ||
143 | extern size_t interrupt_handler_size; |
166 | extern size_t interrupt_handler_size; |
144 | extern void interrupt_handlers(void); |
167 | extern void interrupt_handlers(void); |
145 | 168 | ||
146 | #endif |
169 | #endif |
147 | 170 |