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1 | # |
1 | # |
2 | # Copyright (c) 2005 Jakub Jermar |
2 | # Copyright (c) 2005 Jakub Jermar |
3 | # All rights reserved. |
3 | # All rights reserved. |
4 | # |
4 | # |
5 | # Redistribution and use in source and binary forms, with or without |
5 | # Redistribution and use in source and binary forms, with or without |
6 | # modification, are permitted provided that the following conditions |
6 | # modification, are permitted provided that the following conditions |
7 | # are met: |
7 | # are met: |
8 | # |
8 | # |
9 | # - Redistributions of source code must retain the above copyright |
9 | # - Redistributions of source code must retain the above copyright |
10 | # notice, this list of conditions and the following disclaimer. |
10 | # notice, this list of conditions and the following disclaimer. |
11 | # - Redistributions in binary form must reproduce the above copyright |
11 | # - Redistributions in binary form must reproduce the above copyright |
12 | # notice, this list of conditions and the following disclaimer in the |
12 | # notice, this list of conditions and the following disclaimer in the |
13 | # documentation and/or other materials provided with the distribution. |
13 | # documentation and/or other materials provided with the distribution. |
14 | # - The name of the author may not be used to endorse or promote products |
14 | # - The name of the author may not be used to endorse or promote products |
15 | # derived from this software without specific prior written permission. |
15 | # derived from this software without specific prior written permission. |
16 | # |
16 | # |
17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | # |
27 | # |
28 | 28 | ||
29 | #include <arch/arch.h> |
29 | #include <arch/arch.h> |
- | 30 | #include <arch/cpu.h> |
|
30 | #include <arch/regdef.h> |
31 | #include <arch/regdef.h> |
31 | #include <arch/boot/boot.h> |
32 | #include <arch/boot/boot.h> |
32 | #include <arch/stack.h> |
33 | #include <arch/stack.h> |
33 | 34 | ||
34 | #include <arch/mm/mmu.h> |
35 | #include <arch/mm/mmu.h> |
35 | #include <arch/mm/tlb.h> |
36 | #include <arch/mm/tlb.h> |
36 | #include <arch/mm/tte.h> |
37 | #include <arch/mm/tte.h> |
37 | 38 | ||
38 | #ifdef CONFIG_SMP |
39 | #ifdef CONFIG_SMP |
39 | #include <arch/context_offset.h> |
40 | #include <arch/context_offset.h> |
40 | #endif |
41 | #endif |
41 | 42 | ||
42 | .register %g2, #scratch |
43 | .register %g2, #scratch |
43 | .register %g3, #scratch |
44 | .register %g3, #scratch |
44 | 45 | ||
45 | .section K_TEXT_START, "ax" |
46 | .section K_TEXT_START, "ax" |
46 | 47 | ||
47 | #define BSP_FLAG 1 |
48 | #define BSP_FLAG 1 |
48 | 49 | ||
49 | /* |
50 | /* |
- | 51 | * 2^PHYSMEM_ADDR_SIZE is the size of the physical address space on |
|
- | 52 | * a given processor. |
|
- | 53 | */ |
|
- | 54 | #if defined (US) |
|
- | 55 | #define PHYSMEM_ADDR_SIZE 41 |
|
- | 56 | #elif defined (US3) |
|
- | 57 | #define PHYSMEM_ADDR_SIZE 43 |
|
- | 58 | #endif |
|
- | 59 | ||
- | 60 | /* |
|
50 | * Here is where the kernel is passed control from the boot loader. |
61 | * Here is where the kernel is passed control from the boot loader. |
51 | * |
62 | * |
52 | * The registers are expected to be in this state: |
63 | * The registers are expected to be in this state: |
53 | * - %o0 starting address of physical memory + bootstrap processor flag |
64 | * - %o0 starting address of physical memory + bootstrap processor flag |
54 | * bits 63...1: physical memory starting address / 2 |
65 | * bits 63...1: physical memory starting address / 2 |
55 | * bit 0: non-zero on BSP processor, zero on AP processors |
66 | * bit 0: non-zero on BSP processor, zero on AP processors |
56 | * - %o1 bootinfo structure address (BSP only) |
67 | * - %o1 bootinfo structure address (BSP only) |
57 | * - %o2 bootinfo structure size (BSP only) |
68 | * - %o2 bootinfo structure size (BSP only) |
58 | * |
69 | * |
59 | * Moreover, we depend on boot having established the following environment: |
70 | * Moreover, we depend on boot having established the following environment: |
60 | * - TLBs are on |
71 | * - TLBs are on |
61 | * - identity mapping for the kernel image |
72 | * - identity mapping for the kernel image |
62 | */ |
73 | */ |
63 | 74 | ||
64 | .global kernel_image_start |
75 | .global kernel_image_start |
65 | kernel_image_start: |
76 | kernel_image_start: |
66 | mov BSP_FLAG, %l0 |
77 | mov BSP_FLAG, %l0 |
67 | and %o0, %l0, %l7 ! l7 <= bootstrap processor? |
78 | and %o0, %l0, %l7 ! l7 <= bootstrap processor? |
68 | andn %o0, %l0, %l6 ! l6 <= start of physical memory |
79 | andn %o0, %l0, %l6 ! l6 <= start of physical memory |
69 | 80 | ||
70 | ! Get bits 40:13 of physmem_base. |
81 | ! Get bits (PHYSMEM_ADDR_SIZE - 1):13 of physmem_base. |
71 | srlx %l6, 13, %l5 |
82 | srlx %l6, 13, %l5 |
- | 83 | ||
- | 84 | ! l5 <= physmem_base[(PHYSMEM_ADDR_SIZE - 1):13] |
|
72 | sllx %l5, 13 + (63 - 40), %l5 |
85 | sllx %l5, 13 + (63 - (PHYSMEM_ADDR_SIZE - 1)), %l5 |
73 | srlx %l5, 63 - 40, %l5 ! l5 <= physmem_base[40:13] |
86 | srlx %l5, 63 - (PHYSMEM_ADDR_SIZE - 1), %l5 |
74 | 87 | ||
75 | /* |
88 | /* |
76 | * Setup basic runtime environment. |
89 | * Setup basic runtime environment. |
77 | */ |
90 | */ |
78 | 91 | ||
79 | wrpr %g0, NWINDOWS - 2, %cansave ! set maximum saveable windows |
92 | wrpr %g0, NWINDOWS - 2, %cansave ! set maximum saveable windows |
80 | wrpr %g0, 0, %canrestore ! get rid of windows we will |
93 | wrpr %g0, 0, %canrestore ! get rid of windows we will |
81 | ! never need again |
94 | ! never need again |
82 | wrpr %g0, 0, %otherwin ! make sure the window state is |
95 | wrpr %g0, 0, %otherwin ! make sure the window state is |
83 | ! consistent |
96 | ! consistent |
84 | wrpr %g0, NWINDOWS - 1, %cleanwin ! prevent needless clean_window |
97 | wrpr %g0, NWINDOWS - 1, %cleanwin ! prevent needless clean_window |
85 | ! traps for kernel |
98 | ! traps for kernel |
86 | 99 | ||
- | 100 | wrpr %g0, 0, %wstate ! use default spill/fill trap |
|
- | 101 | ||
87 | wrpr %g0, 0, %tl ! TL = 0, primary context |
102 | wrpr %g0, 0, %tl ! TL = 0, primary context |
88 | ! register is used |
103 | ! register is used |
89 | 104 | ||
90 | wrpr %g0, PSTATE_PRIV_BIT, %pstate ! disable interrupts and disable |
105 | wrpr %g0, PSTATE_PRIV_BIT, %pstate ! disable interrupts and disable |
91 | ! 32-bit address masking |
106 | ! 32-bit address masking |
92 | 107 | ||
93 | wrpr %g0, 0, %pil ! intialize %pil |
108 | wrpr %g0, 0, %pil ! intialize %pil |
94 | 109 | ||
95 | /* |
110 | /* |
96 | * Switch to kernel trap table. |
111 | * Switch to kernel trap table. |
97 | */ |
112 | */ |
98 | sethi %hi(trap_table), %g1 |
113 | sethi %hi(trap_table), %g1 |
99 | wrpr %g1, %lo(trap_table), %tba |
114 | wrpr %g1, %lo(trap_table), %tba |
100 | 115 | ||
101 | /* |
116 | /* |
102 | * Take over the DMMU by installing locked TTE entry identically |
117 | * Take over the DMMU by installing locked TTE entry identically |
103 | * mapping the first 4M of memory. |
118 | * mapping the first 4M of memory. |
104 | * |
119 | * |
105 | * In case of DMMU, no FLUSH instructions need to be issued. Because of |
120 | * In case of DMMU, no FLUSH instructions need to be issued. Because of |
106 | * that, the old DTLB contents can be demapped pretty straightforwardly |
121 | * that, the old DTLB contents can be demapped pretty straightforwardly |
107 | * and without causing any traps. |
122 | * and without causing any traps. |
108 | */ |
123 | */ |
109 | 124 | ||
110 | wr %g0, ASI_DMMU, %asi |
125 | wr %g0, ASI_DMMU, %asi |
111 | 126 | ||
112 | #define SET_TLB_DEMAP_CMD(r1, context_id) \ |
127 | #define SET_TLB_DEMAP_CMD(r1, context_id) \ |
113 | set (TLB_DEMAP_CONTEXT << TLB_DEMAP_TYPE_SHIFT) | (context_id << \ |
128 | set (TLB_DEMAP_CONTEXT << TLB_DEMAP_TYPE_SHIFT) | (context_id << \ |
114 | TLB_DEMAP_CONTEXT_SHIFT), %r1 |
129 | TLB_DEMAP_CONTEXT_SHIFT), %r1 |
115 | 130 | ||
116 | ! demap context 0 |
131 | ! demap context 0 |
117 | SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS) |
132 | SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS) |
118 | stxa %g0, [%g1] ASI_DMMU_DEMAP |
133 | stxa %g0, [%g1] ASI_DMMU_DEMAP |
119 | membar #Sync |
134 | membar #Sync |
120 | 135 | ||
121 | #define SET_TLB_TAG(r1, context) \ |
136 | #define SET_TLB_TAG(r1, context) \ |
122 | set VMA | (context << TLB_TAG_ACCESS_CONTEXT_SHIFT), %r1 |
137 | set VMA | (context << TLB_TAG_ACCESS_CONTEXT_SHIFT), %r1 |
123 | 138 | ||
124 | ! write DTLB tag |
139 | ! write DTLB tag |
125 | SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL) |
140 | SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL) |
126 | stxa %g1, [VA_DMMU_TAG_ACCESS] %asi |
141 | stxa %g1, [VA_DMMU_TAG_ACCESS] %asi |
127 | membar #Sync |
142 | membar #Sync |
128 | 143 | ||
129 | #ifdef CONFIG_VIRT_IDX_DCACHE |
144 | #ifdef CONFIG_VIRT_IDX_DCACHE |
130 | #define TTE_LOW_DATA(imm) (TTE_CP | TTE_CV | TTE_P | LMA | (imm)) |
145 | #define TTE_LOW_DATA(imm) (TTE_CP | TTE_CV | TTE_P | LMA | (imm)) |
131 | #else /* CONFIG_VIRT_IDX_DCACHE */ |
146 | #else /* CONFIG_VIRT_IDX_DCACHE */ |
132 | #define TTE_LOW_DATA(imm) (TTE_CP | TTE_P | LMA | (imm)) |
147 | #define TTE_LOW_DATA(imm) (TTE_CP | TTE_P | LMA | (imm)) |
133 | #endif /* CONFIG_VIRT_IDX_DCACHE */ |
148 | #endif /* CONFIG_VIRT_IDX_DCACHE */ |
134 | 149 | ||
135 | #define SET_TLB_DATA(r1, r2, imm) \ |
150 | #define SET_TLB_DATA(r1, r2, imm) \ |
136 | set TTE_LOW_DATA(imm), %r1; \ |
151 | set TTE_LOW_DATA(imm), %r1; \ |
137 | or %r1, %l5, %r1; \ |
152 | or %r1, %l5, %r1; \ |
138 | mov PAGESIZE_4M, %r2; \ |
153 | mov PAGESIZE_4M, %r2; \ |
139 | sllx %r2, TTE_SIZE_SHIFT, %r2; \ |
154 | sllx %r2, TTE_SIZE_SHIFT, %r2; \ |
140 | or %r1, %r2, %r1; \ |
155 | or %r1, %r2, %r1; \ |
141 | mov 1, %r2; \ |
156 | mov 1, %r2; \ |
142 | sllx %r2, TTE_V_SHIFT, %r2; \ |
157 | sllx %r2, TTE_V_SHIFT, %r2; \ |
143 | or %r1, %r2, %r1; |
158 | or %r1, %r2, %r1; |
144 | 159 | ||
145 | ! write DTLB data and install the kernel mapping |
160 | ! write DTLB data and install the kernel mapping |
146 | SET_TLB_DATA(g1, g2, TTE_L | TTE_W) ! use non-global mapping |
161 | SET_TLB_DATA(g1, g2, TTE_L | TTE_W) ! use non-global mapping |
147 | stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG |
162 | stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG |
148 | membar #Sync |
163 | membar #Sync |
149 | 164 | ||
150 | /* |
165 | /* |
151 | * Because we cannot use global mappings (because we want to have |
166 | * Because we cannot use global mappings (because we want to have |
152 | * separate 64-bit address spaces for both the kernel and the |
167 | * separate 64-bit address spaces for both the kernel and the |
153 | * userspace), we prepare the identity mapping also in context 1. This |
168 | * userspace), we prepare the identity mapping also in context 1. This |
154 | * step is required by the code installing the ITLB mapping. |
169 | * step is required by the code installing the ITLB mapping. |
155 | */ |
170 | */ |
156 | ! write DTLB tag of context 1 (i.e. MEM_CONTEXT_TEMP) |
171 | ! write DTLB tag of context 1 (i.e. MEM_CONTEXT_TEMP) |
157 | SET_TLB_TAG(g1, MEM_CONTEXT_TEMP) |
172 | SET_TLB_TAG(g1, MEM_CONTEXT_TEMP) |
158 | stxa %g1, [VA_DMMU_TAG_ACCESS] %asi |
173 | stxa %g1, [VA_DMMU_TAG_ACCESS] %asi |
159 | membar #Sync |
174 | membar #Sync |
160 | 175 | ||
161 | ! write DTLB data and install the kernel mapping in context 1 |
176 | ! write DTLB data and install the kernel mapping in context 1 |
162 | SET_TLB_DATA(g1, g2, TTE_W) ! use non-global mapping |
177 | SET_TLB_DATA(g1, g2, TTE_W) ! use non-global mapping |
163 | stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG |
178 | stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG |
164 | membar #Sync |
179 | membar #Sync |
165 | 180 | ||
166 | /* |
181 | /* |
167 | * Now is time to take over the IMMU. Unfortunatelly, it cannot be done |
182 | * Now is time to take over the IMMU. Unfortunatelly, it cannot be done |
168 | * as easily as the DMMU, because the IMMU is mapping the code it |
183 | * as easily as the DMMU, because the IMMU is mapping the code it |
169 | * executes. |
184 | * executes. |
170 | * |
185 | * |
171 | * [ Note that brave experiments with disabling the IMMU and using the |
186 | * [ Note that brave experiments with disabling the IMMU and using the |
172 | * DMMU approach failed after a dozen of desparate days with only little |
187 | * DMMU approach failed after a dozen of desparate days with only little |
173 | * success. ] |
188 | * success. ] |
174 | * |
189 | * |
175 | * The approach used here is inspired from OpenBSD. First, the kernel |
190 | * The approach used here is inspired from OpenBSD. First, the kernel |
176 | * creates IMMU mapping for itself in context 1 (MEM_CONTEXT_TEMP) and |
191 | * creates IMMU mapping for itself in context 1 (MEM_CONTEXT_TEMP) and |
177 | * switches to it. Context 0 (MEM_CONTEXT_KERNEL) can be demapped |
192 | * switches to it. Context 0 (MEM_CONTEXT_KERNEL) can be demapped |
178 | * afterwards and replaced with the kernel permanent mapping. Finally, |
193 | * afterwards and replaced with the kernel permanent mapping. Finally, |
179 | * the kernel switches back to context 0 and demaps context 1. |
194 | * the kernel switches back to context 0 and demaps context 1. |
180 | * |
195 | * |
181 | * Moreover, the IMMU requires use of the FLUSH instructions. But that |
196 | * Moreover, the IMMU requires use of the FLUSH instructions. But that |
182 | * is OK because we always use operands with addresses already mapped by |
197 | * is OK because we always use operands with addresses already mapped by |
183 | * the taken over DTLB. |
198 | * the taken over DTLB. |
184 | */ |
199 | */ |
185 | 200 | ||
186 | set kernel_image_start, %g5 |
201 | set kernel_image_start, %g5 |
187 | 202 | ||
188 | ! write ITLB tag of context 1 |
203 | ! write ITLB tag of context 1 |
189 | SET_TLB_TAG(g1, MEM_CONTEXT_TEMP) |
204 | SET_TLB_TAG(g1, MEM_CONTEXT_TEMP) |
190 | mov VA_DMMU_TAG_ACCESS, %g2 |
205 | mov VA_DMMU_TAG_ACCESS, %g2 |
191 | stxa %g1, [%g2] ASI_IMMU |
206 | stxa %g1, [%g2] ASI_IMMU |
192 | flush %g5 |
207 | flush %g5 |
193 | 208 | ||
194 | ! write ITLB data and install the temporary mapping in context 1 |
209 | ! write ITLB data and install the temporary mapping in context 1 |
195 | SET_TLB_DATA(g1, g2, 0) ! use non-global mapping |
210 | SET_TLB_DATA(g1, g2, 0) ! use non-global mapping |
196 | stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG |
211 | stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG |
197 | flush %g5 |
212 | flush %g5 |
198 | 213 | ||
199 | ! switch to context 1 |
214 | ! switch to context 1 |
200 | mov MEM_CONTEXT_TEMP, %g1 |
215 | mov MEM_CONTEXT_TEMP, %g1 |
201 | stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!! |
216 | stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!! |
202 | flush %g5 |
217 | flush %g5 |
203 | 218 | ||
204 | ! demap context 0 |
219 | ! demap context 0 |
205 | SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS) |
220 | SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS) |
206 | stxa %g0, [%g1] ASI_IMMU_DEMAP |
221 | stxa %g0, [%g1] ASI_IMMU_DEMAP |
207 | flush %g5 |
222 | flush %g5 |
208 | 223 | ||
209 | ! write ITLB tag of context 0 |
224 | ! write ITLB tag of context 0 |
210 | SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL) |
225 | SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL) |
211 | mov VA_DMMU_TAG_ACCESS, %g2 |
226 | mov VA_DMMU_TAG_ACCESS, %g2 |
212 | stxa %g1, [%g2] ASI_IMMU |
227 | stxa %g1, [%g2] ASI_IMMU |
213 | flush %g5 |
228 | flush %g5 |
214 | 229 | ||
215 | ! write ITLB data and install the permanent kernel mapping in context 0 |
230 | ! write ITLB data and install the permanent kernel mapping in context 0 |
216 | SET_TLB_DATA(g1, g2, TTE_L) ! use non-global mapping |
231 | SET_TLB_DATA(g1, g2, TTE_L) ! use non-global mapping |
217 | stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG |
232 | stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG |
218 | flush %g5 |
233 | flush %g5 |
219 | 234 | ||
220 | ! enter nucleus - using context 0 |
235 | ! enter nucleus - using context 0 |
221 | wrpr %g0, 1, %tl |
236 | wrpr %g0, 1, %tl |
222 | 237 | ||
223 | ! demap context 1 |
238 | ! demap context 1 |
224 | SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_PRIMARY) |
239 | SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_PRIMARY) |
225 | stxa %g0, [%g1] ASI_IMMU_DEMAP |
240 | stxa %g0, [%g1] ASI_IMMU_DEMAP |
226 | flush %g5 |
241 | flush %g5 |
227 | 242 | ||
228 | ! set context 0 in the primary context register |
243 | ! set context 0 in the primary context register |
229 | stxa %g0, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!! |
244 | stxa %g0, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!! |
230 | flush %g5 |
245 | flush %g5 |
231 | 246 | ||
232 | ! leave nucleus - using primary context, i.e. context 0 |
247 | ! leave nucleus - using primary context, i.e. context 0 |
233 | wrpr %g0, 0, %tl |
248 | wrpr %g0, 0, %tl |
234 | 249 | ||
235 | brz %l7, 1f ! skip if you are not the bootstrap CPU |
250 | brz %l7, 1f ! skip if you are not the bootstrap CPU |
236 | nop |
251 | nop |
237 | 252 | ||
238 | /* |
253 | /* |
239 | * Save physmem_base for use by the mm subsystem. |
254 | * Save physmem_base for use by the mm subsystem. |
240 | * %l6 contains starting physical address |
255 | * %l6 contains starting physical address |
241 | */ |
256 | */ |
242 | sethi %hi(physmem_base), %l4 |
257 | sethi %hi(physmem_base), %l4 |
243 | stx %l6, [%l4 + %lo(physmem_base)] |
258 | stx %l6, [%l4 + %lo(physmem_base)] |
244 | 259 | ||
245 | /* |
260 | /* |
246 | * Precompute kernel 8K TLB data template. |
261 | * Precompute kernel 8K TLB data template. |
247 | * %l5 contains starting physical address bits [40:13] |
262 | * %l5 contains starting physical address |
- | 263 | * bits [(PHYSMEM_ADDR_SIZE - 1):13] |
|
248 | */ |
264 | */ |
249 | sethi %hi(kernel_8k_tlb_data_template), %l4 |
265 | sethi %hi(kernel_8k_tlb_data_template), %l4 |
250 | ldx [%l4 + %lo(kernel_8k_tlb_data_template)], %l3 |
266 | ldx [%l4 + %lo(kernel_8k_tlb_data_template)], %l3 |
251 | or %l3, %l5, %l3 |
267 | or %l3, %l5, %l3 |
252 | stx %l3, [%l4 + %lo(kernel_8k_tlb_data_template)] |
268 | stx %l3, [%l4 + %lo(kernel_8k_tlb_data_template)] |
253 | 269 | ||
254 | /* |
270 | /* |
255 | * Flush D-Cache. |
271 | * Flush D-Cache. |
256 | */ |
272 | */ |
257 | call dcache_flush |
273 | call dcache_flush |
258 | nop |
274 | nop |
259 | 275 | ||
260 | /* |
276 | /* |
261 | * So far, we have not touched the stack. |
277 | * So far, we have not touched the stack. |
262 | * It is a good idea to set the kernel stack to a known state now. |
278 | * It is a good idea to set the kernel stack to a known state now. |
263 | */ |
279 | */ |
264 | sethi %hi(temporary_boot_stack), %sp |
280 | sethi %hi(temporary_boot_stack), %sp |
265 | or %sp, %lo(temporary_boot_stack), %sp |
281 | or %sp, %lo(temporary_boot_stack), %sp |
266 | sub %sp, STACK_BIAS, %sp |
282 | sub %sp, STACK_BIAS, %sp |
267 | 283 | ||
268 | sethi %hi(bootinfo), %o0 |
284 | sethi %hi(bootinfo), %o0 |
269 | call memcpy ! copy bootinfo |
285 | call memcpy ! copy bootinfo |
270 | or %o0, %lo(bootinfo), %o0 |
286 | or %o0, %lo(bootinfo), %o0 |
271 | 287 | ||
272 | call arch_pre_main |
288 | call arch_pre_main |
273 | nop |
289 | nop |
274 | 290 | ||
275 | call main_bsp |
291 | call main_bsp |
276 | nop |
292 | nop |
277 | 293 | ||
278 | /* Not reached. */ |
294 | /* Not reached. */ |
279 | 295 | ||
280 | 0: |
296 | 0: |
281 | ba 0b |
297 | ba 0b |
282 | nop |
298 | nop |
283 | 299 | ||
284 | 300 | ||
- | 301 | 1: |
|
- | 302 | #ifdef CONFIG_SMP |
|
- | 303 | /* |
|
- | 304 | * Determine the width of the MID and save its mask to %g3. The width |
|
- | 305 | * is |
|
- | 306 | * * 5 for US and US-IIIi, |
|
- | 307 | * * 10 for US3 except US-IIIi. |
|
- | 308 | */ |
|
- | 309 | #if defined(US) |
|
- | 310 | mov 0x1f, %g3 |
|
- | 311 | #elif defined(US3) |
|
- | 312 | mov 0x3ff, %g3 |
|
- | 313 | rdpr %ver, %g2 |
|
- | 314 | sllx %g2, 16, %g2 |
|
- | 315 | srlx %g2, 48, %g2 |
|
- | 316 | cmp %g2, IMPL_ULTRASPARCIII_I |
|
- | 317 | move %xcc, 0x1f, %g3 |
|
- | 318 | #endif |
|
- | 319 | ||
285 | /* |
320 | /* |
286 | * Read MID from the processor. |
321 | * Read MID from the processor. |
287 | */ |
322 | */ |
288 | 1: |
- | |
289 | ldxa [%g0] ASI_UPA_CONFIG, %g1 |
323 | ldxa [%g0] ASI_ICBUS_CONFIG, %g1 |
290 | srlx %g1, UPA_CONFIG_MID_SHIFT, %g1 |
324 | srlx %g1, ICBUS_CONFIG_MID_SHIFT, %g1 |
291 | and %g1, UPA_CONFIG_MID_MASK, %g1 |
325 | and %g1, %g3, %g1 |
292 | 326 | ||
293 | #ifdef CONFIG_SMP |
- | |
294 | /* |
327 | /* |
295 | * Active loop for APs until the BSP picks them up. A processor cannot |
328 | * Active loop for APs until the BSP picks them up. A processor cannot |
296 | * leave the loop until the global variable 'waking_up_mid' equals its |
329 | * leave the loop until the global variable 'waking_up_mid' equals its |
297 | * MID. |
330 | * MID. |
298 | */ |
331 | */ |
299 | set waking_up_mid, %g2 |
332 | set waking_up_mid, %g2 |
300 | 2: |
333 | 2: |
301 | ldx [%g2], %g3 |
334 | ldx [%g2], %g3 |
302 | cmp %g3, %g1 |
335 | cmp %g3, %g1 |
303 | bne 2b |
336 | bne 2b |
304 | nop |
337 | nop |
305 | 338 | ||
306 | /* |
339 | /* |
307 | * Configure stack for the AP. |
340 | * Configure stack for the AP. |
308 | * The AP is expected to use the stack saved |
341 | * The AP is expected to use the stack saved |
309 | * in the ctx global variable. |
342 | * in the ctx global variable. |
310 | */ |
343 | */ |
311 | set ctx, %g1 |
344 | set ctx, %g1 |
312 | add %g1, OFFSET_SP, %g1 |
345 | add %g1, OFFSET_SP, %g1 |
313 | ldx [%g1], %o6 |
346 | ldx [%g1], %o6 |
314 | 347 | ||
315 | call main_ap |
348 | call main_ap |
316 | nop |
349 | nop |
317 | 350 | ||
318 | /* Not reached. */ |
351 | /* Not reached. */ |
319 | #endif |
352 | #endif |
320 | 353 | ||
321 | 0: |
354 | 0: |
322 | ba 0b |
355 | ba 0b |
323 | nop |
356 | nop |
324 | 357 | ||
325 | 358 | ||
326 | .section K_DATA_START, "aw", @progbits |
359 | .section K_DATA_START, "aw", @progbits |
327 | 360 | ||
328 | /* |
361 | /* |
329 | * Create small stack to be used by the bootstrap processor. It is going to be |
362 | * Create small stack to be used by the bootstrap processor. It is going to be |
330 | * used only for a very limited period of time, but we switch to it anyway, |
363 | * used only for a very limited period of time, but we switch to it anyway, |
331 | * just to be sure we are properly initialized. |
364 | * just to be sure we are properly initialized. |
332 | */ |
365 | */ |
333 | 366 | ||
334 | #define INITIAL_STACK_SIZE 1024 |
367 | #define INITIAL_STACK_SIZE 1024 |
335 | 368 | ||
336 | .align STACK_ALIGNMENT |
369 | .align STACK_ALIGNMENT |
337 | .space INITIAL_STACK_SIZE |
370 | .space INITIAL_STACK_SIZE |
338 | .align STACK_ALIGNMENT |
371 | .align STACK_ALIGNMENT |
339 | temporary_boot_stack: |
372 | temporary_boot_stack: |
340 | .space STACK_WINDOW_SAVE_AREA_SIZE |
373 | .space STACK_WINDOW_SAVE_AREA_SIZE |
341 | 374 | ||
342 | 375 | ||
343 | .data |
376 | .data |
344 | 377 | ||
345 | .align 8 |
378 | .align 8 |
346 | .global physmem_base ! copy of the physical memory base address |
379 | .global physmem_base ! copy of the physical memory base address |
347 | physmem_base: |
380 | physmem_base: |
348 | .quad 0 |
381 | .quad 0 |
349 | 382 | ||
350 | /* |
383 | /* |
351 | * This variable is used by the fast_data_MMU_miss trap handler. In runtime, it |
384 | * This variable is used by the fast_data_MMU_miss trap handler. In runtime, it |
352 | * is further modified to reflect the starting address of physical memory. |
385 | * is further modified to reflect the starting address of physical memory. |
353 | */ |
386 | */ |
354 | .global kernel_8k_tlb_data_template |
387 | .global kernel_8k_tlb_data_template |
355 | kernel_8k_tlb_data_template: |
388 | kernel_8k_tlb_data_template: |
356 | #ifdef CONFIG_VIRT_IDX_DCACHE |
389 | #ifdef CONFIG_VIRT_IDX_DCACHE |
357 | .quad ((1 << TTE_V_SHIFT) | (PAGESIZE_8K << TTE_SIZE_SHIFT) | TTE_CP | \ |
390 | .quad ((1 << TTE_V_SHIFT) | (PAGESIZE_8K << TTE_SIZE_SHIFT) | TTE_CP | \ |
358 | TTE_CV | TTE_P | TTE_W) |
391 | TTE_CV | TTE_P | TTE_W) |
359 | #else /* CONFIG_VIRT_IDX_DCACHE */ |
392 | #else /* CONFIG_VIRT_IDX_DCACHE */ |
360 | .quad ((1 << TTE_V_SHIFT) | (PAGESIZE_8K << TTE_SIZE_SHIFT) | TTE_CP | \ |
393 | .quad ((1 << TTE_V_SHIFT) | (PAGESIZE_8K << TTE_SIZE_SHIFT) | TTE_CP | \ |
361 | TTE_P | TTE_W) |
394 | TTE_P | TTE_W) |
362 | #endif /* CONFIG_VIRT_IDX_DCACHE */ |
395 | #endif /* CONFIG_VIRT_IDX_DCACHE */ |
363 | 396 | ||
364 | 397 |