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1 | /* |
1 | /* |
2 | * Copyright (C) 2003-2004 Jakub Jermar |
2 | * Copyright (C) 2003-2004 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | 29 | ||
30 | #include <arch.h> |
30 | #include <arch.h> |
31 | #include <arch/cp0.h> |
31 | #include <arch/cp0.h> |
32 | #include <arch/exception.h> |
32 | #include <arch/exception.h> |
33 | #include <arch/asm.h> |
33 | #include <arch/asm.h> |
34 | #include <mm/as.h> |
34 | #include <mm/as.h> |
35 | 35 | ||
36 | #include <userspace.h> |
36 | #include <userspace.h> |
37 | #include <arch/console.h> |
37 | #include <arch/console.h> |
38 | #include <memstr.h> |
38 | #include <memstr.h> |
39 | #include <proc/thread.h> |
39 | #include <proc/thread.h> |
40 | #include <proc/uarg.h> |
40 | #include <proc/uarg.h> |
41 | #include <print.h> |
41 | #include <print.h> |
42 | #include <syscall/syscall.h> |
42 | #include <syscall/syscall.h> |
43 | 43 | ||
44 | #include <arch/interrupt.h> |
44 | #include <arch/interrupt.h> |
45 | #include <arch/drivers/arc.h> |
45 | #include <arch/drivers/arc.h> |
46 | #include <console/chardev.h> |
46 | #include <console/chardev.h> |
47 | #include <arch/debugger.h> |
47 | #include <arch/debugger.h> |
- | 48 | #include <genarch/fb/fb.h> |
|
48 | 49 | ||
49 | #include <arch/asm/regname.h> |
50 | #include <arch/asm/regname.h> |
50 | 51 | ||
51 | /* Size of the code jumping to the exception handler code |
52 | /* Size of the code jumping to the exception handler code |
52 | * - J+NOP |
53 | * - J+NOP |
53 | */ |
54 | */ |
54 | #define EXCEPTION_JUMP_SIZE 8 |
55 | #define EXCEPTION_JUMP_SIZE 8 |
55 | 56 | ||
56 | #define TLB_EXC ((char *) 0x80000000) |
57 | #define TLB_EXC ((char *) 0x80000000) |
57 | #define NORM_EXC ((char *) 0x80000180) |
58 | #define NORM_EXC ((char *) 0x80000180) |
58 | #define CACHE_EXC ((char *) 0x80000100) |
59 | #define CACHE_EXC ((char *) 0x80000100) |
59 | 60 | ||
60 | void arch_pre_main(void) |
61 | void arch_pre_main(void) |
61 | { |
62 | { |
62 | /* Setup usermode */ |
63 | /* Setup usermode */ |
63 | init.cnt = 3; |
64 | init.cnt = 3; |
64 | init.tasks[0].addr = INIT_ADDRESS; |
65 | init.tasks[0].addr = INIT_ADDRESS; |
65 | init.tasks[0].size = INIT_SIZE; |
66 | init.tasks[0].size = INIT_SIZE; |
66 | init.tasks[1].addr = INIT_ADDRESS + 0x100000; |
67 | init.tasks[1].addr = INIT_ADDRESS + 0x100000; |
67 | init.tasks[1].size = INIT_SIZE; |
68 | init.tasks[1].size = INIT_SIZE; |
68 | init.tasks[2].addr = INIT_ADDRESS + 0x200000; |
69 | init.tasks[2].addr = INIT_ADDRESS + 0x200000; |
69 | init.tasks[2].size = INIT_SIZE; |
70 | init.tasks[2].size = INIT_SIZE; |
70 | } |
71 | } |
71 | 72 | ||
72 | void arch_pre_mm_init(void) |
73 | void arch_pre_mm_init(void) |
73 | { |
74 | { |
74 | /* It is not assumed by default */ |
75 | /* It is not assumed by default */ |
75 | interrupts_disable(); |
76 | interrupts_disable(); |
76 | 77 | ||
77 | /* Initialize dispatch table */ |
78 | /* Initialize dispatch table */ |
78 | exception_init(); |
79 | exception_init(); |
79 | interrupt_init(); |
80 | interrupt_init(); |
80 | 81 | ||
81 | arc_init(); |
82 | arc_init(); |
82 | 83 | ||
83 | /* Copy the exception vectors to the right places */ |
84 | /* Copy the exception vectors to the right places */ |
84 | memcpy(TLB_EXC, (char *)tlb_refill_entry, EXCEPTION_JUMP_SIZE); |
85 | memcpy(TLB_EXC, (char *)tlb_refill_entry, EXCEPTION_JUMP_SIZE); |
85 | memcpy(NORM_EXC, (char *)exception_entry, EXCEPTION_JUMP_SIZE); |
86 | memcpy(NORM_EXC, (char *)exception_entry, EXCEPTION_JUMP_SIZE); |
86 | memcpy(CACHE_EXC, (char *)cache_error_entry, EXCEPTION_JUMP_SIZE); |
87 | memcpy(CACHE_EXC, (char *)cache_error_entry, EXCEPTION_JUMP_SIZE); |
87 | 88 | ||
88 | /* |
89 | /* |
89 | * Switch to BEV normal level so that exception vectors point to the kernel. |
90 | * Switch to BEV normal level so that exception vectors point to the kernel. |
90 | * Clear the error level. |
91 | * Clear the error level. |
91 | */ |
92 | */ |
92 | cp0_status_write(cp0_status_read() & ~(cp0_status_bev_bootstrap_bit|cp0_status_erl_error_bit)); |
93 | cp0_status_write(cp0_status_read() & ~(cp0_status_bev_bootstrap_bit|cp0_status_erl_error_bit)); |
93 | 94 | ||
94 | /* |
95 | /* |
95 | * Mask all interrupts |
96 | * Mask all interrupts |
96 | */ |
97 | */ |
97 | cp0_mask_all_int(); |
98 | cp0_mask_all_int(); |
98 | /* |
99 | /* |
99 | * Unmask hardware clock interrupt. |
100 | * Unmask hardware clock interrupt. |
100 | */ |
101 | */ |
101 | cp0_unmask_int(TIMER_IRQ); |
102 | cp0_unmask_int(TIMER_IRQ); |
102 | 103 | ||
103 | /* |
104 | /* |
104 | * Start hardware clock. |
105 | * Start hardware clock. |
105 | */ |
106 | */ |
106 | cp0_compare_write(cp0_compare_value + cp0_count_read()); |
107 | cp0_compare_write(cp0_compare_value + cp0_count_read()); |
107 | 108 | ||
108 | console_init(); |
109 | console_init(); |
109 | debugger_init(); |
110 | debugger_init(); |
110 | } |
111 | } |
111 | 112 | ||
112 | void arch_post_mm_init(void) |
113 | void arch_post_mm_init(void) |
113 | { |
114 | { |
- | 115 | #ifdef CONFIG_FB |
|
- | 116 | fb_init(0x12000000, 640, 480, 24, 1920); // gxemul framebuffer |
|
- | 117 | #endif |
|
114 | } |
118 | } |
115 | 119 | ||
116 | void arch_pre_smp_init(void) |
120 | void arch_pre_smp_init(void) |
117 | { |
121 | { |
118 | } |
122 | } |
119 | 123 | ||
120 | void arch_post_smp_init(void) |
124 | void arch_post_smp_init(void) |
121 | { |
125 | { |
122 | } |
126 | } |
123 | 127 | ||
124 | /* Stack pointer saved when entering user mode */ |
128 | /* Stack pointer saved when entering user mode */ |
125 | /* TODO: How do we do it on SMP system???? */ |
129 | /* TODO: How do we do it on SMP system???? */ |
126 | 130 | ||
127 | /* Why the linker moves the variable 64K away in assembler |
131 | /* Why the linker moves the variable 64K away in assembler |
128 | * when not in .text section ???????? |
132 | * when not in .text section ???????? |
129 | */ |
133 | */ |
130 | __address supervisor_sp __attribute__ ((section (".text"))); |
134 | __address supervisor_sp __attribute__ ((section (".text"))); |
131 | 135 | ||
132 | void userspace(uspace_arg_t *kernel_uarg) |
136 | void userspace(uspace_arg_t *kernel_uarg) |
133 | { |
137 | { |
134 | /* EXL=1, UM=1, IE=1 */ |
138 | /* EXL=1, UM=1, IE=1 */ |
135 | cp0_status_write(cp0_status_read() | (cp0_status_exl_exception_bit | |
139 | cp0_status_write(cp0_status_read() | (cp0_status_exl_exception_bit | |
136 | cp0_status_um_bit | |
140 | cp0_status_um_bit | |
137 | cp0_status_ie_enabled_bit)); |
141 | cp0_status_ie_enabled_bit)); |
138 | cp0_epc_write((__address) kernel_uarg->uspace_entry); |
142 | cp0_epc_write((__address) kernel_uarg->uspace_entry); |
139 | userspace_asm(((__address) kernel_uarg->uspace_stack+PAGE_SIZE), |
143 | userspace_asm(((__address) kernel_uarg->uspace_stack+PAGE_SIZE), |
140 | (__address) kernel_uarg->uspace_uarg, |
144 | (__address) kernel_uarg->uspace_uarg, |
141 | (__address) kernel_uarg->uspace_entry); |
145 | (__address) kernel_uarg->uspace_entry); |
142 | while (1) |
146 | while (1) |
143 | ; |
147 | ; |
144 | } |
148 | } |
145 | 149 | ||
146 | /** Perform mips32 specific tasks needed before the new task is run. */ |
150 | /** Perform mips32 specific tasks needed before the new task is run. */ |
147 | void before_task_runs_arch(void) |
151 | void before_task_runs_arch(void) |
148 | { |
152 | { |
149 | } |
153 | } |
150 | 154 | ||
151 | /** Perform mips32 specific tasks needed before the new thread is scheduled. */ |
155 | /** Perform mips32 specific tasks needed before the new thread is scheduled. */ |
152 | void before_thread_runs_arch(void) |
156 | void before_thread_runs_arch(void) |
153 | { |
157 | { |
154 | supervisor_sp = (__address) &THREAD->kstack[THREAD_STACK_SIZE-SP_DELTA]; |
158 | supervisor_sp = (__address) &THREAD->kstack[THREAD_STACK_SIZE-SP_DELTA]; |
155 | } |
159 | } |
156 | 160 | ||
157 | void after_thread_ran_arch(void) |
161 | void after_thread_ran_arch(void) |
158 | { |
162 | { |
159 | } |
163 | } |
160 | 164 | ||
161 | /** Set thread-local-storage pointer |
165 | /** Set thread-local-storage pointer |
162 | * |
166 | * |
163 | * We have it currently in K1, it is |
167 | * We have it currently in K1, it is |
164 | * possible to have it separately in the future. |
168 | * possible to have it separately in the future. |
165 | */ |
169 | */ |
166 | __native sys_tls_set(__native addr) |
170 | __native sys_tls_set(__native addr) |
167 | { |
171 | { |
168 | return 0; |
172 | return 0; |
169 | } |
173 | } |
170 | 174 |