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1 | # |
1 | # |
2 | # Copyright (C) 2005 Jakub Jermar |
2 | # Copyright (C) 2005 Jakub Jermar |
3 | # All rights reserved. |
3 | # All rights reserved. |
4 | # |
4 | # |
5 | # Redistribution and use in source and binary forms, with or without |
5 | # Redistribution and use in source and binary forms, with or without |
6 | # modification, are permitted provided that the following conditions |
6 | # modification, are permitted provided that the following conditions |
7 | # are met: |
7 | # are met: |
8 | # |
8 | # |
9 | # - Redistributions of source code must retain the above copyright |
9 | # - Redistributions of source code must retain the above copyright |
10 | # notice, this list of conditions and the following disclaimer. |
10 | # notice, this list of conditions and the following disclaimer. |
11 | # - Redistributions in binary form must reproduce the above copyright |
11 | # - Redistributions in binary form must reproduce the above copyright |
12 | # notice, this list of conditions and the following disclaimer in the |
12 | # notice, this list of conditions and the following disclaimer in the |
13 | # documentation and/or other materials provided with the distribution. |
13 | # documentation and/or other materials provided with the distribution. |
14 | # - The name of the author may not be used to endorse or promote products |
14 | # - The name of the author may not be used to endorse or promote products |
15 | # derived from this software without specific prior written permission. |
15 | # derived from this software without specific prior written permission. |
16 | # |
16 | # |
17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | # |
27 | # |
28 | 28 | ||
29 | 29 | ||
30 | #include <arch/register.h> |
30 | #include <arch/register.h> |
31 | #include <arch/mm/page.h> |
31 | #include <arch/mm/page.h> |
32 | #include <arch/mm/asid.h> |
32 | #include <arch/mm/asid.h> |
33 | #include <mm/asid.h> |
33 | #include <mm/asid.h> |
34 | 34 | ||
35 | 35 | ||
36 | #define RR_MASK (0xFFFFFFFF00000002) |
36 | #define RR_MASK (0xFFFFFFFF00000002) |
37 | #define RID_SHIFT 8 |
37 | #define RID_SHIFT 8 |
38 | #define PS_SHIFT 2 |
38 | #define PS_SHIFT 2 |
39 | 39 | ||
40 | 40 | ||
41 | #define KERNEL_TRANSLATION_I 0x0010000000000661 |
41 | #define KERNEL_TRANSLATION_I 0x0010000000000661 |
42 | #define KERNEL_TRANSLATION_D 0x0010000000000661 |
42 | #define KERNEL_TRANSLATION_D 0x0010000000000661 |
43 | 43 | ||
44 | 44 | ||
45 | .section K_TEXT_START |
45 | .section K_TEXT_START |
46 | 46 | ||
47 | .global kernel_image_start |
47 | .global kernel_image_start |
48 | 48 | ||
49 | stack0: |
49 | stack0: |
50 | kernel_image_start: |
50 | kernel_image_start: |
51 | .auto |
51 | .auto |
52 | 52 | ||
53 | #Fill TR.i and TR.d and enable paging |
53 | #Fill TR.i and TR.d and enable paging |
54 | 54 | ||
55 | mov r9=rr[r0] |
55 | mov r9=rr[r0] |
56 | movl r10=(RR_MASK) |
56 | movl r10=(RR_MASK) |
57 | and r9=r10,r9 |
57 | and r9=r10,r9 |
58 | movl r10=((ASID2RID(ASID_KERNEL,VRN_KERNEL)<<RID_SHIFT)|(KERNEL_PAGE_WIDTH<<PS_SHIFT)) |
58 | movl r10=((ASID2RID(ASID_KERNEL,VRN_KERNEL)<<RID_SHIFT)|(KERNEL_PAGE_WIDTH<<PS_SHIFT)) |
59 | or r9=r10,r9 |
59 | or r9=r10,r9 |
60 | mov rr[r0]=r9 |
60 | mov rr[r0]=r9 |
61 | 61 | ||
62 | 62 | ||
63 | 63 | ||
64 | movl r8=(VRN_KERNEL<<VRN_SHIFT) |
64 | movl r8=(VRN_KERNEL<<VRN_SHIFT) |
65 | mov r9=rr[r8] |
65 | mov r9=rr[r8] |
66 | movl r10=(RR_MASK) |
66 | movl r10=(RR_MASK) |
67 | and r9=r10,r9 |
67 | and r9=r10,r9 |
68 | movl r10=((ASID2RID(ASID_KERNEL,VRN_KERNEL)<<RID_SHIFT)|(KERNEL_PAGE_WIDTH<<PS_SHIFT)) |
68 | movl r10=((ASID2RID(ASID_KERNEL,VRN_KERNEL)<<RID_SHIFT)|(KERNEL_PAGE_WIDTH<<PS_SHIFT)) |
69 | or r9=r10,r9 |
69 | or r9=r10,r9 |
70 | mov rr[r8]=r9 |
70 | mov rr[r8]=r9 |
71 | 71 | ||
72 | 72 | ||
73 | movl r8=(VRN_KERNEL<<VRN_SHIFT) |
73 | movl r8=(VRN_KERNEL<<VRN_SHIFT) |
74 | mov cr.ifa=r8 |
74 | mov cr.ifa=r8 |
75 | movl r10=(KERNEL_PAGE_WIDTH<<PS_SHIFT) |
75 | movl r10=(KERNEL_PAGE_WIDTH<<PS_SHIFT) |
76 | mov cr.itir=r10 |
76 | mov cr.itir=r10 |
77 | movl r10=(KERNEL_TRANSLATION_I) |
77 | movl r10=(KERNEL_TRANSLATION_I) |
78 | itr.i itr[r0]=r10 |
78 | itr.i itr[r0]=r10 |
79 | 79 | ||
80 | # mov cr.ifa=r0 |
80 | # mov cr.ifa=r0 |
81 | # movl r10=(KERNEL_PAGE_WIDTH<<PS_SHIFT) |
81 | # movl r10=(KERNEL_PAGE_WIDTH<<PS_SHIFT) |
82 | # mov cr.itir=r10 |
82 | # mov cr.itir=r10 |
83 | movl r10=(KERNEL_TRANSLATION_D) |
83 | movl r10=(KERNEL_TRANSLATION_D) |
84 | itr.d dtr[r0]=r10 |
84 | itr.d dtr[r0]=r10 |
85 | 85 | ||
86 | 86 | ||
87 | 87 | ||
88 | 88 | ||
89 | 89 | ||
90 | 90 | ||
91 | 91 | ||
92 | # initialize PSR |
92 | # initialize PSR |
93 | mov psr.l = r0 |
93 | mov psr.l = r0 |
94 | srlz.i |
94 | srlz.i |
95 | srlz.d |
95 | srlz.d |
96 | movl r10=(PSR_DT_MASK|PSR_RT_MASK|PSR_IT_MASK|PSR_IC_MASK) /*Enable paging*/ |
96 | movl r10=(PSR_DT_MASK|PSR_RT_MASK|PSR_IT_MASK|PSR_IC_MASK) /*Enable paging*/ |
97 | mov r9=psr |
97 | mov r9=psr |
98 | or r10=r10,r9 |
98 | or r10=r10,r9 |
99 | mov cr.ipsr=r10 |
99 | mov cr.ipsr=r10 |
100 | mov cr.ifs=r0 |
100 | mov cr.ifs=r0 |
101 | # movl r8=(paging_start+VRN_KERNEL<<VRN_SHIFT) |
101 | # movl r8=(paging_start+VRN_KERNEL<<VRN_SHIFT) |
102 | movl r8=paging_start |
102 | movl r8=paging_start |
103 | mov cr.iip=r8 |
103 | mov cr.iip=r8 |
104 | srlz.d |
104 | srlz.d |
105 | srlz.i |
105 | srlz.i |
106 | .explicit |
106 | .explicit |
107 | {rfi;;} |
107 | {rfi;;} |
108 | {nop 0;;} |
108 | {nop 0;;} |
109 | {nop 0;;} |
109 | {nop 0;;} |
110 | {nop 0;;} |
110 | {nop 0;;} |
111 | {nop 0;;} |
111 | {nop 0;;} |
112 | {nop 0;;} |
112 | {nop 0;;} |
113 | {nop 0;;} |
113 | {nop 0;;} |
114 | {nop 0;;} |
114 | {nop 0;;} |
115 | {nop 0;;} |
115 | {nop 0;;} |
116 | {nop 0;;} |
116 | {nop 0;;} |
117 | {nop 0;;} |
117 | {nop 0;;} |
118 | {nop 0;;} |
118 | {nop 0;;} |
119 | {nop 0;;} |
119 | {nop 0;;} |
120 | {nop 0;;} |
120 | {nop 0;;} |
121 | {nop 0;;} |
121 | {nop 0;;} |
122 | {nop 0;;} |
122 | {nop 0;;} |
123 | {nop 0;;} |
123 | {nop 0;;} |
124 | 124 | ||
125 | .global paging_start |
125 | .global paging_start |
126 | paging_start: |
126 | paging_start: |
127 | 127 | ||
128 | .auto |
128 | .auto |
129 | 129 | ||
130 | # switch to register bank 1 |
130 | # switch to register bank 1 |
131 | bsw.1 |
131 | bsw.1 |
132 | 132 | ||
133 | # initialize register stack |
133 | # initialize register stack |
134 | mov ar.rsc = r0 |
134 | mov ar.rsc = r0 |
135 | movl r8=(VRN_KERNEL<<VRN_SHIFT) |
135 | movl r8=(VRN_KERNEL<<VRN_SHIFT) |
136 | mov ar.bspstore = r8 |
136 | mov ar.bspstore = r8 |
137 | # mov ar.bspstore = r0 |
137 | # mov ar.bspstore = r0 |
138 | loadrs |
138 | loadrs |
139 | 139 | ||
140 | .explicit |
140 | .explicit |
141 | # initialize memory stack to some sane value |
141 | # initialize memory stack to some sane value |
142 | # movl r12 = stack0 ;; |
142 | # movl r12 = stack0 ;; |
143 | movl r12 = stack0 + (VRN_KERNEL<<VRN_SHIFT);; |
143 | movl r12 = stack0 + (VRN_KERNEL<<VRN_SHIFT);; |
144 | 144 | ||
145 | add r12 = - 16, r12 /* allocate a scratch area on the stack */ |
145 | add r12 = - 16, r12 /* allocate a scratch area on the stack */ |
146 | 146 | ||
147 | # initialize gp (Global Pointer) register |
147 | # initialize gp (Global Pointer) register |
148 | movl r1 = _hardcoded_load_address ;; |
148 | movl r1 = _hardcoded_load_address ;; |
149 | 149 | ||
150 | # movl r1 = _hardcoded_load_address + (VRN_KERNEL<<VRN_SHIFT) ;; |
150 | # movl r1 = _hardcoded_load_address + (VRN_KERNEL<<VRN_SHIFT) ;; |
151 | 151 | ||
152 | 152 | ||
153 | # |
153 | # |
154 | # Initialize hardcoded_* variables. |
154 | # Initialize hardcoded_* variables. |
155 | # |
155 | # |
156 | movl r14 = _hardcoded_ktext_size |
156 | movl r14 = _hardcoded_ktext_size |
157 | movl r15 = _hardcoded_kdata_size |
157 | movl r15 = _hardcoded_kdata_size |
158 | movl r16 = _hardcoded_load_address |
158 | movl r16 = _hardcoded_load_address |
159 | addl r17 = @gprel(hardcoded_ktext_size), gp |
159 | addl r17 = @gprel(hardcoded_ktext_size), gp |
160 | addl r18 = @gprel(hardcoded_kdata_size), gp |
160 | addl r18 = @gprel(hardcoded_kdata_size), gp |
161 | addl r19 = @gprel(hardcoded_load_address), gp |
161 | addl r19 = @gprel(hardcoded_load_address), gp |
162 | ;; |
162 | ;; |
163 | st4 [r17] = r14 |
163 | st8 [r17] = r14 |
164 | st4 [r18] = r15 |
164 | st8 [r18] = r15 |
165 | st8 [r19] = r16 |
165 | st8 [r19] = r16 |
166 | 166 | ||
167 | 167 | ||
168 | .auto |
168 | .auto |
169 | 169 | ||
170 | movl r18=main_bsp |
170 | movl r18=main_bsp |
171 | mov b1=r18 |
171 | mov b1=r18 |
172 | br.call.sptk.many b0=b1 |
172 | br.call.sptk.many b0=b1 |
173 | 173 | ||
174 | # br.call.sptk.many b0=main_bsp |
174 | # br.call.sptk.many b0=main_bsp |
175 | 175 | ||
176 | 0: |
176 | 0: |
177 | br 0b |
177 | br 0b |
178 | 178 |