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1 | /* |
1 | /* |
2 | * Copyright (c) 2005 Ondrej Palkovsky |
2 | * Copyright (c) 2005 Ondrej Palkovsky |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup amd64mm |
29 | /** @addtogroup amd64mm |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | */ |
33 | */ |
34 | 34 | ||
35 | /** Paging on AMD64 |
35 | /** Paging on AMD64 |
36 | * |
36 | * |
37 | * The space is divided in positive numbers - userspace and |
37 | * The space is divided in positive numbers - userspace and |
38 | * negative numbers - kernel space. The 'negative' space starting |
38 | * negative numbers - kernel space. The 'negative' space starting |
39 | * with 0xffff800000000000 and ending with 0xffffffff80000000 |
39 | * with 0xffff800000000000 and ending with 0xffffffff80000000 |
40 | * (-2GB) is identically mapped physical memory. The area |
40 | * (-2GB) is identically mapped physical memory. The area |
41 | * (0xffffffff80000000 ... 0xffffffffffffffff is again identically |
41 | * (0xffffffff80000000 ... 0xffffffffffffffff is again identically |
42 | * mapped first 2GB. |
42 | * mapped first 2GB. |
43 | * |
43 | * |
44 | * ATTENTION - PA2KA(KA2PA(x)) != x if 'x' is in kernel |
44 | * ATTENTION - PA2KA(KA2PA(x)) != x if 'x' is in kernel |
45 | */ |
45 | */ |
46 | 46 | ||
47 | #ifndef KERN_amd64_PAGE_H_ |
47 | #ifndef KERN_amd64_PAGE_H_ |
48 | #define KERN_amd64_PAGE_H_ |
48 | #define KERN_amd64_PAGE_H_ |
49 | 49 | ||
50 | #include <arch/mm/frame.h> |
50 | #include <arch/mm/frame.h> |
51 | 51 | ||
52 | #define PAGE_WIDTH FRAME_WIDTH |
52 | #define PAGE_WIDTH FRAME_WIDTH |
53 | #define PAGE_SIZE FRAME_SIZE |
53 | #define PAGE_SIZE FRAME_SIZE |
54 | 54 | ||
55 | #ifdef KERNEL |
55 | #ifdef KERNEL |
56 | 56 | ||
57 | #ifndef __ASM__ |
57 | #ifndef __ASM__ |
58 | # include <mm/mm.h> |
58 | # include <mm/mm.h> |
59 | # include <arch/types.h> |
59 | # include <arch/types.h> |
60 | # include <arch/interrupt.h> |
60 | # include <arch/interrupt.h> |
61 | 61 | ||
62 | static inline uintptr_t ka2pa(uintptr_t x) |
62 | static inline uintptr_t ka2pa(uintptr_t x) |
63 | { |
63 | { |
64 | if (x > 0xffffffff80000000) |
64 | if (x > 0xffffffff80000000) |
65 | return x - 0xffffffff80000000; |
65 | return x - 0xffffffff80000000; |
66 | else |
66 | else |
67 | return x - 0xffff800000000000; |
67 | return x - 0xffff800000000000; |
68 | } |
68 | } |
69 | 69 | ||
70 | # define KA2PA(x) ka2pa((uintptr_t) x) |
70 | # define KA2PA(x) ka2pa((uintptr_t) x) |
71 | # define PA2KA_CODE(x) (((uintptr_t) (x)) + 0xffffffff80000000) |
71 | # define PA2KA_CODE(x) (((uintptr_t) (x)) + 0xffffffff80000000) |
72 | # define PA2KA(x) (((uintptr_t) (x)) + 0xffff800000000000) |
72 | # define PA2KA(x) (((uintptr_t) (x)) + 0xffff800000000000) |
73 | #else |
73 | #else |
74 | # define KA2PA(x) ((x) - 0xffffffff80000000) |
74 | # define KA2PA(x) ((x) - 0xffffffff80000000) |
75 | # define PA2KA(x) ((x) + 0xffffffff80000000) |
75 | # define PA2KA(x) ((x) + 0xffffffff80000000) |
76 | #endif |
76 | #endif |
77 | 77 | ||
78 | /* Number of entries in each level. */ |
78 | /* Number of entries in each level. */ |
79 | #define PTL0_ENTRIES_ARCH 512 |
79 | #define PTL0_ENTRIES_ARCH 512 |
80 | #define PTL1_ENTRIES_ARCH 512 |
80 | #define PTL1_ENTRIES_ARCH 512 |
81 | #define PTL2_ENTRIES_ARCH 512 |
81 | #define PTL2_ENTRIES_ARCH 512 |
82 | #define PTL3_ENTRIES_ARCH 512 |
82 | #define PTL3_ENTRIES_ARCH 512 |
83 | 83 | ||
84 | /* Page table sizes for each level. */ |
84 | /* Page table sizes for each level. */ |
85 | #define PTL0_SIZE_ARCH ONE_FRAME |
85 | #define PTL0_SIZE_ARCH ONE_FRAME |
86 | #define PTL1_SIZE_ARCH ONE_FRAME |
86 | #define PTL1_SIZE_ARCH ONE_FRAME |
87 | #define PTL2_SIZE_ARCH ONE_FRAME |
87 | #define PTL2_SIZE_ARCH ONE_FRAME |
88 | #define PTL3_SIZE_ARCH ONE_FRAME |
88 | #define PTL3_SIZE_ARCH ONE_FRAME |
89 | 89 | ||
90 | /* Macros calculating indices into page tables in each level. */ |
90 | /* Macros calculating indices into page tables in each level. */ |
91 | #define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 39) & 0x1ff) |
91 | #define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 39) & 0x1ff) |
92 | #define PTL1_INDEX_ARCH(vaddr) (((vaddr) >> 30) & 0x1ff) |
92 | #define PTL1_INDEX_ARCH(vaddr) (((vaddr) >> 30) & 0x1ff) |
93 | #define PTL2_INDEX_ARCH(vaddr) (((vaddr) >> 21) & 0x1ff) |
93 | #define PTL2_INDEX_ARCH(vaddr) (((vaddr) >> 21) & 0x1ff) |
94 | #define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x1ff) |
94 | #define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x1ff) |
95 | 95 | ||
96 | /* Get PTE address accessors for each level. */ |
96 | /* Get PTE address accessors for each level. */ |
97 | #define GET_PTL1_ADDRESS_ARCH(ptl0, i) \ |
97 | #define GET_PTL1_ADDRESS_ARCH(ptl0, i) \ |
98 | ((pte_t *) ((((uint64_t) ((pte_t *) (ptl0))[(i)].addr_12_31) << 12) | \ |
98 | ((pte_t *) ((((uint64_t) ((pte_t *) (ptl0))[(i)].addr_12_31) << 12) | \ |
99 | (((uint64_t) ((pte_t *) (ptl0))[(i)].addr_32_51) << 32))) |
99 | (((uint64_t) ((pte_t *) (ptl0))[(i)].addr_32_51) << 32))) |
100 | #define GET_PTL2_ADDRESS_ARCH(ptl1, i) \ |
100 | #define GET_PTL2_ADDRESS_ARCH(ptl1, i) \ |
101 | ((pte_t *) ((((uint64_t) ((pte_t *) (ptl1))[(i)].addr_12_31) << 12) | \ |
101 | ((pte_t *) ((((uint64_t) ((pte_t *) (ptl1))[(i)].addr_12_31) << 12) | \ |
102 | (((uint64_t) ((pte_t *) (ptl1))[(i)].addr_32_51) << 32))) |
102 | (((uint64_t) ((pte_t *) (ptl1))[(i)].addr_32_51) << 32))) |
103 | #define GET_PTL3_ADDRESS_ARCH(ptl2, i) \ |
103 | #define GET_PTL3_ADDRESS_ARCH(ptl2, i) \ |
104 | ((pte_t *) ((((uint64_t) ((pte_t *) (ptl2))[(i)].addr_12_31) << 12) | \ |
104 | ((pte_t *) ((((uint64_t) ((pte_t *) (ptl2))[(i)].addr_12_31) << 12) | \ |
105 | (((uint64_t) ((pte_t *) (ptl2))[(i)].addr_32_51) << 32))) |
105 | (((uint64_t) ((pte_t *) (ptl2))[(i)].addr_32_51) << 32))) |
106 | #define GET_FRAME_ADDRESS_ARCH(ptl3, i) \ |
106 | #define GET_FRAME_ADDRESS_ARCH(ptl3, i) \ |
107 | ((uintptr_t *) \ |
107 | ((uintptr_t *) \ |
108 | ((((uint64_t) ((pte_t *) (ptl3))[(i)].addr_12_31) << 12) | \ |
108 | ((((uint64_t) ((pte_t *) (ptl3))[(i)].addr_12_31) << 12) | \ |
109 | (((uint64_t) ((pte_t *) (ptl3))[(i)].addr_32_51) << 32))) |
109 | (((uint64_t) ((pte_t *) (ptl3))[(i)].addr_32_51) << 32))) |
110 | 110 | ||
111 | /* Set PTE address accessors for each level. */ |
111 | /* Set PTE address accessors for each level. */ |
112 | #define SET_PTL0_ADDRESS_ARCH(ptl0) \ |
112 | #define SET_PTL0_ADDRESS_ARCH(ptl0) \ |
113 | (write_cr3((uintptr_t) (ptl0))) |
113 | (write_cr3((uintptr_t) (ptl0))) |
114 | #define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \ |
114 | #define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \ |
115 | set_pt_addr((pte_t *) (ptl0), (index_t) (i), a) |
115 | set_pt_addr((pte_t *) (ptl0), (size_t) (i), a) |
116 | #define SET_PTL2_ADDRESS_ARCH(ptl1, i, a) \ |
116 | #define SET_PTL2_ADDRESS_ARCH(ptl1, i, a) \ |
117 | set_pt_addr((pte_t *) (ptl1), (index_t) (i), a) |
117 | set_pt_addr((pte_t *) (ptl1), (size_t) (i), a) |
118 | #define SET_PTL3_ADDRESS_ARCH(ptl2, i, a) \ |
118 | #define SET_PTL3_ADDRESS_ARCH(ptl2, i, a) \ |
119 | set_pt_addr((pte_t *) (ptl2), (index_t) (i), a) |
119 | set_pt_addr((pte_t *) (ptl2), (size_t) (i), a) |
120 | #define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \ |
120 | #define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \ |
121 | set_pt_addr((pte_t *) (ptl3), (index_t) (i), a) |
121 | set_pt_addr((pte_t *) (ptl3), (size_t) (i), a) |
122 | 122 | ||
123 | /* Get PTE flags accessors for each level. */ |
123 | /* Get PTE flags accessors for each level. */ |
124 | #define GET_PTL1_FLAGS_ARCH(ptl0, i) \ |
124 | #define GET_PTL1_FLAGS_ARCH(ptl0, i) \ |
125 | get_pt_flags((pte_t *) (ptl0), (index_t) (i)) |
125 | get_pt_flags((pte_t *) (ptl0), (size_t) (i)) |
126 | #define GET_PTL2_FLAGS_ARCH(ptl1, i) \ |
126 | #define GET_PTL2_FLAGS_ARCH(ptl1, i) \ |
127 | get_pt_flags((pte_t *) (ptl1), (index_t) (i)) |
127 | get_pt_flags((pte_t *) (ptl1), (size_t) (i)) |
128 | #define GET_PTL3_FLAGS_ARCH(ptl2, i) \ |
128 | #define GET_PTL3_FLAGS_ARCH(ptl2, i) \ |
129 | get_pt_flags((pte_t *) (ptl2), (index_t) (i)) |
129 | get_pt_flags((pte_t *) (ptl2), (size_t) (i)) |
130 | #define GET_FRAME_FLAGS_ARCH(ptl3, i) \ |
130 | #define GET_FRAME_FLAGS_ARCH(ptl3, i) \ |
131 | get_pt_flags((pte_t *) (ptl3), (index_t) (i)) |
131 | get_pt_flags((pte_t *) (ptl3), (size_t) (i)) |
132 | 132 | ||
133 | /* Set PTE flags accessors for each level. */ |
133 | /* Set PTE flags accessors for each level. */ |
134 | #define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \ |
134 | #define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \ |
135 | set_pt_flags((pte_t *) (ptl0), (index_t) (i), (x)) |
135 | set_pt_flags((pte_t *) (ptl0), (size_t) (i), (x)) |
136 | #define SET_PTL2_FLAGS_ARCH(ptl1, i, x) \ |
136 | #define SET_PTL2_FLAGS_ARCH(ptl1, i, x) \ |
137 | set_pt_flags((pte_t *) (ptl1), (index_t) (i), (x)) |
137 | set_pt_flags((pte_t *) (ptl1), (size_t) (i), (x)) |
138 | #define SET_PTL3_FLAGS_ARCH(ptl2, i, x) \ |
138 | #define SET_PTL3_FLAGS_ARCH(ptl2, i, x) \ |
139 | set_pt_flags((pte_t *) (ptl2), (index_t) (i), (x)) |
139 | set_pt_flags((pte_t *) (ptl2), (size_t) (i), (x)) |
140 | #define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \ |
140 | #define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \ |
141 | set_pt_flags((pte_t *) (ptl3), (index_t) (i), (x)) |
141 | set_pt_flags((pte_t *) (ptl3), (size_t) (i), (x)) |
142 | 142 | ||
143 | /* Macros for querying the last-level PTE entries. */ |
143 | /* Macros for querying the last-level PTE entries. */ |
144 | #define PTE_VALID_ARCH(p) \ |
144 | #define PTE_VALID_ARCH(p) \ |
145 | (*((uint64_t *) (p)) != 0) |
145 | (*((uint64_t *) (p)) != 0) |
146 | #define PTE_PRESENT_ARCH(p) \ |
146 | #define PTE_PRESENT_ARCH(p) \ |
147 | ((p)->present != 0) |
147 | ((p)->present != 0) |
148 | #define PTE_GET_FRAME_ARCH(p) \ |
148 | #define PTE_GET_FRAME_ARCH(p) \ |
149 | ((((uintptr_t) (p)->addr_12_31) << 12) | \ |
149 | ((((uintptr_t) (p)->addr_12_31) << 12) | \ |
150 | ((uintptr_t) (p)->addr_32_51 << 32)) |
150 | ((uintptr_t) (p)->addr_32_51 << 32)) |
151 | #define PTE_WRITABLE_ARCH(p) \ |
151 | #define PTE_WRITABLE_ARCH(p) \ |
152 | ((p)->writeable != 0) |
152 | ((p)->writeable != 0) |
153 | #define PTE_EXECUTABLE_ARCH(p) \ |
153 | #define PTE_EXECUTABLE_ARCH(p) \ |
154 | ((p)->no_execute == 0) |
154 | ((p)->no_execute == 0) |
155 | 155 | ||
156 | #ifndef __ASM__ |
156 | #ifndef __ASM__ |
157 | 157 | ||
158 | /* Page fault error codes. */ |
158 | /* Page fault error codes. */ |
159 | 159 | ||
160 | /** When bit on this position is 0, the page fault was caused by a not-present |
160 | /** When bit on this position is 0, the page fault was caused by a not-present |
161 | * page. |
161 | * page. |
162 | */ |
162 | */ |
163 | #define PFERR_CODE_P (1 << 0) |
163 | #define PFERR_CODE_P (1 << 0) |
164 | 164 | ||
165 | /** When bit on this position is 1, the page fault was caused by a write. */ |
165 | /** When bit on this position is 1, the page fault was caused by a write. */ |
166 | #define PFERR_CODE_RW (1 << 1) |
166 | #define PFERR_CODE_RW (1 << 1) |
167 | 167 | ||
168 | /** When bit on this position is 1, the page fault was caused in user mode. */ |
168 | /** When bit on this position is 1, the page fault was caused in user mode. */ |
169 | #define PFERR_CODE_US (1 << 2) |
169 | #define PFERR_CODE_US (1 << 2) |
170 | 170 | ||
171 | /** When bit on this position is 1, a reserved bit was set in page directory. */ |
171 | /** When bit on this position is 1, a reserved bit was set in page directory. */ |
172 | #define PFERR_CODE_RSVD (1 << 3) |
172 | #define PFERR_CODE_RSVD (1 << 3) |
173 | 173 | ||
174 | /** When bit on this position os 1, the page fault was caused during instruction |
174 | /** When bit on this position os 1, the page fault was caused during instruction |
175 | * fecth. |
175 | * fecth. |
176 | */ |
176 | */ |
177 | #define PFERR_CODE_ID (1 << 4) |
177 | #define PFERR_CODE_ID (1 << 4) |
178 | 178 | ||
179 | static inline int get_pt_flags(pte_t *pt, index_t i) |
179 | static inline int get_pt_flags(pte_t *pt, size_t i) |
180 | { |
180 | { |
181 | pte_t *p = &pt[i]; |
181 | pte_t *p = &pt[i]; |
182 | 182 | ||
183 | return ((!p->page_cache_disable) << PAGE_CACHEABLE_SHIFT | |
183 | return ((!p->page_cache_disable) << PAGE_CACHEABLE_SHIFT | |
184 | (!p->present) << PAGE_PRESENT_SHIFT | |
184 | (!p->present) << PAGE_PRESENT_SHIFT | |
185 | p->uaccessible << PAGE_USER_SHIFT | |
185 | p->uaccessible << PAGE_USER_SHIFT | |
186 | 1 << PAGE_READ_SHIFT | |
186 | 1 << PAGE_READ_SHIFT | |
187 | p->writeable << PAGE_WRITE_SHIFT | |
187 | p->writeable << PAGE_WRITE_SHIFT | |
188 | (!p->no_execute) << PAGE_EXEC_SHIFT | |
188 | (!p->no_execute) << PAGE_EXEC_SHIFT | |
189 | p->global << PAGE_GLOBAL_SHIFT); |
189 | p->global << PAGE_GLOBAL_SHIFT); |
190 | } |
190 | } |
191 | 191 | ||
192 | static inline void set_pt_addr(pte_t *pt, index_t i, uintptr_t a) |
192 | static inline void set_pt_addr(pte_t *pt, size_t i, uintptr_t a) |
193 | { |
193 | { |
194 | pte_t *p = &pt[i]; |
194 | pte_t *p = &pt[i]; |
195 | 195 | ||
196 | p->addr_12_31 = (a >> 12) & 0xfffff; |
196 | p->addr_12_31 = (a >> 12) & 0xfffff; |
197 | p->addr_32_51 = a >> 32; |
197 | p->addr_32_51 = a >> 32; |
198 | } |
198 | } |
199 | 199 | ||
200 | static inline void set_pt_flags(pte_t *pt, index_t i, int flags) |
200 | static inline void set_pt_flags(pte_t *pt, size_t i, int flags) |
201 | { |
201 | { |
202 | pte_t *p = &pt[i]; |
202 | pte_t *p = &pt[i]; |
203 | 203 | ||
204 | p->page_cache_disable = !(flags & PAGE_CACHEABLE); |
204 | p->page_cache_disable = !(flags & PAGE_CACHEABLE); |
205 | p->present = !(flags & PAGE_NOT_PRESENT); |
205 | p->present = !(flags & PAGE_NOT_PRESENT); |
206 | p->uaccessible = (flags & PAGE_USER) != 0; |
206 | p->uaccessible = (flags & PAGE_USER) != 0; |
207 | p->writeable = (flags & PAGE_WRITE) != 0; |
207 | p->writeable = (flags & PAGE_WRITE) != 0; |
208 | p->no_execute = (flags & PAGE_EXEC) == 0; |
208 | p->no_execute = (flags & PAGE_EXEC) == 0; |
209 | p->global = (flags & PAGE_GLOBAL) != 0; |
209 | p->global = (flags & PAGE_GLOBAL) != 0; |
210 | 210 | ||
211 | /* |
211 | /* |
212 | * Ensure that there is at least one bit set even if the present bit is cleared. |
212 | * Ensure that there is at least one bit set even if the present bit is cleared. |
213 | */ |
213 | */ |
214 | p->soft_valid = 1; |
214 | p->soft_valid = 1; |
215 | } |
215 | } |
216 | 216 | ||
217 | extern void page_arch_init(void); |
217 | extern void page_arch_init(void); |
218 | extern void page_fault(int n, istate_t *istate); |
218 | extern void page_fault(int n, istate_t *istate); |
219 | 219 | ||
220 | #endif /* __ASM__ */ |
220 | #endif /* __ASM__ */ |
221 | 221 | ||
222 | #endif /* KERNEL */ |
222 | #endif /* KERNEL */ |
223 | 223 | ||
224 | #endif |
224 | #endif |
225 | 225 | ||
226 | /** @} |
226 | /** @} |
227 | */ |
227 | */ |
228 | 228 |