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1 | /* |
1 | /* |
2 | * Copyright (c) 2006 Jakub Jermar |
2 | * Copyright (c) 2006 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup genericddi |
29 | /** @addtogroup genericddi |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** |
32 | /** |
33 | * @file |
33 | * @file |
34 | * @brief IRQ dispatcher. |
34 | * @brief IRQ dispatcher. |
35 | * |
35 | * |
36 | * This file provides means of connecting IRQs with particular |
36 | * This file provides means of connecting IRQs with particular |
37 | * devices and logic for dispatching interrupts to IRQ handlers |
37 | * devices and logic for dispatching interrupts to IRQ handlers |
38 | * defined by those devices. |
38 | * defined by those devices. |
39 | * |
39 | * |
40 | * This code is designed to support: |
40 | * This code is designed to support: |
41 | * - multiple devices sharing single IRQ |
41 | * - multiple devices sharing single IRQ |
42 | * - multiple IRQs per single device |
42 | * - multiple IRQs per single device |
43 | * - multiple instances of the same device |
43 | * - multiple instances of the same device |
44 | * |
44 | * |
45 | * |
45 | * |
46 | * Note about architectures. |
46 | * Note about architectures. |
47 | * |
47 | * |
48 | * Some architectures has the term IRQ well defined. Examples |
48 | * Some architectures has the term IRQ well defined. Examples |
49 | * of such architectures include amd64, ia32 and mips32. Some |
49 | * of such architectures include amd64, ia32 and mips32. Some |
50 | * other architectures, such as sparc64, don't use the term |
50 | * other architectures, such as sparc64, don't use the term |
51 | * at all. In those cases, we boldly step forward and define what |
51 | * at all. In those cases, we boldly step forward and define what |
52 | * an IRQ is. |
52 | * an IRQ is. |
53 | * |
53 | * |
54 | * The implementation is generic enough and still allows the |
54 | * The implementation is generic enough and still allows the |
55 | * architectures to use the hardware layout effectively. |
55 | * architectures to use the hardware layout effectively. |
56 | * For instance, on amd64 and ia32, where there is only 16 |
56 | * For instance, on amd64 and ia32, where there is only 16 |
57 | * IRQs, the irq_hash_table can be optimized to a one-dimensional |
57 | * IRQs, the irq_hash_table can be optimized to a one-dimensional |
58 | * array. Next, when it is known that the IRQ numbers (aka INR's) |
58 | * array. Next, when it is known that the IRQ numbers (aka INR's) |
59 | * are unique, the claim functions can always return IRQ_ACCEPT. |
59 | * are unique, the claim functions can always return IRQ_ACCEPT. |
60 | * |
60 | * |
61 | * |
61 | * |
62 | * Note about the irq_hash_table. |
62 | * Note about the irq_hash_table. |
63 | * |
63 | * |
64 | * The hash table is configured to use two keys: inr and devno. |
64 | * The hash table is configured to use two keys: inr and devno. |
65 | * However, the hash index is computed only from inr. Moreover, |
65 | * However, the hash index is computed only from inr. Moreover, |
66 | * if devno is -1, the match is based on the return value of |
66 | * if devno is -1, the match is based on the return value of |
67 | * the claim() function instead of on devno. |
67 | * the claim() function instead of on devno. |
68 | */ |
68 | */ |
69 | 69 | ||
70 | #include <ddi/irq.h> |
70 | #include <ddi/irq.h> |
71 | #include <adt/hash_table.h> |
71 | #include <adt/hash_table.h> |
- | 72 | #include <mm/slab.h> |
|
72 | #include <arch/types.h> |
73 | #include <arch/types.h> |
73 | #include <synch/spinlock.h> |
74 | #include <synch/spinlock.h> |
- | 75 | #include <console/console.h> |
|
- | 76 | #include <memstr.h> |
|
74 | #include <arch.h> |
77 | #include <arch.h> |
75 | 78 | ||
76 | #define KEY_INR 0 |
79 | #define KEY_INR 0 |
77 | #define KEY_DEVNO 1 |
80 | #define KEY_DEVNO 1 |
78 | 81 | ||
79 | /** |
82 | /** |
80 | * Spinlock protecting the hash table. |
83 | * Spinlock protecting the kernel IRQ hash table. |
81 | * This lock must be taken only when interrupts are disabled. |
84 | * This lock must be taken only when interrupts are disabled. |
82 | */ |
85 | */ |
83 | SPINLOCK_INITIALIZE(irq_hash_table_lock); |
86 | SPINLOCK_INITIALIZE(irq_kernel_hash_table_lock); |
- | 87 | /** The kernel IRQ hash table. */ |
|
84 | static hash_table_t irq_hash_table; |
88 | static hash_table_t irq_kernel_hash_table; |
- | 89 | ||
- | 90 | /** |
|
- | 91 | * Spinlock protecting the uspace IRQ hash table. |
|
- | 92 | * This lock must be taken only when interrupts are disabled. |
|
- | 93 | */ |
|
- | 94 | SPINLOCK_INITIALIZE(irq_uspace_hash_table_lock); |
|
- | 95 | /** The uspace IRQ hash table. */ |
|
- | 96 | hash_table_t irq_uspace_hash_table; |
|
85 | 97 | ||
86 | /** |
98 | /** |
87 | * Hash table operations for cases when we know that |
99 | * Hash table operations for cases when we know that |
88 | * there will be collisions between different keys. |
100 | * there will be collisions between different keys. |
89 | */ |
101 | */ |
90 | static index_t irq_ht_hash(unative_t *key); |
102 | static index_t irq_ht_hash(unative_t *key); |
91 | static bool irq_ht_compare(unative_t *key, count_t keys, link_t *item); |
103 | static bool irq_ht_compare(unative_t *key, count_t keys, link_t *item); |
92 | 104 | ||
93 | static hash_table_operations_t irq_ht_ops = { |
105 | static hash_table_operations_t irq_ht_ops = { |
94 | .hash = irq_ht_hash, |
106 | .hash = irq_ht_hash, |
95 | .compare = irq_ht_compare, |
107 | .compare = irq_ht_compare, |
96 | .remove_callback = NULL /* not used */ |
108 | .remove_callback = NULL /* not used */ |
97 | }; |
109 | }; |
98 | 110 | ||
99 | /** |
111 | /** |
100 | * Hash table operations for cases when we know that |
112 | * Hash table operations for cases when we know that |
101 | * there will be no collisions between different keys. |
113 | * there will be no collisions between different keys. |
102 | * However, there might be still collisions among |
114 | * However, there might be still collisions among |
103 | * elements with single key (sharing of one IRQ). |
115 | * elements with single key (sharing of one IRQ). |
104 | */ |
116 | */ |
105 | static index_t irq_lin_hash(unative_t *key); |
117 | static index_t irq_lin_hash(unative_t *key); |
106 | static bool irq_lin_compare(unative_t *key, count_t keys, link_t *item); |
118 | static bool irq_lin_compare(unative_t *key, count_t keys, link_t *item); |
107 | 119 | ||
108 | static hash_table_operations_t irq_lin_ops = { |
120 | static hash_table_operations_t irq_lin_ops = { |
109 | .hash = irq_lin_hash, |
121 | .hash = irq_lin_hash, |
110 | .compare = irq_lin_compare, |
122 | .compare = irq_lin_compare, |
111 | .remove_callback = NULL /* not used */ |
123 | .remove_callback = NULL /* not used */ |
112 | }; |
124 | }; |
113 | 125 | ||
- | 126 | /** Number of buckets in either of the hash tables. */ |
|
- | 127 | static count_t buckets; |
|
- | 128 | ||
114 | /** Initialize IRQ subsystem. |
129 | /** Initialize IRQ subsystem. |
115 | * |
130 | * |
116 | * @param inrs Numbers of unique IRQ numbers or INRs. |
131 | * @param inrs Numbers of unique IRQ numbers or INRs. |
117 | * @param chains Number of chains in the hash table. |
132 | * @param chains Number of chains in the hash table. |
118 | */ |
133 | */ |
119 | void irq_init(count_t inrs, count_t chains) |
134 | void irq_init(count_t inrs, count_t chains) |
120 | { |
135 | { |
- | 136 | buckets = chains; |
|
121 | /* |
137 | /* |
122 | * Be smart about the choice of the hash table operations. |
138 | * Be smart about the choice of the hash table operations. |
123 | * In cases in which inrs equals the requested number of |
139 | * In cases in which inrs equals the requested number of |
124 | * chains (i.e. where there is no collision between |
140 | * chains (i.e. where there is no collision between |
125 | * different keys), we can use optimized set of operations. |
141 | * different keys), we can use optimized set of operations. |
126 | */ |
142 | */ |
127 | if (inrs == chains) |
143 | if (inrs == chains) { |
- | 144 | hash_table_create(&irq_uspace_hash_table, chains, 2, |
|
- | 145 | &irq_lin_ops); |
|
128 | hash_table_create(&irq_hash_table, chains, 2, &irq_lin_ops); |
146 | hash_table_create(&irq_kernel_hash_table, chains, 2, |
- | 147 | &irq_lin_ops); |
|
129 | else |
148 | } else { |
- | 149 | hash_table_create(&irq_uspace_hash_table, chains, 2, |
|
- | 150 | &irq_ht_ops); |
|
130 | hash_table_create(&irq_hash_table, chains, 2, &irq_ht_ops); |
151 | hash_table_create(&irq_kernel_hash_table, chains, 2, |
- | 152 | &irq_ht_ops); |
|
- | 153 | } |
|
131 | } |
154 | } |
132 | 155 | ||
133 | /** Initialize one IRQ structure. |
156 | /** Initialize one IRQ structure. |
134 | * |
157 | * |
135 | * @param irq Pointer to the IRQ structure to be initialized. |
158 | * @param irq Pointer to the IRQ structure to be initialized. |
136 | * |
159 | * |
137 | */ |
160 | */ |
138 | void irq_initialize(irq_t *irq) |
161 | void irq_initialize(irq_t *irq) |
139 | { |
162 | { |
- | 163 | memsetb(irq, sizeof(irq_t), 0); |
|
140 | link_initialize(&irq->link); |
164 | link_initialize(&irq->link); |
141 | spinlock_initialize(&irq->lock, "irq.lock"); |
165 | spinlock_initialize(&irq->lock, "irq.lock"); |
142 | irq->preack = false; |
166 | link_initialize(&irq->notif_cfg.link); |
143 | irq->inr = -1; |
167 | irq->inr = -1; |
144 | irq->devno = -1; |
168 | irq->devno = -1; |
145 | irq->trigger = (irq_trigger_t) 0; |
- | |
146 | irq->claim = NULL; |
- | |
147 | irq->handler = NULL; |
- | |
148 | irq->instance = NULL; |
- | |
149 | irq->cir = NULL; |
- | |
150 | irq->cir_arg = NULL; |
- | |
151 | irq->notif_cfg.notify = false; |
- | |
152 | irq->notif_cfg.answerbox = NULL; |
- | |
153 | irq->notif_cfg.code = NULL; |
- | |
154 | irq->notif_cfg.method = 0; |
- | |
155 | irq->notif_cfg.counter = 0; |
- | |
156 | link_initialize(&irq->notif_cfg.link); |
- | |
157 | } |
169 | } |
158 | 170 | ||
159 | /** Register IRQ for device. |
171 | /** Register IRQ for device. |
160 | * |
172 | * |
161 | * The irq structure must be filled with information |
173 | * The irq structure must be filled with information |
162 | * about the interrupt source and with the claim() |
174 | * about the interrupt source and with the claim() |
163 | * function pointer and irq_handler() function pointer. |
175 | * function pointer and handler() function pointer. |
164 | * |
176 | * |
165 | * @param irq IRQ structure belonging to a device. |
177 | * @param irq IRQ structure belonging to a device. |
- | 178 | * @return True on success, false on failure. |
|
166 | */ |
179 | */ |
167 | void irq_register(irq_t *irq) |
180 | void irq_register(irq_t *irq) |
168 | { |
181 | { |
169 | ipl_t ipl; |
182 | ipl_t ipl; |
170 | unative_t key[] = { |
183 | unative_t key[] = { |
171 | (unative_t) irq->inr, |
184 | (unative_t) irq->inr, |
172 | (unative_t) irq->devno |
185 | (unative_t) irq->devno |
173 | }; |
186 | }; |
174 | 187 | ||
175 | ipl = interrupts_disable(); |
188 | ipl = interrupts_disable(); |
176 | spinlock_lock(&irq_hash_table_lock); |
189 | spinlock_lock(&irq_kernel_hash_table_lock); |
- | 190 | spinlock_lock(&irq->lock); |
|
177 | hash_table_insert(&irq_hash_table, key, &irq->link); |
191 | hash_table_insert(&irq_kernel_hash_table, key, &irq->link); |
- | 192 | spinlock_unlock(&irq->lock); |
|
178 | spinlock_unlock(&irq_hash_table_lock); |
193 | spinlock_unlock(&irq_kernel_hash_table_lock); |
179 | interrupts_restore(ipl); |
194 | interrupts_restore(ipl); |
180 | } |
195 | } |
181 | 196 | ||
182 | /** Dispatch the IRQ. |
- | |
183 | * |
- | |
184 | * We assume this function is only called from interrupt |
- | |
185 | * context (i.e. that interrupts are disabled prior to |
197 | /** Search and lock the uspace IRQ hash table. |
186 | * this call). |
- | |
187 | * |
198 | * |
188 | * This function attempts to lookup a fitting IRQ |
- | |
189 | * structure. In case of success, return with interrupts |
- | |
190 | * disabled and holding the respective structure. |
- | |
191 | * |
- | |
192 | * @param inr Interrupt number (aka inr or irq). |
- | |
193 | * |
- | |
194 | * @return IRQ structure of the respective device or NULL. |
- | |
195 | */ |
199 | */ |
196 | irq_t *irq_dispatch_and_lock(inr_t inr) |
200 | static irq_t *irq_dispatch_and_lock_uspace(inr_t inr) |
197 | { |
201 | { |
198 | link_t *lnk; |
202 | link_t *lnk; |
199 | unative_t key[] = { |
203 | unative_t key[] = { |
200 | (unative_t) inr, |
204 | (unative_t) inr, |
201 | (unative_t) -1 /* search will use claim() instead of devno */ |
205 | (unative_t) -1 /* search will use claim() instead of devno */ |
202 | }; |
206 | }; |
203 | 207 | ||
204 | spinlock_lock(&irq_hash_table_lock); |
208 | spinlock_lock(&irq_uspace_hash_table_lock); |
205 | - | ||
206 | lnk = hash_table_find(&irq_hash_table, key); |
209 | lnk = hash_table_find(&irq_uspace_hash_table, key); |
207 | if (lnk) { |
210 | if (lnk) { |
208 | irq_t *irq; |
211 | irq_t *irq; |
209 | 212 | ||
210 | irq = hash_table_get_instance(lnk, irq_t, link); |
213 | irq = hash_table_get_instance(lnk, irq_t, link); |
211 | - | ||
212 | spinlock_unlock(&irq_hash_table_lock); |
214 | spinlock_unlock(&irq_uspace_hash_table_lock); |
213 | return irq; |
215 | return irq; |
214 | } |
216 | } |
215 | - | ||
216 | spinlock_unlock(&irq_hash_table_lock); |
217 | spinlock_unlock(&irq_uspace_hash_table_lock); |
217 | 218 | ||
218 | return NULL; |
219 | return NULL; |
219 | } |
220 | } |
220 | 221 | ||
221 | /** Find the IRQ structure corresponding to inr and devno. |
- | |
222 | * |
- | |
223 | * This functions attempts to lookup the IRQ structure |
- | |
224 | * corresponding to its arguments. On success, this |
- | |
225 | * function returns with interrups disabled, holding |
- | |
226 | * the lock of the respective IRQ structure. |
222 | /** Search and lock the kernel IRQ hash table. |
227 | * |
- | |
228 | * This function assumes interrupts are already disabled. |
- | |
229 | * |
- | |
230 | * @param inr INR being looked up. |
- | |
231 | * @param devno Devno being looked up. |
- | |
232 | * |
223 | * |
233 | * @return Locked IRQ structure on success or NULL on failure. |
- | |
234 | */ |
224 | */ |
235 | irq_t *irq_find_and_lock(inr_t inr, devno_t devno) |
225 | static irq_t *irq_dispatch_and_lock_kernel(inr_t inr) |
236 | { |
226 | { |
237 | link_t *lnk; |
227 | link_t *lnk; |
238 | unative_t keys[] = { |
228 | unative_t key[] = { |
239 | (unative_t) inr, |
229 | (unative_t) inr, |
240 | (unative_t) devno |
230 | (unative_t) -1 /* search will use claim() instead of devno */ |
241 | }; |
231 | }; |
242 | 232 | ||
243 | spinlock_lock(&irq_hash_table_lock); |
233 | spinlock_lock(&irq_kernel_hash_table_lock); |
244 | - | ||
245 | lnk = hash_table_find(&irq_hash_table, keys); |
234 | lnk = hash_table_find(&irq_kernel_hash_table, key); |
246 | if (lnk) { |
235 | if (lnk) { |
247 | irq_t *irq; |
236 | irq_t *irq; |
248 | 237 | ||
249 | irq = hash_table_get_instance(lnk, irq_t, link); |
238 | irq = hash_table_get_instance(lnk, irq_t, link); |
250 | - | ||
251 | spinlock_unlock(&irq_hash_table_lock); |
239 | spinlock_unlock(&irq_kernel_hash_table_lock); |
252 | return irq; |
240 | return irq; |
253 | } |
241 | } |
254 | - | ||
255 | spinlock_unlock(&irq_hash_table_lock); |
242 | spinlock_unlock(&irq_kernel_hash_table_lock); |
256 | 243 | ||
257 | return NULL; |
244 | return NULL; |
258 | } |
245 | } |
259 | 246 | ||
- | 247 | /** Dispatch the IRQ. |
|
- | 248 | * |
|
- | 249 | * We assume this function is only called from interrupt |
|
- | 250 | * context (i.e. that interrupts are disabled prior to |
|
- | 251 | * this call). |
|
- | 252 | * |
|
- | 253 | * This function attempts to lookup a fitting IRQ |
|
- | 254 | * structure. In case of success, return with interrupts |
|
- | 255 | * disabled and holding the respective structure. |
|
- | 256 | * |
|
- | 257 | * @param inr Interrupt number (aka inr or irq). |
|
- | 258 | * |
|
- | 259 | * @return IRQ structure of the respective device or NULL. |
|
- | 260 | */ |
|
- | 261 | irq_t *irq_dispatch_and_lock(inr_t inr) |
|
- | 262 | { |
|
- | 263 | irq_t *irq; |
|
- | 264 | ||
- | 265 | /* |
|
- | 266 | * If the kernel console is silenced, |
|
- | 267 | * then try first the uspace handlers, |
|
- | 268 | * eventually fall back to kernel handlers. |
|
- | 269 | * |
|
- | 270 | * If the kernel console is active, |
|
- | 271 | * then do it the other way around. |
|
- | 272 | */ |
|
- | 273 | if (silent) { |
|
- | 274 | irq = irq_dispatch_and_lock_uspace(inr); |
|
- | 275 | if (irq) |
|
- | 276 | return irq; |
|
- | 277 | return irq_dispatch_and_lock_kernel(inr); |
|
- | 278 | } |
|
- | 279 | ||
- | 280 | irq = irq_dispatch_and_lock_kernel(inr); |
|
- | 281 | if (irq) |
|
- | 282 | return irq; |
|
- | 283 | return irq_dispatch_and_lock_uspace(inr); |
|
- | 284 | } |
|
- | 285 | ||
260 | /** Compute hash index for the key. |
286 | /** Compute hash index for the key. |
261 | * |
287 | * |
262 | * This function computes hash index into |
288 | * This function computes hash index into |
263 | * the IRQ hash table for which there |
289 | * the IRQ hash table for which there |
264 | * can be collisions between different |
290 | * can be collisions between different |
265 | * INRs. |
291 | * INRs. |
266 | * |
292 | * |
267 | * The devno is not used to compute the hash. |
293 | * The devno is not used to compute the hash. |
268 | * |
294 | * |
269 | * @param key The first of the keys is inr and the second is devno or -1. |
295 | * @param key The first of the keys is inr and the second is devno or -1. |
270 | * |
296 | * |
271 | * @return Index into the hash table. |
297 | * @return Index into the hash table. |
272 | */ |
298 | */ |
273 | index_t irq_ht_hash(unative_t key[]) |
299 | index_t irq_ht_hash(unative_t key[]) |
274 | { |
300 | { |
275 | inr_t inr = (inr_t) key[KEY_INR]; |
301 | inr_t inr = (inr_t) key[KEY_INR]; |
276 | return inr % irq_hash_table.entries; |
302 | return inr % buckets; |
277 | } |
303 | } |
278 | 304 | ||
279 | /** Compare hash table element with a key. |
305 | /** Compare hash table element with a key. |
280 | * |
306 | * |
281 | * There are two things to note about this function. |
307 | * There are two things to note about this function. |
282 | * First, it is used for the more complex architecture setup |
308 | * First, it is used for the more complex architecture setup |
283 | * in which there are way too many interrupt numbers (i.e. inr's) |
309 | * in which there are way too many interrupt numbers (i.e. inr's) |
284 | * to arrange the hash table so that collisions occur only |
310 | * to arrange the hash table so that collisions occur only |
285 | * among same inrs of different devnos. So the explicit check |
311 | * among same inrs of different devnos. So the explicit check |
286 | * for inr match must be done. |
312 | * for inr match must be done. |
287 | * Second, if devno is -1, the second key (i.e. devno) is not |
313 | * Second, if devno is -1, the second key (i.e. devno) is not |
288 | * used for the match and the result of the claim() function |
314 | * used for the match and the result of the claim() function |
289 | * is used instead. |
315 | * is used instead. |
290 | * |
316 | * |
291 | * This function assumes interrupts are already disabled. |
317 | * This function assumes interrupts are already disabled. |
292 | * |
318 | * |
293 | * @param key Keys (i.e. inr and devno). |
319 | * @param key Keys (i.e. inr and devno). |
294 | * @param keys This is 2. |
320 | * @param keys This is 2. |
295 | * @param item The item to compare the key with. |
321 | * @param item The item to compare the key with. |
296 | * |
322 | * |
297 | * @return True on match or false otherwise. |
323 | * @return True on match or false otherwise. |
298 | */ |
324 | */ |
299 | bool irq_ht_compare(unative_t key[], count_t keys, link_t *item) |
325 | bool irq_ht_compare(unative_t key[], count_t keys, link_t *item) |
300 | { |
326 | { |
301 | irq_t *irq = hash_table_get_instance(item, irq_t, link); |
327 | irq_t *irq = hash_table_get_instance(item, irq_t, link); |
302 | inr_t inr = (inr_t) key[KEY_INR]; |
328 | inr_t inr = (inr_t) key[KEY_INR]; |
303 | devno_t devno = (devno_t) key[KEY_DEVNO]; |
329 | devno_t devno = (devno_t) key[KEY_DEVNO]; |
304 | 330 | ||
305 | bool rv; |
331 | bool rv; |
306 | 332 | ||
307 | spinlock_lock(&irq->lock); |
333 | spinlock_lock(&irq->lock); |
308 | if (devno == -1) { |
334 | if (devno == -1) { |
309 | /* Invoked by irq_dispatch_and_lock(). */ |
335 | /* Invoked by irq_dispatch_and_lock(). */ |
310 | rv = ((irq->inr == inr) && |
336 | rv = ((irq->inr == inr) && |
311 | (irq->claim(irq->instance) == IRQ_ACCEPT)); |
337 | (irq->claim(irq) == IRQ_ACCEPT)); |
312 | } else { |
338 | } else { |
313 | /* Invoked by irq_find_and_lock(). */ |
339 | /* Invoked by irq_find_and_lock(). */ |
314 | rv = ((irq->inr == inr) && (irq->devno == devno)); |
340 | rv = ((irq->inr == inr) && (irq->devno == devno)); |
315 | } |
341 | } |
316 | 342 | ||
317 | /* unlock only on non-match */ |
343 | /* unlock only on non-match */ |
318 | if (!rv) |
344 | if (!rv) |
319 | spinlock_unlock(&irq->lock); |
345 | spinlock_unlock(&irq->lock); |
320 | 346 | ||
321 | return rv; |
347 | return rv; |
322 | } |
348 | } |
323 | 349 | ||
324 | /** Compute hash index for the key. |
350 | /** Compute hash index for the key. |
325 | * |
351 | * |
326 | * This function computes hash index into |
352 | * This function computes hash index into |
327 | * the IRQ hash table for which there |
353 | * the IRQ hash table for which there |
328 | * are no collisions between different |
354 | * are no collisions between different |
329 | * INRs. |
355 | * INRs. |
330 | * |
356 | * |
331 | * @param key The first of the keys is inr and the second is devno or -1. |
357 | * @param key The first of the keys is inr and the second is devno or -1. |
332 | * |
358 | * |
333 | * @return Index into the hash table. |
359 | * @return Index into the hash table. |
334 | */ |
360 | */ |
335 | index_t irq_lin_hash(unative_t key[]) |
361 | index_t irq_lin_hash(unative_t key[]) |
336 | { |
362 | { |
337 | inr_t inr = (inr_t) key[KEY_INR]; |
363 | inr_t inr = (inr_t) key[KEY_INR]; |
338 | return inr; |
364 | return inr; |
339 | } |
365 | } |
340 | 366 | ||
341 | /** Compare hash table element with a key. |
367 | /** Compare hash table element with a key. |
342 | * |
368 | * |
343 | * There are two things to note about this function. |
369 | * There are two things to note about this function. |
344 | * First, it is used for the less complex architecture setup |
370 | * First, it is used for the less complex architecture setup |
345 | * in which there are not too many interrupt numbers (i.e. inr's) |
371 | * in which there are not too many interrupt numbers (i.e. inr's) |
346 | * to arrange the hash table so that collisions occur only |
372 | * to arrange the hash table so that collisions occur only |
347 | * among same inrs of different devnos. So the explicit check |
373 | * among same inrs of different devnos. So the explicit check |
348 | * for inr match is not done. |
374 | * for inr match is not done. |
349 | * Second, if devno is -1, the second key (i.e. devno) is not |
375 | * Second, if devno is -1, the second key (i.e. devno) is not |
350 | * used for the match and the result of the claim() function |
376 | * used for the match and the result of the claim() function |
351 | * is used instead. |
377 | * is used instead. |
352 | * |
378 | * |
353 | * This function assumes interrupts are already disabled. |
379 | * This function assumes interrupts are already disabled. |
354 | * |
380 | * |
355 | * @param key Keys (i.e. inr and devno). |
381 | * @param key Keys (i.e. inr and devno). |
356 | * @param keys This is 2. |
382 | * @param keys This is 2. |
357 | * @param item The item to compare the key with. |
383 | * @param item The item to compare the key with. |
358 | * |
384 | * |
359 | * @return True on match or false otherwise. |
385 | * @return True on match or false otherwise. |
360 | */ |
386 | */ |
361 | bool irq_lin_compare(unative_t key[], count_t keys, link_t *item) |
387 | bool irq_lin_compare(unative_t key[], count_t keys, link_t *item) |
362 | { |
388 | { |
363 | irq_t *irq = list_get_instance(item, irq_t, link); |
389 | irq_t *irq = list_get_instance(item, irq_t, link); |
364 | devno_t devno = (devno_t) key[KEY_DEVNO]; |
390 | devno_t devno = (devno_t) key[KEY_DEVNO]; |
365 | bool rv; |
391 | bool rv; |
366 | 392 | ||
367 | spinlock_lock(&irq->lock); |
393 | spinlock_lock(&irq->lock); |
368 | if (devno == -1) { |
394 | if (devno == -1) { |
369 | /* Invoked by irq_dispatch_and_lock() */ |
395 | /* Invoked by irq_dispatch_and_lock() */ |
370 | rv = (irq->claim(irq->instance) == IRQ_ACCEPT); |
396 | rv = (irq->claim(irq) == IRQ_ACCEPT); |
371 | } else { |
397 | } else { |
372 | /* Invoked by irq_find_and_lock() */ |
398 | /* Invoked by irq_find_and_lock() */ |
373 | rv = (irq->devno == devno); |
399 | rv = (irq->devno == devno); |
374 | } |
400 | } |
375 | 401 | ||
376 | /* unlock only on non-match */ |
402 | /* unlock only on non-match */ |
377 | if (!rv) |
403 | if (!rv) |
378 | spinlock_unlock(&irq->lock); |
404 | spinlock_unlock(&irq->lock); |
379 | 405 | ||
380 | return rv; |
406 | return rv; |
381 | } |
407 | } |
382 | 408 | ||
383 | /** @} |
409 | /** @} |
384 | */ |
410 | */ |
385 | 411 |